ESDALC5-1BT2

ESDALC5-1BT2, ESDALC5-1BM2 Datasheet Single-line low capacitance Transil, transient surge voltage suppressor (TVS) for ESD protection Features • • • • • • • • Single-line bidirectional protection Breakdown voltage = 5.8 V min. Low capacitance = 26 pF at 0 V Lead-free packages ECOPACK2 compliant component Benefits – Low capacitance for optimized data integrity – Low leakage current < 60 nA – Low PCB space consumption: 0.6 mm² – High reliability offered by monolithic integration Complies with IEC 61000-4-2 (exceeds level 4) – ±30 kV (air discharge) – ±30 kV (contact discharge) Complies MIL STD 883G - Method 3015-7: class 3 – Human body model Application Where transient overvoltage protection in ESD sensitive equipment is required, such as: Product status link ESDALC5-1BT2, ESDALC5-1BM2 • • • • • Computers Printers Communication systems Cellular phone handsets and accessories Video equipment Description The ESDALC5-1BM2 (SOD882) and ESDALC5-1BT2 (SOD882T) are bidirectional single-line TVS diodes designed to protect data lines or other I/O ports against ESD transients. These devices are ideal for applications where both reduced line capacitance and board space saving are required. DS6658 - Rev 7 - July 2023 For further information contact your local STMicroelectronics sales office. www.st.com ESDALC5-1BT2, ESDALC5-1BM2 Characteristics 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value IEC 61000-4-2: contact discharge 30 IEC 61000-4-2: air discharge 30 VPP Peak pulse voltage PPP Peak pulse power dissipation (8/20 µs), Tj initial = Tamb IPP Peak Pulse current (8/20 µs) Tstg Unit kV 150 W 9 A Storage temperature range -65 to +150 °C Tj Junction temperature -55 to +150 °C TL Maximum lead temperature for soldering during 10 s 260 °C Figure 1. Electrical characteristics (definitions) Table 2. Electrical characteristics (values) (Tamb = 25° C) Symbol VBR IRM Test conditions Min. Typ. Max. From I/O1 to I/O2, IR = 1 mA 11 13 17 From I/O2 to I/O1, IR = 1 mA 5.8 8 11 VR = 5 V 60 Unit V nA Dynamic resistance, pulse width 100 ns Rd From I/O1 to I/O2 From I/O2 to I/O1 0.25 Ω 0.23 8 kV contact discharge after 30 ns IEC 61000 4-2: VCL From I/O1 to I/O2 From I/O2 to I/O1 CLINE DS6658 - Rev 7 F = 1 MHz, VR = 0 V 16 V 11 26 30 pF page 2/13 ESDALC5-1BT2, ESDALC5-1BM2 Characteristics (curves) 1.1 Characteristics (curves) Figure 2. Peak pulse power versus initial junction temperature (maximum values) Figure 3. Leakage current versus junction temperature (typical values) PPP (W) 250 IR (nA) 1000 225 V R = V RM = 5 V from I/O1 to I/O2 8/20µs 100 200 175 10 150 125 1 100 75 0.1 50 25 Tj (°C) Tj (°C) 0.01 0 0 25 50 75 100 125 150 Figure 4. Leakage current versus junction temperature (typical values) 1000 25 175 IR (nA) 50 75 100 125 150 Figure 5. Peak pulse power versus exponential pulse duration (direct) 10000 PPP(W) V R = V RM = 5 V from I/O2 to I/O1 100 1000 10 100 1 10 0.1 T j (°C) 0.01 25 50 75 100 1 150 125 Figure 6. Clamping voltage versus peak pulse current (typical values) 10 IPP (A) 10 100 1000 Figure 7. Clamping voltage versus peak pulse current (typical values) IPP (A) 10 8/20µs T j initial = 25 °C From I/O1 to I/O2 8/20µs T j initial = 25 °C From I/O2 to I/O1 1 1 VCL(V) VCL(V) 0,1 TP(µs) 1 12 13 DS6658 - Rev 7 14 15 16 17 18 19 20 21 22 0.1 23 7 8 9 10 11 12 13 14 15 16 page 3/13 ESDALC5-1BT2, ESDALC5-1BM2 Characteristics (curves) Figure 8. Junction capacitance versus reverse applied voltage (typical values from I/O1 to I/O2) Figure 9. Junction capacitance versus reverse applied voltage (typical values from I/O2 to I/O1) C(pF) C(pF) 35 35 T j = 25 °C F = 1 MHz Vosc = 30 mV from I/O1 to I/O2 30 T j = 25 °C F = 1 MHz Vosc = 30 mV from I/O2 to I/O1 30 25 25 20 20 15 15 10 10 5 5 VR(V) 0 0 1 2 3 4 VR (V) 0 5 Figure 10. ESD response to IEC 61000-4-2 (+8 kV air discharge) 0 1 3 4 5 Figure 11. ESD response to IEC 61000-4-2 (-8 kV air discharge) Figure 12. S21 attenuation measurement result 0 2 Figure 13. TLP measurements dB I PP (A) 20 -5 18 - 10 16 from I/O2 to I/O1 14 - 15 12 - 20 10 - 25 8 6 - 30 from I/O1 to I/O2 4 - 35 2 F(Hz) - 40 100k DS6658 - Rev 7 1M 10M 100M 1G V CL (V) 0 0 5 10 15 20 25 page 4/13 ESDALC5-1BT2, ESDALC5-1BM2 Package information 2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 2.1 SOD882 package information Figure 14. SOD882 package outline Table 3. SOD882 package mechanical data Dimensions Millimeters Ref. DS6658 - Rev 7 Inches Min. Typ. Max. Min. Typ. Max. A 0.40 0.47 0.50 0.016 0.019 0.020 A1 0.00 0.05 0.000 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 D 0.95 1.00 1.05 0.037 0.039 0.041 E 0.55 0.60 0.65 0.022 0.024 0.026 e 0.60 0.65 0.70 0.024 0.026 0.028 L1 0.20 0.25 0.30 0.008 0.010 0.012 L2 0.20 0.25 0.30 0.008 0.010 0.012 0.002 page 5/13 ESDALC5-1BT2, ESDALC5-1BM2 SOD882 package information Figure 15. Recommended footprint Note: Figure 16. Marking layout Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 17. Tape outline DS6658 - Rev 7 page 6/13 ESDALC5-1BT2, ESDALC5-1BM2 SOD882T package information 2.2 SOD882T package information Figure 18. SOD882T package outline Table 4. SOD882T package mechanical data Dimensions Millimeters Ref. Min. DS6658 - Rev 7 Typ. Inches Max. Min. Typ. Max. A 0.30 0.40 0.012 0.016 A1 0.00 0.05 0.000 0.002 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 D 0.95 1.00 1.05 0.037 0.039 0.041 E 0.55 0.60 0.65 0.022 0.024 0.026 e 0.60 0.65 0.70 0.024 0.026 0.028 L1 0.20 0.25 0.30 0.008 0.010 0.012 L2 0.20 0.25 0.30 0.008 0.010 0.012 page 7/13 ESDALC5-1BT2, ESDALC5-1BM2 SOD882T package information Figure 19. Recommended footprint Note: Figure 20. Marking layout Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 21. Tape outline DS6658 - Rev 7 page 8/13 ESDALC5-1BT2, ESDALC5-1BM2 Recommendations on PCB assembly 3 Recommendations on PCB assembly 3.1 Stencil opening design Stencil opening thickness: 100 μm Figure 22. Recommended stencil window position in mm (inches) 3.2 Solder paste 1. 2. 3. 4. 3.3 Placement 1. 2. 3. 4. 5. 6. 3.4 Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. Standard tolerance of ± 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. 2. DS6658 - Rev 7 Halide-free flux, qualification ROL0 according to ANSI/J-STD-004. “No clean” solder paste recommended. Offers a high tack force to resist component movement during high speed. Solder paste with fine particles: powder particle size is 20-38 μm. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is paste printing, pick and place and reflow soldering by using optimized tools. page 9/13 ESDALC5-1BT2, ESDALC5-1BM2 Reflow profile 3.5 Reflow profile Figure 23. ST ECOPACK recommended soldering reflow profile for PCB mounting 250 240-245 °C Temperature (°C) -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: DS6658 - Rev 7 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020. page 10/13 ESDALC5-1BT2, ESDALC5-1BM2 Ordering information 4 Ordering information Figure 24. Ordering information scheme Table 5. Ordering information Order code Marking(1) Package Weight Base qty. Delivery mode ESDALC5-1BM2 G SOD882 0.93 mg 12000 Tape and reel ESDALC5-1BT2 H SOD882T 0.82 mg 12000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location DS6658 - Rev 7 page 11/13 ESDALC5-1BT2, ESDALC5-1BM2 Revision history Table 6. Document revision history Date Version Changes 02-Feb-2010 1 Initial release. 06-Jun-2012 2 Updated Figure 11, Figure 12, Figure 15, Figure 19, Table 3, and Table 4. Updated note in page 7, 8 and 13. Updated IRM in Table 2. 05-Mar-2013 3 Clamping voltage at 30 ns added in Table 2. 09-Jan-2014 4 Updated Table 1, Table 2, Table 5, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 16, Figure 17, Figure 20, Figure 21 and Figure 24. Added Figure 14. 02-Apr-2014 5 Updated Figure 4 and Figure 5. 28-Nov-2016 6 Updated cover image, Table 2: "Electrical characteristics (Tamb = 25 °C)" and Figure 2: "Electrical characteristics (definitions)". 04-Jul-2023 7 Updated Section Cover image, Section 2.1 SOD882 package information, and Section 2.2 SOD882T package information. Minor text changes. DS6658 - Rev 7 page 12/13 ESDALC5-1BT2, ESDALC5-1BM2 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2023 STMicroelectronics – All rights reserved DS6658 - Rev 7 page 13/13