ESDALC6V1-5P6

ESDALC6V1-5P6 ESD protection for high speed interface Features ■ ■ ■ Diode array topology Low capacitance (12 pF typical) Lead-free package SOT666 Benefits ■ ■ ■ ■ Low capacitance uni-directional ESD protection. Low PCB space consuming, 2.5 mm2 max. footprint Low leakage current High reliability offered by monolithic integration Figure 1. ESDALC6V1-5P6 functional diagram Complies with the following standards ■ IEC 61000-4-2 level 4: – 8 kV (contact discharge) – 15 kV (air discharge) MIL STD 883G-Method 3015-7: class3B – Human body model ■ Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ ■ ■ ■ ■ Computers Printers Communication systems Cellular phone handsets and accessories Video equipment Description The ESDALC6V1-5P6 is a monolithic array designed to protect up to 5 lines against ESD transients. The device is ideal for high speed interface applications where both reduced printed circuit board space and power absorption capability are required. November 2007 Rev 3 1/8 www.st.com 8 Characteristics ESDALC6V1-5P6 1 Characteristics Table 1. Symbol VPP(1) PPP (1) IPP Tj Tstg TL TOP Peak pulse voltage Absolute ratings (Tamb = 25 °C) Parameter IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge Tj initial = Tamb Value ±8 ± 15 30 2.5 125 -55 to +150 260 - 40 + 125 Unit kV W A °C °C °C °C Peak pulse power dissipation (8/20 µs) Peak pulse current (8/20 µs) Junction temperature Storage temperature range Maximum lead temperature for soldering during 10 s Operating temperature range 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Table 2. Symbol VRM VBR VCL IRM IPP αT VF C Rd Parameter VRRM VBR IRM VCL VF Rd αT (1) Electrical characteristics (Tamb = 25 °C) Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Forward voltage drop Capacitance Dynamic resistance Test condition Reverse stand-off voltage IR = 1 mA VRM = 3 V Non repetitive peak pulse voltage (8/20 µs) IF = 10 mA 2 IR = 1 mA VR = 0 V DC, F = 1 MHz, Vosc = 30 mV rms 12 IPP = 1 A IPP = 2.5 A 6.1 Min Typ Max 5 7.2 70 10 V 14 1 3 5 15 V Ω 10-4/°C pF Unit V V nA Slope: 1/Rd IPP VF VCL VBR VRM IRM V IF I C 1. ΔVBR = αT x (Tamb - 25 °C) x VBR (25 °C) 2/8 ESDALC6V1-5P6 Characteristics Figure 2. Relative variation of peak pulse power versus initial junction temperature Figure 3. Peak pulse power versus exponential pulse duration (Tj initial = 25 °C) Tj initial = 25°C PPP[Tj initial] / PPP[Tj initial=25°C) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 100 1000 PPP(W) Tj(°C) 10 1 tp(µs) 10 100 Figure 4. Clamping voltage versus peak pulse current (typical values) Figure 5. Relative variation of leakage current versus junction temperature (typical values) IPP(A) 10.0 8/20 µs Tj initial = 25°C IR[Tj] / IR[Tj=25°C] 1000 VR=3V 100 1.0 10 VCL(V) 0.1 5 6 7 8 9 10 11 12 13 14 15 1 25 50 75 Tj(°C) 100 125 150 Figure 6. Breakdown voltage versus initial junction temperature Figure 7. Junction capacitance versus reverse voltage applied (typical values) VBR 8.0 1 mA C(pF) 14 12 10 8 F=1MHz VOSC=30mVRMS Tj=25°C 7.0 6 4 2 Tj(°C) 6.0 25 50 75 100 125 0 0.0 0.4 0.8 VR(V) 1.2 1.6 2.0 2.4 2.8 3/8 Characteristics ESDALC6V1-5P6 Figure 8. ESD response to IEC 61000-4-2 (air discharge +15 kV surge) Figure 9. ESD response to IEC 61000-4-2 (air discharge -15 kV surge) 10 V per div. 10 V per div. 0.1 µs per division 0.1 µs per division Figure 10. Frequency response curves - all lines together dB 0.00 Figure 11. Crosstalk response curves - 1/2 and 1/3 dB 0.00 - 20.00 - 6.00 - 40.00 - 12.00 - 60.00 - 18.00 - 80.00 - 100.00 - 24.00 F (Hz) - 30.00 100.0k Line 1 Line 3 1.0M 10.0M 100.0M Line 2 Line 5 1.0G - 120.00 F (Hz) 100.0k Xtalk 1/2 1.0M 10.0M 100.0M Xtalk 1/3 1.0G - 140.00 4/8 ESDALC6V1-5P6 Application information 2 Application information Figure 12. Application schematic diagram V DD IMAGE PROCESSING SDA Image Sensor Sensor Controller View finder FrontEnd JPEG Encoder SCL EN DCLCK D0 D1 D2 D3 D4 D5 D6 D7 I2C BUS (115kbs) I2C BUS (115 ) khz BB interface BB IC BB IC HSYNC VSYNC FLASH MEMORY 3 Ordering information scheme Figure 13. Ordering information scheme ESDA ESD Array Low Capacitance Breakdown Voltage (min) 6V1 = 6.1 Volt Number of lines protected 5 Package P6 = SOT666 LC 6V1 - 5 P6 5/8 Package information ESDALC6V1-5P6 4 Package information ● Epoxy meets UL 94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 3. SOT666 dimensions Dimensions b1 L1 Ref. Millimeters Min. Typ. Max. Min. Inches Typ. Max. 0.024 0.007 0.013 L3 b A A3 b D E1 0.45 0.08 0.17 0.19 1.50 1.50 1.10 0.50 0.19 0.10 0.10 0.27 0.60 0.018 0.18 0.003 0.34 0.007 b1 D 0.34 0.007 0.011 0.013 1.70 0.059 1.70 0.059 1.30 0.043 0.020 0.007 0.30 0.004 0.004 0.012 0.067 0.067 0.051 A E L2 E A3 E1 e L1 L2 e L3 Figure 14. SOT666 footprint (dimensions in mm) 0.50 0.62 2.60 0.99 0.30 6/8 ESDALC6V1-5P6 Figure 15. Tape and reel specifications Dot identifying Pin A1 location 4 ± 0.1 Ordering information Ø 1.5 ± 0.1 1.75 ± 0.1 3.5 ± 0.1 0.69 ± 0.05 All dimensions in mm 8 ± 0.3 4 ± 0.1 User direction of unreeling Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. 5 Ordering information Table 4. Ordering information Marking J(1) Package SOT666 Weight 2.9 mg Base qty 3000 Delivery mode Tape and reel Order code ESDALC6V1-5P6 1. The marking can be rotated by 90° to diferentiate assembly location 6 Revision history Table 5. Date 29-May-2007 30-Jul-2007 15-Nov-2007 Document revision history Revision 1 2 3 First issue. Upgrade VCL from 8 V to 10 V and from 9.5 V to 14 V. Reformatted to current standards. Marking changed to J in Table 4. Notes on marking rotation added to Table 4 and Figure 15. Description of changes 7/8 ESDALC6V1-5P6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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