ESDALC6V1M3

ESDALC6V1M3 Dual low capacitance Transil™ array for ESD protection Features ■ 2 unidirectional, low capacitance Transil diodes ■ Better than IEC 61000-4-2 standard (ESD protection: 11 kV contact discharge) ■ Breakdown voltage VBR = 6.1 V min ■ Low diode capacitance (11 pF typ at 0 V) ■ Low leakage current < 0.5 µA ■ Very small PCB area: 0.6 mm2 ■ RoHS compliant SOT883 (JEDEC MO-236AA) Figure 1. Functional diagram Benefits ■ High ESD protection level ■ High integration ■ Suitable for high density boards I/O2 ■ I/O1 GND 3 Complies with the following standards ■ 12 2 1 2 IEC61000-4-2 level 4: – 15 kV (air discharge) – 8 kV (contact discharge) GND Underside view MIL STD 883G-Method 3015-7: class 3B: – HBM (human body model) Description The ESDALC6V1M3 is a monolithic array designed to protect 1 line or 2 lines against ESD transients. Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems ■ Cellular phone handsets and accessories ■ Video equipment The device is ideal for applications where both reduced line capacitance and board space saving are required. TM: Transil is a trademark of STMicroelectronics October 2010 Doc ID 11555 Rev 5 1/12 www.st.com 12 Characteristics 1 ESDALC6V1M3 Characteristics Table 1. Absolute ratings (Tamb = 25 °C) Symbol Parameter IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge Value Unit ± 15 ± 11 kV 30 W VPP Peak pulse voltage PPP Peak pulse power dissipation (8/20 µs)(1) Ipp Repetitive peak pulse current (8/20 µs) 3 A Tj Operating junction temperature range -40 + 125 °C Storage temperature range -55 + 150 °C 260 °C Tstg TL Tj initial = Tamb Maximum lead temperature for soldering during 10 s 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Electrical characteristics (definitions) I Symbol VBR IRM VRM VCL Rd IPP IR αT VF 2/12 = = = = = = = = = Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Breakdown current Voltage temperature coefficient Forward voltage drop IF VF VCL VBR VRM Slope = 1/Rd Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Test condition V IRM IR Min. IPP Typ. 6.1 Max. Unit 7.2 V VBR IR = 1 mA IRM VRM = 5 V 0.5 µA αT IR = 1 mA 4.2 10-4/°C C VR = 0 V, F = 1 MHz, VOSC = 30 mV Doc ID 11555 Rev 5 11 pF ESDALC6V1M3 Figure 3. Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 4. PPP[Tj initial] /PPP[Tj initial=25°C] 1.1 1000 Peak pulse power versus exponential pulse duration PPP(W) Tj initial = 25 °C 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 Tj(°C) 0 25 Figure 5. 10.0 tp(µs) 10 0.0 50 75 100 125 1 150 Clamping voltage versus peak pulse current (typical values) 10 Figure 6. IPP(A) 1.E+00 100 Forward voltage drop versus peak forward current (typical values) IFM(A) 8/20 µs Tinitial = 25 °C Tj = 25 °C Tj = 125 °C Tj = -40 °C 1.E-01 1.0 VCL(V) 0.1 6 7 Figure 7. 8 9 10 11 Junction capacitance versus reverse voltage applied (typical values) 1.E-02 0.6 Figure 8. C(pF) 12 100 F=1 MHz VOSC = 30 mVRMS Tj = 25 °C 11 10 VFM(V) 0.8 1.0 1.2 1.4 1.6 1.8 Variation of leakage current versus junction temperature (typical values) IR(nA) VR = 5 V 90 80 9 8 70 7 60 6 50 5 40 4 30 3 20 2 VLINE (V) 1 10 0 0 1 2 3 4 5 6 Tj(°C) 0 25 Doc ID 11555 Rev 5 50 75 100 125 3/12 Characteristics Figure 9. ESDALC6V1M3 ESD response to IEC61000-4-2 (+15 kV air discharge) on each channel Figure 11. S21 attenuation measurement results of each channel Figure 10. ESD response to IEC61000-4-2 (-15 kV air discharge) on each channel Figure 12. Analog crosstalk measurements between channels dB dB 0.00 0.00 - 10.00 - 30.00 - 20.00 - 60.00 - 30.00 - 90.00 F (Hz) F (Hz) - 40.00 100.0k - 120.00 1.0M 10.0M 100.0M 100.0k 1.0G 4/12 1.0M Xtalk Att 1 Doc ID 11555 Rev 5 10.0M 100.0M 1.0G ESDALC6V1M3 2 Ordering information Ordering information Figure 13. Ordering information scheme ESDA LC 6V1 M3 ESD array Low capacitance Breakdown voltage 6V1 = 6.1 Volts min. Package M3 = SOT883 Doc ID 11555 Rev 5 5/12 Package information 3 ESDALC6V1M3 Package information ● Epoxy meets UL94, V0 ● Lead-free packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 3. SOT883 dimensions Dimensions L1 b1 Ref. L2 2 Min. 3 e b2 1 e1 A Max. Min. Typ. 0.50 0.016 0.02 A1 0.00 0.05 0.00 0.002 b1 0.10 0.15 0.20 0.004 0.006 0.007 b2 0.45 0.50 0.55 0.018 0.020 0.021 D 0.55 0.60 0.65 0.022 0.024 0.026 E 0.95 1.00 1.05 0.037 0.039 0.041 e 0.30 0.35 0.40 0.012 0.014 0.015 e1 0.60 0.65 0.70 0.024 0.026 0.027 L1 0.20 0.25 0.30 0.008 0.010 0.012 L2 0.20 0.25 0.30 0.008 0.010 0.012 Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 14. Footprint 0.40 Figure 15. Marking 0.40 2 0.20 K 0.70 0.25 0.30 1 All dimensions in mm 6/12 Max. 0.40 E D Typ. Inches A A1 Note: Millimeters Doc ID 11555 Rev 5 3 ESDALC6V1M3 Package information Figure 16. Packing information Cathode bar Ø 1.55 4.0 2.0 1.75 0.20 3.5 1.10 8.0 K K K 0.68 K K All dimensions in mm K K 0.6 2.0 User direction of unreeling Doc ID 11555 Rev 5 7/12 Recommendation on PCB assembly ESDALC6V1M3 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 17. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for leads: Opening to footprint ratio 90%. Figure 18. Recommended stencil window position 400 µm 236 µm 7 µm T=100 µm 380 µm 7 µm 10 µm 0.4 10 µm 10 µm 10 µm 0.4 0.20 18 µm 0.70 0.25 664 µm 700 µm 0.30 Footprint 380 µm 18 µm Stencil window Footprint 400 µm 8/12 Doc ID 11555 Rev 5 ESDALC6V1M3 4.2 4.3 4.4 Recommendation on PCB assembly Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Doc ID 11555 Rev 5 9/12 Recommendation on PCB assembly 4.5 ESDALC6V1M3 Reflow profile Figure 19. ST Ecopack® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 10/12 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 11555 Rev 5 ESDALC6V1M3 5 Ordering information Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDALC6V1M3 K(1) SOT883 0.86 mg 12000 Tape and reel 1. The marking can be rotated by 90° to differentiate assembly location 6 Revision history Table 5. Document revision history Date Revision Changes 04-Aug-2005 1 Initial release. 23-May-2006 2 Reformated to current standards. Added soldering reflow profile diagram. 16-Jun-2006 3 Updated tape and reel illustration (Figure 14). 18-Feb-2007 4 Reformatted to current standards. Added notes on marking rotation. Updated tape and reel illustration - Figure 16. Added Section 4: Recommendation on PCB assembly. Updated footprint in Figure 14. 26-Oct-2010 5 General revision on: figures (order and values), values and descriptions on the tables. Doc ID 11555 Rev 5 11/12 ESDALC6V1M3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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