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ESDALC8-1BF4

ESDALC8-1BF4

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    0201

  • 描述:

    TVS DIODE 6VWM 16VC 0201

  • 数据手册
  • 价格&库存
ESDALC8-1BF4 数据手册
ESDALC8-1BF4 Low clamping single line bidirectional ESD protection Datasheet − production data Features • Low clamping voltage: 16 V (IEC 61000-4-2 contact discharge 8 kV at 30 ns) • Bidirectional device • Low leakage current • 0201 package • Ultra small PCB area: 0.18 mm2 • ECOPACK®2 compliant component 0201 package Figure 1. Functional diagram Complies with the following standards • IEC 61000-4-2: – ±15 kV (air discharge) – ±8 kV (contact discharge) Applications Where transient over voltage protection in ESD sensitive equipment is required, such as: • Smartphones, mobile phones and accessories • Tablet, PC, netbooks and notebooks • Portable multimedia devices and accessories • Digital cameras and camcorders • Communication and highly integrated systems Description The ESDALC8-1BF4 is a bidirectional single line TVS diode designed to protect the data line or other I/O ports against ESD transients. The device is ideal for applications where both board space saving and high protection efficiency are required. Thanks to the strong IPP capability, this diode can also be used as a Vbus protection. April 2014 This is information on a product in full production. DocID025043 Rev 1 1/10 www.st.com Characteristics 1 ESDALC8-1BF4 Characteristics Table 1. Absolute maximum ratings Symbol Parameter IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge Value Unit 20 20 kV VPP (1) Peak pulse voltage PPP(1) Peak pulse power (8/20 µs) 165 W IPP(1) Peak pulse current (8/20 µs) 8.6 A Operating junction temperature range -40 to 125 °C Tstg Storage temperature range -65 to +150 °C TL Maximum lead temperature for soldering during 10 s 260 °C Tj 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Electrical characteristics (definitions) Symbol VBR VCL IRM VRM IPP Rd aT = = = = = Parameter Breakdown voltage Clamping voltage Leakage current @ VRM Stand-off voltage Peak pulse current = = Dynamic resistance Voltage temperature C LINE = IR = VCL VCL Slope: 1/Rd Line capacitance IPP Breakdown current Table 2. Electrical characteristics (values, Tamb = 25 °C) Value Symbol VBR IRM VCL C LINE 2/10 Unit Test conditions Min. Typ. Pin1 to Pin2, IR = 1 mA 11 13 Pin2 to Pin1, IR = 1 mA 7 9 Max. V Pin1 to Pin2, VRM = 9 V 50 Pin2 to Pin1, VRM = 6 V 50 nA 8 kV contact discharge after 30 ns, IEC 61000-4-2 (Pin2 to Pin1) 16 F = 1 MHz, VRM = 0 V 30 DocID025043 Rev 1 V 38 pF ESDALC8-1BF4 Characteristics Figure 3. Leakage current versus junction temperature (typical values) IR ( nA) 100 Figure 4. Junction capacitance versus applied voltage (typical values) 40.0 VR = VRM = 9 V direct and 6 V reverse C(pF) Tj = 25 °C F = 1 MHz Vosc = 30 mV direct and reverse 35.0 30.0 10 25.0 direct 20.0 15.0 reverse 1 10.0 5.0 Tj (°C) 0.1 25 50 75 100 125 0.0 150 Figure 5. ESD response to IEC 61000-4-2 (+8 kV contact discharge) VR (V) 0 1 2 3 4 5 6 Figure 6. ESD response to IEC 61000-4-2 (-8 kV contact discharge) 5 V/div 5 V/div 1 34 V 1 2 22 21 V 3 18 V 3 4 VCL: Peak clamping voltage VCL :clamping voltage at 30 ns VCL :clamping voltage at 60 ns VCL :clamping voltage at 100 ns 4 -3 V 4 15 V 3 -13 1 2 2 3 4 -16 V VCL: Peak clamping voltage VCL :clamping voltage at 30 ns VCL :clamping voltage at 60 ns VCL :clamping voltage at 100 ns 1 -29 V 20 ns/div 20 ns/div Figure 7. Dynamic resistance 25 Figure 8. S21 attenuation result measurements IPP (A) 0 S21 (dB) -3 -6 -9 20 -12 -15 15 -18 Positive polarity -21 Negative polarity 10 -24 -27 -30 5 -33 -36 VCL (V) 0 5 10 15 20 F (Hz) -39 0 25 100k DocID025043 Rev 1 1M 10M 100M 1G 10G ESDALC8-1BF4 3/10 10 Package information 2 ESDALC8-1BF4 Package information • Epoxy meets UL94, V0 • Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 9. 0201 package dimension definitions D E Top A Side fD D1 fE E1 Bottom Table 3. b 0201 package dimension values Dimensions Ref. Millimeters Min. Max. Min. Typ. Max. A 0.28 0.3 0.32 0.0110 0.0118 0.0126 b 0.125 0.14 0.155 0.0049 0.0055 0.0061 D 0.57 0.6 0.63 0.0224 0.0236 0.0248 D1 4/10 Typ. Inches 0.35 0.0138 E 0.27 0.3 0.33 0.0106 0.0118 0.0130 E1 0.175 0.19 0.205 0.0069 0.0075 0.0081 fD 0.065 0.08 0.095 0.0026 0.0031 0.0037 fE 0.11 0.125 0.13 0.0043 0.0049 0.0051 DocID025043 Rev 1 ESDALC8-1BF4 Package information Figure 10. Footprint dimensions in mm (inches) 0.656 (0.0258) 0.243 (0.0096) E 0.243 (0.0096) Figure 11. Marking Pin1 0.300 (0.0118) Pin2 0.170 (0.0067) The marking codes can be rotated by 90° or 180° to differentiate assembly location.In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 12. Tape and reel specification Ø 1.5 ± 0.1 2.0 ± 0.05 4.0 ± 0.1 0.36 ± 0.03 3.5 ± 0.05 0.68 ± 0.03 0.22 1.75 ± 0.1 Bar indicates Pin 1 8.0 + 0.03 - 0.01 Note: E E E E E E E 0.38 ± 0.03 2.0 ± 0.05 All dimensions in mm User direction of unreeling DocID025043 Rev 1 5/10 10 Recommendation on PCB assembly ESDALC8-1BF4 3 Recommendation on PCB assembly 3.1 Stencil opening design 1. General recommendations on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 13. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1,5 T L×W Aspect Area = ---------------------------- ≥ 0,66 2T ( L + W ) 2. Recommended stencil window a) Stencil opening thickness: 80 µm b) Other dimensions: see Figure 14 Figure 14. Recommended stencil window position, stencil opening thickness: 80 µm 0.230 (0.0091) 0.643 (0.0253) 0.183 (0.0072) 0.285 (0.0112) 0.008 (0.0003) 0.300 (0.0118) 0.008 (0.0003) 0.656 (0.0258) 0.007 0.007 (0.00027) (0.00027) 0.170 (0.0067) 0.243 (0.0096) mm (inches) Footprint 6/10 DocID025043 Rev 1 Stencil window ESDALC8-1BF4 3.2 3.3 3.4 Recommendation on PCB assembly Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: Type 4 (powder particle size 20-48 µm per IPC J STD-005). Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 1.0 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. DocID025043 Rev 1 7/10 10 Recommendation on PCB assembly 3.5 ESDALC8-1BF4 Reflow profile Figure 15. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 8/10 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. DocID025043 Rev 1 ESDALC8-1BF4 4 Ordering information Ordering information Figure 16. Ordering information scheme ESDA LC 8 - 1 B F4 ESDA array Low capacitance Breakdown voltage 8 = 7 V min Number of lines Directional B = Bi-directional Package F4 = 0201 Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDALC8-1BF4 E(1) 0201 0.116 mg 15000 Tape and reel 1. The marking codes can be rotated by 90° or 180° to differentiate assembly location 5 Revision history Table 5. Document revision history Date Revision 08-Apr-2014 1 Changes First issue DocID025043 Rev 1 9/10 10 ESDALC8-1BF4 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 10/10 DocID025043 Rev 1
ESDALC8-1BF4 价格&库存

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