ESDALCL5-1BM2

ESDALCL5-1BM2 Single-line low capacitance and low leakage current ESD protection Datasheet − production data Features ■ Single-line low capacitance Transil diode ■ Bidirectional ESD protection ■ Breakdown voltage VBR = 5.0 V min. ■ Low diode capacitance (26 pF typ at 0 V) ■ Low leakage current: – 10 nA at 3 V – 1 nA at 1 V ■ Very small PCB area: 0.6 mm² ■ ECOPACK®2 compliant components SOD882 ESDALC5-1BM2 Complies with the following standards: ■ ■ Figure 1. Functional diagram IEC 61000-4-2 level 4 and higher – 30 kV (air discharge) – 30 kV (contact discharge) I/O1 MIL STD 883G - Method 3015-7: class 3 – Human body model I/O2 Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Portable multimedia players and accessories ■ Portable healthcare equipment ■ Notebooks ■ Communication systems ■ Cellular phone handsets and accessories October 2012 This is information on a product in full production. Description The ESDALCL5-1BM2 is a bidirectional singleline TVS diode designed to protect data lines or other I/O ports against ESD transients. This device is ideal for applications where reduced line capacitance and board space saving are required. Its low leakage current makes it suitable for portable equipment. Doc ID 023846 Rev 1 1/12 www.st.com 12 Characteristics 1 ESDALCL5-1BM2 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol VPP PPP(1) Parameter Peak pulse voltage Value Unit ±30 kV 150 W 9 A IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge Peak pulse power dissipation (8/20 µs) Tj initial = Tamb IPP Peak pulse current (8/20 µs) Tj Junction temperature -55 to +150 °C Storage temperature range -65 to +150 °C 260 °C Tstg TL Maximum lead temperature for soldering during 10 s 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Symbol VBR VCL IRM VRM IPP IR Cline Table 2. Electrical characteristics (definitions) = = = = = = = Parameter Breakdown voltage Clamping voltage Leakage current at VRM Stand-off voltage Peak pulse current Breakdown current Input capacitance per line IRM Rd Cline 2/12 VBR VRM IR IRM IRM IR VRM V VBR Electrical characteristics (values, Tamb = 25 °C) Symbol VBR I Test condition Min. Typ. From pin1 to pin2, IR = 1 mA 11 13 From pin2 to pin1, IR = 1 mA 5 8 Max. Unit V VRM = 3 V 10 VRM = 1 V 1 nA Square pulse, IPP = 1 A, tp = 2.5 µs 650 F = 1 MHz, VR = 0 V 26 Doc ID 023846 Rev 1 mΩ 30 pF ESDALCL5-1BM2 Figure 3. 1.1 Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 4. PPP[Tjinitial]/PPP[Tjinitial = 25°C] Leakage current versus junction temperature (typical values, VR = 1 V) IR(pA) 1.0 0.9 0.8 1000 0.7 0.6 100 0.5 0.4 10 0.3 0.2 Tj(°C) 0.1 0.0 Tj(°C) 0 25 Figure 5. 50 75 100 125 1 0 20 40 60 80 100 120 140 150 Leakage current versus reverse applied voltage (typical values) Figure 6. IR(µA) Peak pulse power versus exponential pulse duration (direct) PPP(W) 10000 100 60 1000 20 100 -20 10 -60 VR(V) -100 -14 -12 -10 Figure 7. 10000 -8 -6 -4 -2 0 2 4 6 8 TP(µs) 1 10 1 Peak pulse power versus exponential pulse duration (reverse) 10 Figure 8. PPP(W) 100.0 100 1000 Clamping voltage versus peak pulse current (typical values, exponential waveform, direct) IPP(A) 1000 10.0 100 1.0 10 TP(µs) 1 1 10 100 1000 0.1 VCL(V) 8 Doc ID 023846 Rev 1 10 12 14 16 18 20 22 3/12 Characteristics Figure 9. ESDALCL5-1BM2 Clamping voltage versus peak pulse current (typical values, exponential waveform, reverse) Figure 10. Junction capacitance versus reverse applied voltage (typical values, direct) IPP(A) 100.0 50 C(pF) 40 10.0 30 20 1.0 10 VCL(V) 0.1 6 8 10 12 14 16 Figure 11. Junction capacitance versus reverse applied voltage (typical values, reverse) 50 VLINE(V) 0 0 1 2 3 4 Figure 12. ESD response to IEC 61000-4-2 (+30 kV contact discharge) C(pF) 20 V/div VPP: ESD peak voltage VCL :clamping voltage at 30 ns VCL :clamping voltage at 60 ns 4V CL :clamping voltage at 100 ns 1 2 3 40 97 V 1 30 20 21 V 2 25 V 3 16 V 4 10 VLINE(V) 0 0 1 2 3 4 20 ns/div 5 Figure 13. ESD response to IEC 61000-4-2 (-30 kV contact discharge) Figure 14. S21 attenuation measurement result 0 20 V/div dB -5 - 10 -11 V -13 V2 -18 V - 15 4 3 - 20 - 25 -86 V 1 VPP: ESD peak voltage VCL :clamping voltage @ 30 ns 3 VCL :clamping voltage @ 60 ns 4 VCL :clamping voltage @ 100 ns 1 - 30 2 20 ns/div - 35 F(Hz) - 40 100k 4/12 Doc ID 023846 Rev 1 1M 10M 100M 1G 5 ESDALCL5-1BM2 2 Ordering information scheme Ordering information scheme Figure 15. Ordering information scheme ESDA LC L 5 - 1 B M2 ESD array Low capacitance Low leakage Breakdown voltage 5 = 5 Volts minimum Number of lines 1 = 1 line protected Directional B = Bi-directional Package M2 = SOD882 Doc ID 023846 Rev 1 5/12 Package information 3 ESDALCL5-1BM2 Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 16. SOD882 dimension definitions L1 L2 b1 b2 PIN # 1 ID e A A1 E D Table 3. SOD882 dimension values Dimensions Ref. 6/12 Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.40 0.47 0.50 0.016 0.019 0.020 A1 0.00 0.05 0.000 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 D 0.55 0.60 0.65 0.022 0.024 0.026 E 0.95 1.00 1.05 0.037 0.039 0.041 e 0.60 0.65 0.70 0.024 0.026 0.028 L1 0.20 0.25 0.30 0.008 0.010 0.012 L2 0.20 0.25 0.30 0.008 0.010 0.012 Doc ID 023846 Rev 1 0.002 ESDALCL5-1BM2 Package information Figure 17. SOD882 footprint in mm (inches) 0.55 (0.022) Figure 18. SOD882 marking 0.55 (0.022) 0.50 0.020 S Pin1 Pin 2 0.40 (0.016) Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 19. SOD882 tape and reel specifications Cathode bar 2.0 Ø 1.50 4.0 1.15 3.5 1.75 0.20 S S S S S All dimensions in mm S 0.59 S 8.0 Note: 2.0 0.70 User direction of unreeling Doc ID 023846 Rev 1 7/12 Recommendations on PCB assembly ESDALCL5-1BM2 4 Recommendations on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 20. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 21. Recommended stencil window position Package footprint Lead footprint on PCB Lead footprint on PCB Stencil window position 0.39 mm Stencil window position 0.45 mm 0.05 mm 8/12 Doc ID 023846 Rev 1 0.05 mm ESDALCL5-1BM2 4.2 4.3 4.4 Recommendations on PCB assembly Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Doc ID 023846 Rev 1 9/12 Recommendations on PCB assembly 4.5 ESDALCL5-1BM2 Reflow profile Figure 22. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 10/12 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 023846 Rev 1 ESDALCL5-1BM2 5 Ordering information Ordering information Table 4. Ordering information Order code Marking(1) Package Weight Base qty Delivery mode ESDALCL5-1BM2 S SOD882 0.92 mg 12,000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location 6 Revision history Table 5. Document revision history Date Revision 31-Oct-2012 1 Changes Initial release. Doc ID 023846 Rev 1 11/12 ESDALCL5-1BM2 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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