ESDAULC5-1BF4
Low clamping and ultra low capacitance single line bidirectional
ESD protection
Datasheet - production data
Applications
Where transient over voltage protection in ESD
sensitive equipment is required, such as:
• Smartphones, mobile phones and accessories
• Tablet, PC, netbooks and notebooks
• Portable multimedia devices and accessories
• Digital cameras and camcorders
• Communication and highly integrated systems
Description
0201 package
The ESDAULC5-1BF4 is a bidirectional single
line TVS diode designed to protect the data line or
other I/O ports against ESD transients.
Features
The device is ideal for applications where both
reduced line capacitance and board space saving
are required.
• Low clamping voltage
• Bidirectional device
• Dynamic resistance Rd = 0.3 Ω typ.
Figure 1. Functional diagram
• Low leakage current
• 0201 package size compatible
• Ultra small PCB area: 0.18 mm2
• ECOPACK®2 compliant component
Complies with the following standards
• IEC 61000-4-2 level 4:
– ±30 kV (air discharge)
– ±30 kV (contact discharge)
June 2014
This is information on a product in full production.
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Characteristics
1
ESDAULC5-1BF4
Characteristics
Table 1. Absolute maximum ratings
Symbol
Parameter
Value
Unit
30
30
kV
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air discharge
VPP (1)
Peak pulse voltage
PPP(1)
Peak pulse power (8/20 µs)
140
W
IPP(1)
Peak pulse current (8/20 µs)
10
A
Operating junction temperature range
-40 to 150
°C
Tstg
Storage temperature range
-65 to +150
°C
TL
Maximum lead temperature for soldering during 10 s
260
°C
Tj
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Figure 2. Electrical characteristics (definitions)
Symbol
VBR
VCL
IRM
VRM
IPP
Rd
aT
=
=
=
=
=
Parameter
Breakdown voltage
Clamping voltage
Leakage current @ VRM
Stand-off voltage
Peak pulse current
=
=
Dynamic resistance
Voltage temperature
C LINE =
VCL
VCL
Slope: 1/Rd
Line capacitance
IPP
Table 2. Electrical characteristics (values, Tamb = 25 °C)
Value
Symbol
Min.
IR = 1 mA
IRM
VRM = 3 V
VCL
8 kV contact discharge after 30 ns, IEC 61000-4-2
13.5
VLINE= 0 V, F = 1 MHz, VOSC = 30 mV
1.5
Dynamic resistance, pulse duration 100 ns, I/O to GND
0.3
Rd
2/12
Typ.
VBR
CLINE
Unit
Test conditions
5.8
DocID025890 Rev 1
Max.
8.5
V
70
nA
V
3
pF
Ω
ESDAULC5-1BF4
Characteristics
Figure 3. Leakage current versus junction
temperature (typical values)
1000
Figure 4. S21 attenuation measurement result
IR ( nA)
S21 (dB)
0.00
VR = VRM = 3 V
direct and reverse
-1.00
100
-2.00
10
-3.00
F(Hz)
Tj (°C)
1
25
50
75
100
125
150
Figure 5. Eye diagram HDMI 1.4 (1080p/60 Hz)
3.35 Gbps Thru PCB
Rise time:94.1 ps
Fall time: 94.1 ps
-4.00
100.0k
1.0M
S21
10.0M
100.0M
1.0G
Figure 6. Eye diagram HDMI 1.4 (1080p/60 Hz)
3.35 Gbps ESDAULC5-1BF4
250 mV/c
250 mV/c
49.8 ps/c
49.8 ps/c
Rise time: 131.7 ps
Fall time: 130.6 ps
Eye height: 804 mv
Eye width: 275.8 ps
Eye height: 745 mv
Eye width: 270.7 ps
Figure 7. Eye diagram display port
HBR 2.7 Gbps Thru PCB
Figure 8. Eye diagram display port
HBR 2.7 Gbps ESDAULC5-1BF4
250 mV/c
250 mV/c
61.7 ps/c
61.7 ps/c
Rise time: 94.6 ps
Fall time: 94.6 ps
Eye height: 923 mv
Eye width: 356.4 ps
Rise time: 131.6 ps
Fall time: 131.6 ps
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Eye height: 356.4 mv
Eye width: 294.7 ps
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Characteristics
ESDAULC5-1BF4
Figure 9. Eye diagram MHL 1.0
2.5 Gbps Thru PCB
Figure 10. Eye diagram MHL 1.0
2.5 Gbps ESDAULC5-1BF4
200 mV/c
200 mV/c
74.1 ps/c
74.1 ps/c
Rise time: 92.2 ps
Fall time: 90.6 ps
Rise time: 136.7 ps
Fall time: 133.4 ps
Eye height: 743 mv
Eye width: 430.1 ps
Figure 11. Eye diagram SD4.2,
3.12 Gbps Thru PCB
Figure 12. Eye diagram SD4.2,
3.12 Gbps ESDAULC5-1BF4
140 mV/c
140 mV/c
53.4 ps/c
Rise time: 98.5 ps
Fall time: 96.1 ps
53.4 ps/c
Rise time: 137.7 ps
Fall time: 138.8 ps
Eye height: 345 mv
Eye width: 299.5 ps
Figure 13. Eye diagram USB2.0,
480 Mbps Thru PCB
200 mV/c
347.2 ps/c
347.2 ps/c
4/12
Eye height: 718 mv
Eye width: 2042 ps
Eye height: 321 mv
Eye width: 294.7 ps
Figure 14. Eye diagram USB2.0,
480 Mbps ESDAULC5-1BF4
200 mV/c
Rise time: 532 ps
Fall time: 532 ps
Eye height: 729 mv
Eye width: 418.6 ps
Rise time: 556 ps
Fall time: 548 ps
DocID025890 Rev 1
Eye height: 716 mv
Eye width: 2048 ps
ESDAULC5-1BF4
Characteristics
Figure 15. ESD response to IEC 61000-4-2
(+8 kV contact discharge)
Figure 16. ESD response to IEC 61000-4-2
(-8 kV contact discharge)
20 V/div
20 V/div
1 106.8 V
1
2
3
4
22 11.3 V
VCL: Peak clamping voltage
VCL :clamping voltage at 30 ns
VCL :clamping voltage at 60 ns
VCL :clamping voltage at 100 ns
3 13.3 V
3 -10
4 -8 V
2
-12.4 V
1
2
3
4
4 7.5 V
VCL: Peak clamping voltage
VCL :clamping voltage at 30 ns
VCL :clamping voltage at 60 ns
VCL :clamping voltage at 100 ns
1 -113.1 V
20 ns/div
20 ns/div
Figure 17. TLP measurements
20
IPP (A)
18
Tj = 25 °C
16
14
12
10
8
6
4
2
0
VCL (V)
5
6
7
8
9
10
11
12
13
14
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Package information
2
ESDAULC5-1BF4
Package information
•
Epoxy meets UL94, V0
•
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 18. 0201 package dimension definitions
D
E
Top
A
Side
fD
D1
fE
E1
Bottom
b
Table 3. 0201 package dimension values
Dimensions
Ref.
Millimeters
Min.
Max.
Min.
Typ.
Max.
A
0.28
0.3
0.32
0.0110
0.0118
0.0126
b
0.125
0.14
0.155
0.0049
0.0055
0.0061
D
0.57
0.6
0.63
0.0224
0.0236
0.0248
D1
6/12
Typ.
Inches
0.35
0.0138
E
0.27
0.3
0.33
0.0106
0.0118
0.0130
E1
0.175
0.19
0.205
0.0069
0.0075
0.0081
fD
0.065
0.08
0.095
0.0026
0.0031
0.0037
fE
0.11
0.125
0.13
0.0043
0.0049
0.0051
DocID025890 Rev 1
ESDAULC5-1BF4
Package information
Figure 19. Footprint in mm (inches)
0.656
(0.0258)
0.243
(0.0096)
L
0.243
(0.0096)
Figure 20. Marking
Pin1
0.300
(0.0118)
Pin2
0.170
(0.0067)
The marking codes can be rotated by 90° or 180° to differentiate assembly location.In no
case should this product marking be used to orient the component for its placement on a
PCB. Only pin 1 mark is to be used for this purpose.
Figure 21. Tape and reel specification
Bar indicates Pin 1
Ø 1.5 ± 0.1
4.0 ± 0.1
1.75 ± 0.1
2.0 ± 0.05
3.5 ± 0.05
0.68 ± 0.03
0.22
8.0 + 0.03 - 0.01
Note:
5
0.36 ± 0.03
5
5
5
5
5
5
0.38 ± 0.03
2.0 ± 0.05
All dimensions in mm
User direction of unreeling
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Recommendation on PCB assembly
ESDAULC5-1BF4
3
Recommendation on PCB assembly
3.1
Stencil opening design
1.
General recommendations on stencil opening design
a)
Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 22. Stencil opening dimensions
L
T
b)
W
General design rule
Stencil thickness (T) = 75 ~ 125 µm
W
Aspect Ratio = ----- ≥ 1.5
T
L×W
Aspect Area = ---------------------------- ≥ 0.66
2T ( L + W )
2.
Recommended stencil window
a)
Stencil opening thickness: 80 µm
b)
Other dimensions: see Figure 23
Figure 23. Recommended stencil window position, stencil opening thickness: 80 µm
0.230
(0.0091)
0.643
(0.0253)
0.183
(0.0072)
0.285
(0.0112)
0.008
(0.0003)
0.300
(0.0118)
0.008
(0.0003)
0.656
(0.0258)
0.007
0.007
(0.00027) (0.00027)
0.170
(0.0067)
0.243
(0.0096)
mm
(inches)
Footprint
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Stencil window
ESDAULC5-1BF4
3.2
3.3
3.4
Recommendation on PCB assembly
Solder paste
1.
Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste recommended.
3.
Offers a high tack force to resist component displacement during PCB movement.
4.
Use solder paste with fine particles: Type 4 (powder particle size 20-48 µm per
IPC J STD-005).
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Standard tolerance of ± 0.05 mm is recommended.
4.
1.0 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
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Recommendation on PCB assembly
3.5
ESDAULC5-1BF4
Reflow profile
Figure 24. ST ECOPACK® recommended soldering reflow profile for PCB mounting
240-245 °C
Temperature (°C)
250
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
Note:
10/12
30
60
90
120
150
180
210
240
270
300
Minimize air convection currents in the reflow oven to avoid component movement.
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ESDAULC5-1BF4
4
Ordering information
Ordering information
Figure 25. Ordering information scheme
ESDA ULC
5 - 1 B F4
ESDA array
Ultra low capacitance
Breakdown voltage
5 = 5.8 V min
Number of lines
Directional
B = Bi-directional
Package
F4 = 0201
Table 4. Ordering information
Order code
Marking
ESDAULC5-1BF4
L
(1)
Package
Weight
Base qty
Delivery mode
0201
0.116 mg
15000
Tape and reel
1. The marking codes can be rotated by 90° or 180° to differentiate assembly location
5
Revision history
Table 5. Document revision history
Date
Revision
03-Jun-2014
1
Changes
First issue.
DocID025890 Rev 1
11/12
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ESDAULC5-1BF4
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