ESDAULC6-3BF2

ESDAULC6-3BP6 ESDAULC6-3BF2 ESD protection for high speed interface Main applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ ■ ■ ■ ■ Computers Printers Communication systems Cellular phones handsets and accessories Video equipment SOT-666 ESDAULC6-3BP6 Flip-Chip ESDAULC6-3BF2 Figure 1. Functional diagram A B GND Features ■ ■ ■ Ultra low capacitance 1.25 pF max. Bi-directional protection RoHS package I/O1 NC I/O2 1 2 3 6 5 4 GND NC I/O3 I/O1 1 I/O2 I/O3 2 Description The ESDAULC6-3Bxx is a monolithic application specific discrete device dedicated to ESD protection of high speed interfaces such as USB2.0. The device is ideal for applications where both reduced print circuit board space and power absorption capability are required. Top view ESDAULC6-3BP6 Bump side view ESDAULC6-3BF2 Figure 2. Pin configuration I/O1 I/O2 I/O3 Benefits ■ ■ ■ GND Ultra low capacitance bidirectional ESD protection Low PCB space consumption: 2.5 mm2 max footprint (1.7 mm2 for Flip-Chip) Enhanced ESD protection: – 15 kV contact discharge – 15 kV air discharge No insertion loss to 3.0 GHz Ultra low leakage current High reliability offered by monolithic integration Table 1. Order codes Marking 3 3B Part number ESDAULC6-3BP6 ESDAULC6-3BF2 Complies with the following standards: IEC 61000-4-2 level 4: 8 kV (contact discharge) 15 kV (air discharge) MIL STD 883G-Method 3015-7: class 3B HBM (Human Body Model) ■ ■ ■ July 2007 Rev 1 1/11 www.st.com 11 Characteristics ESDAULC6-3BP6, ESDAULC6-3BF2 1 Characteristics Table 2. Symbol VPP Tj Tstg TL Peak pulse voltage (1) Absolute maximum ratings Parameter IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge Value (min.) Unit 15 15 150 -55 to +150 260 kV °C °C °C Maximum operating junction temperature Storage temperature range Maximum lead temperature for soldering during 10 s at 5 mm for case 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Table 3. Symbol VRM VBR VCL IRM IPP αT C Rd Parameter VBR (1) Electrical characteristics (Tamb = 25° C) Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Capacitance Dynamic resistance Test condition IR = 1 mA VRM = 5 V Square pulse, IPP = 6 A, tp = 2.5 µs 1.4 1.2 VI/O = 0 V, F = 1 MHz, VOSC = 30 mV SOT-666 Flip-Chip SOT-666 Flip-Chip 1.0 1.25 0.75 0.9 1.25 1.5 pF VI/O = 1.65 V, VCC = 4.3 V, F = 1 MHz, VOSC = 400 mV 0.9 1.20 10 Min 6.0 Typ Max 9.2 0.5 Unit V µA Ω -4/°C I VCL VBR VRM IRM V VRM VBR VCL Slope: 1/Rd IPP IRM Rd αT Ci/o-i/o 1. Same value for I/O to I/O and I/O to GND 2/11 ESDAULC6-3BP6, ESDAULC6-3BF2 Characteristics Figure 3. Relative variation of peak pulse power versus initial junction temperature (SOT-666) Figure 4. Relative variation of peak pulse power versus initial junction temperature (Flip-Chip) PPP[Tj initial] / PPP[Tj initial=25°C) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 PPP [T j initial] / PPP [T j initial=25°C] Tj(°C) Tj(°C) 0 25 50 75 100 125 150 0.0 Figure 5. Peak pulse power versus exponential pulse duration (SOT-666) Tj initial=25°C Figure 6. Peak pulse power versus exponential pulse duration (Flip-Chip) Tj initial = 25 °C PPP(W) 1000 1000 PPP (W) 100 100 tp(µs) 10 1 10 100 tP(µs) 10 1 10 100 Figure 7. Clamping voltage versus peak pulse current (typical values) (SOT-666) Figure 8. Clamping voltage versus peak pulse current (typical values) (Flip-Chip) IPP(A) 10.0 8/20µs Tj initial=25°C 10.0 IPP(A) Square wave 2.5 µs Tj initial =25° C 1.0 1.0 VCL(V) VCL(V) 0.1 5 10 15 20 25 30 0.1 5 10 15 20 25 30 3/11 Characteristics ESDAULC6-3BP6, ESDAULC6-3BF2 Figure 9. Junction capacitance versus reverse voltage applied (typical values) (SOT-666) Figure 10. Junction capacitance versus reverse voltage applied (typical values) (Flip-Chip) C(pF) 2 F=1MHz VOSC=30mVRMS Tj=25°C C(pF) 1 F=1MHz VOSC=30mVRMS Tj=25°C 1 VLINE(V) 0 0 1 2 3 4 5 VLINE(V) 0 0 1 2 3 4 5 Figure 11. Relative variation of leakage current versus junction temperature (typical values) (SOT-666) IR[Tj] / IR[Tj=25°C] 100 VR=5V Figure 12. Relative variation of leakage current versus junction temperature (typical values) (Flip-Chip) IR [T j] / IR [Tj=25°C] 100 VR =5V 10 10 Tj(°C) 1 25 50 75 100 125 150 T j(°C) 1 25 50 75 100 125 Figure 13. Remaining voltage after ESDAULC6-3BP6 during ESD 15 kV positive surge (air discharge) (SOT-666) 10 V/div Figure 14. Remaining voltage after ESDAULC6-3BF2 during ESD 15 kV positive surge (air discharge) (Flip-Chip) 10 V/div 0.1 µs/div 0.1 µs/div 4/11 ESDAULC6-3BP6, ESDAULC6-3BF2 Characteristics Figure 15. Remaining voltage after ESDAULC6-3BP6 during ESD 15 kV negative surge (air discharge) (SOT-666) 10 V/div Figure 16. Remaining voltage after ESDAULC6-3BF2 during ESD 15 kV negative surge (air discharge) (Flip-Chip) 10 V/div 0.1 µs/div 0.1 µs/div Figure 17. S21 attenuation measurement Figure 18. S21 attenuation measurement results of each channel (SOT-666) results of channel 1 (Flip-Chip) 0.00 dB 0.00 dB - 5.00 - 5.00 - 10.00 - 10.00 - 15.00 - 15.00 F (Hz) - 20.00 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M Line 2 1.0G 3.0G - 20.00 1.0M 3.0M 10.0M F (Hz) 30.0M 100.0M 300.0M 1.0G 3.0G Line 1 Line 3 Line 1 Figure 19. Analog crosstalk measurements between channels (SOT-666) 0.00 Figure 20. Analog crosstalk measurements between channels (Flip-Chip) 0.00 dB dB - 20.00 - 20.00 - 40.00 - 40.00 - 60.00 - 60.00 - 80.00 - 80.00 - 100.00 - 100.00 - 120.00 F (Hz) 1.0M Xtalk 3.0M 1/2 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G - 120.00 F (Hz) 1.0M Xtalk 3.0M 1/2 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G - 140.00 - 140.00 5/11 Application examples ESDAULC6-3BP6, ESDAULC6-3BF2 2 Application examples Figure 21. USB2.0 (high speed) protection application schematic USB 2.0 CONNECTOR V BUS D+ DGND IC to Protect Figure 22. Audio jack protection application schematic Audio jack 100pF FM Tuner Figure 23. SIM card protection application schematic MEMORY CONNECTOR RST CLK DATA GND 330nH SIM CARD PROCESSOR 6/11 ESDAULC6-3BP6, ESDAULC6-3BF2 Ordering information scheme 3 Ordering information scheme ESDA ULC 6 - 3 B xx ESD Array Ultra low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 3 = 3 lines Type B = Bidirectional Packages F2 = Flip-Chip P6 = SOT-666 7/11 Package information ESDAULC6-3BP6, ESDAULC6-3BF2 4 Package information ● Epoxy meets UL 94, V0 SOT-666 dimensions Dimensions b1 L1 Table 4. Ref. Millimeters Min. Typ. Max. Min. Inches Typ. Max. 0.024 0.007 0.013 L3 b A A3 b D E1 0.45 0.08 0.17 0.19 1.50 1.50 1.10 0.50 0.19 0.10 0.10 0.27 0.60 0.018 0.18 0.003 0.34 0.007 b1 D 0.34 0.007 0.011 0.013 1.70 0.059 1.70 0.059 1.30 0.043 0.020 0.007 0.30 0.004 0.004 0.012 0.067 0.067 0.051 A E L2 E A3 E1 e L1 L2 e L3 Figure 24. SOT-666 footprint (dimensions in mm) 0.50 0.62 2.60 0.99 0.30 8/11 ESDAULC6-3BP6, ESDAULC6-3BF2 Figure 25. Flip-Chip dimensions 650 µm ± 65 500 µm ± 50 Package information 1.0 mm ± 50 µm 1.1 mm ± 50 µm 315 µm ± 50 Figure 26. Flip-Chip footprint Copper pad Diameter: 220 µm recommended Solder stencil opening: 330 µmrecommended 1.6 mm ± 50µm Figure 27. Flip-Chip marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) E Solder mask opening recommendation: 300 µmrecommended xxz y ww Figure 28. Flip-Chip tape and reel specifications Dot identifying Pin A1 location 4 +/- 0.1 Ø 1.5 +/- 0.1 1.75 +/- 0.1 3.5 +/- 0.1 0.71 +/- 0.05 All dimensions in mm In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 8 +/- 0.3 ST E ST E ST E xxz yww xxz yww User direction of unreeling xxz yww 4 +/- 0.1 9/11 Ordering information ESDAULC6-3BP6, ESDAULC6-3BF2 5 Ordering information Table 5. Ordering information Marking 3 3B Package SOT-666 Flip-Chip Weight 2.9 mg 2.22 mg Base qty 5000 5000 Delivery mode Tape and reel Tape and reel Part number ESDAULC6-3BP6 ESDAULC6-3BF2 6 Revision history Table 6. Datet 03-Jul-2007 Revision history Revision 1 Initial release Changes 10/11 ESDAULC6-3BP6, ESDAULC6-3BF2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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