ESDAVLC6-1BF4

ESDAVLC6-1BF4 Single-line low capacitance Transil™, transient surge voltage suppressor (TVS) Datasheet - production data Description The ESDAVLC6-1BF4 is a bidirectional single line TVS diode designed to protect the data lines or other I/O ports against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required. Figure 1. Functional diagram 0201 package Features • Bidirectional device • Multiple ESD strike sustainability • Very low capacitance: 7 pF max at 0 V • Low leakage current • Ultra small PCB area • RoHS compliant Complies with the following standards • IEC 61000-4-2: – ±15 kV (air discharge) – ±8 kV (contact discharge) Applications Where transient over voltage protection in ESD sensitive equipment is required, such as: • Portable multimedia devices and accessories • Notebooks • Digital camera and camcorders • Communication systems • Cellular phone handsets and accessories TM: Transil is a trademark of STMicroelectronics May 2015 This is information on a product in full production. DocID023119 Rev 2 1/9 www.st.com Characteristics 1 ESDAVLC6-1BF4 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol VPP (1) Parameter Value Unit ±15 kV IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge Peak pulse voltage Top Operating temperature range -30 to +85 °C IPP Peak pulse current (8/20 µs) 3 A Tstg Storage temperature range - 55 to +150 °C 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Electrical characteristics (definitions) I Symbol VBR VRM VCL IRM IPP = = = = = CLINE = Parameter Breakdown voltage Stand-off voltage Clamping voltage Leakage current @ VRM Peak pulse current Line capacitance VCL VBR VRM IRM Slope: 1/Rd V VRM VBR VCL IPP Table 2. Electrical characteristics (values, Tamb = 25 °C) Symbol VBR Breakdown voltage, IRM = 1 mA IRM Leakage current, VRM = 3 V per line Rd Dynamic resistance, pulse width 100 ns CLINE VCL 2/9 Test condition Line capacitance, F = 1 MHz, VOSC30 mV +8 kV contact discharge after 30 ns IEC 61000 4-2 DocID023119 Rev 2 Min. Typ. 6 Max. Unit 10 V 100 nA 1.7 4 Ω 7 35 pF V ESDAVLC6-1BF4 Characteristics Figure 3. ESD response to IEC 61000-4-2 (typical values, +8 kV contact discharge) Figure 4. ESD response to IEC 61000-4-2 (typical values, -8 kV contact discharge) 10 V/div 10 V/div 1 71 V 1 VPP: ESD peak voltage 2 VCL :clamping voltage @ 30 ns 3 VCL :clamping voltage @ 60 ns 4 VCL :clamping voltage @ 100 ns 2 41 V 4 -20 V 3 25 V 3 -24 V 4 20 V 1 VPP: ESD peak voltage 2 VCL :clamping voltage @ 30 ns 3 VCL :clamping voltage @ 60 ns 4 VCL :clamping voltage @ 100 ns 2 -40 V 20 ns/div 1 -72 V 20 ns/div Figure 5. Junction capacitance versus reverse Figure 6. Relative variation of peak pulse power applied voltage (typical values) versus initial junction temperature C (pF) 10 9 8 7 F=1 MHz Vosc =30mVRMS Tj=25 °C 100.0 DIRECT / REVERSE 80.0 PPP(W) 8/20µs Direct/Reverse 6 60.0 5 40.0 4 3 20.0 2 1 T j(°C) VR(V) 0.0 0 0 1 2 3 4 5 6 Figure 7. Peak pulse power versus exponential pulse duration 25 35 45 55 65 75 85 95 Figure 8. Leakage current versus junction temperature (typical values) PPP(W) IR (nA) 1000.0 100.00 Tj = 25 °C VR = VRM = 3 V Direct/Reverse Direct/Reverse 10.00 100.0 1.00 10.0 0.10 tP(µs) Tj (°C) 0.01 1.0 10 100 1000 25 DocID023119 Rev 2 35 45 55 65 75 85 3/9 9 Package information 2 ESDAVLC6-1BF4 Package information • Epoxy meets UL94, V0 • Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 2.1 0201 package information Figure 9. 0201 package outline D E Top A Side fD D1 fE E1 Bottom b Table 3. 0201 package mechanical data Dimensions Ref. Millimeters Min. Max. Min. Typ. Max. A 0.28 0.3 0.32 0.0110 0.0118 0.0126 b 0.125 0.14 0.155 0.0049 0.0055 0.0061 D 0.57 0.6 0.63 0.0224 0.0236 0.0248 D1 4/9 Typ. Inches 0.35 0.0138 E 0.27 0.3 0.33 0.0106 0.0118 0.0130 E1 0.175 0.19 0.205 0.0069 0.0075 0.0081 fD 0.11 0.125 0.14 0.0043 0.0049 0.0055 fE 0.04 0.055 0.07 0.0016 0.0022 0.0028 DocID023119 Rev 2 ESDAVLC6-1BF4 2.2 Package information Packing information Figure 10. Footprint in mm (inches) 0.243 (0.0096) 0.656 (0.0258) Figure 11. Marking 0.243 (0.0096) ID 0.300 (0.0118) 0.170 (0.0067) The marking codes can be rotated by 90° or 180° to differentiate assembly location.In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 12. Tape and reel outline 2.0 ± 0.05 Ø 1.5 ± 0.1 4.0 ± 0.1 3.5 ± 0.05 0.67 ± 0.03 0.22 5 0.36 ± 0.03 1.75 ± 0.1 Bar indicates Pin 1 8.0 + 0.03 - 0.01 Note: 5 5 5 5 5 5 0.38 ± 0.03 2.0 ± 0.05 All dimensions in mm User direction of unreeling DocID023119 Rev 2 5/9 9 Recommendation on PCB assembly ESDAVLC6-1BF4 3 Recommendation on PCB assembly 3.1 Stencil opening design 1. General recommendations on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 13. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Recommended stencil window a) Stencil opening thickness: 80 µm b) Other dimensions: see Figure 14 Figure 14. Recommended stencil window position, stencil opening thickness: 80 µm 0.230 (0.0091) 0.643 (0.0253) 0.183 (0.0072) 0.285 (0.0112) 0.008 (0.0003) 0.300 (0.0118) 0.008 (0.0003) 0.656 (0.0258) 0.007 0.007 (0.00027) (0.00027) 0.170 (0.0067) 0.243 (0.0096) mm (inches) Footprint 6/9 DocID023119 Rev 2 Stencil window ESDAVLC6-1BF4 3.2 3.3 3.4 3.5 Recommendation on PCB assembly Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: Type 4 (powder particle size 20-48 µm per IPC J STD-005). Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 1.0 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Reflow profile Figure 15. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. DocID023119 Rev 2 7/9 9 Ordering information 4 ESDAVLC6-1BF4 Ordering information Figure 16. Ordering information scheme ESDA VLC 6 - 1 B F4 ESDA protection device Very low capactitance Breakdown voltage 6=6V Number of lines Directional B = Bidirectional Package F4 = 0201 Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDAVLC6-1BF4 D(1) 0201 0.116 mg 15 000 Tape and reel 1. The marking codes can be rotated by 90° or 180° to differentiate assembly location 5 Revision history Table 5. Document revision history 8/9 Date Revision Changes 02-May-2012 1 First issue 20-May-2015 2 Updated package graphics and dimensions. Updated Table 2 and Figure 16. Removed internal restriction. DocID023119 Rev 2 ESDAVLC6-1BF4 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID023119 Rev 2 9/9 9