ESDAVLC8-1BT2Y

ESDAVLC8-1BT2Y Automotive single-line low capacitance Transil™, transient surge voltage suppressor (TVS) for ESD protection Datasheet − production data Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: • Automotive applications • Computers • Printers • Communication systems • Cellular phone handsets and accessories SOD882T ESDAVLC8-1BT2Y • Video equipment Description Features The ESDAVLC8-1BT2Y is a bidirectional singleline TVS diode designed to protect data lines or other I/O ports against ESD transients. • Single-line bidirectional protection • Breakdown voltage = 8.5 V min. This device is ideal for applications where both printed circuit board space and power absorption capability are required. • Very low capacitance = 4.5 pF at 0 V • Lead-free packages • ECOPACK®2 compliant component Figure 1. Functional diagram • AEC-Q101 qualified Benefits I/O1 • Very low capacitance for optimized data integrity • Very low reverse current < 50 nA • Low PCB space consumption: 0.6 mm2 I/O2 • High reliability offered by monolithic integration Complies with the following standards: • IEC 61000-4-2 (exceeds level 4) – 17 kV (air discharge) – 17 kV (contact discharge) • ISO10605: C = 330 pF, R = 330 Ω – 15 kV (air discharge) – 8 kV (contact discharge) • MIL STD 883G - Method 3015-7: class 3 – HBM (human body model) July 2014 This is information on a product in full production. TM: Transil is a trademark of STMicroelectronics DocID025558 Rev 2 1/13 www.st.com Characteristics 1 ESDAVLC8-1BT2Y Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value Unit 17 17 8 15 25 kV 30 W 1.3 A IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge ISO10605 contact discharge ISO10605 air discharge MIL STD 883G - Method 3015-7: class 3 VPP(1) Peak pulse voltage PPP(1) Peak pulse power dissipation (8/20 µs) Tj initial = Tamb IPP Peak pulse current (8/20 µs) TOP Operating junction temperature range - 50 to + 125 °C Tstg Storage temperature range - 65 to + 125 °C TL Maximum lead temperature for soldering during 10 s 260 °C 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Electrical characteristics (definitions) I Symbol VBR = VCL = IRM = VRM = IPP = IR = VTRIG = Cline = RD = Parameter Breakdown voltage Clamping voltage Leakage current @ VRM Stand-off voltage Peak pulse current Breakdown current Triggering voltage Input capacitance per line Dynamic resistance RD VCL VTrig VBR VRM V IRM IR I PP Table 2. Electrical characteristics (values, Tamb = 25 °C) Symbol VBR 2/13 Test condition Min. Typ. Max. From I/O 1 to I/O 2, IR = 1 mA 14.5 17 20 From I/O 2 to I/O 1, IR = 1 mA 8.5 11 14 IRM VRM = 3 V Cline F = 1 MHz, VR = 0 V V 4.5 DocID025558 Rev 2 Unit 50 nA 5.5 pF ESDAVLC8-1BT2Y Characteristics Figure 3. Peak pulse power versus initial junction temperature (maximum values) 50 PPP(W) Figure 4. Junction capacitance versus reverse voltage applied (typical values) 6,0 C(pF) F = 1 MHz VOSC= 30 mV Tj = 25 °C 5,0 40 8/20µs 4,0 30 3,0 20 2,0 10 0 1,0 Tj (°C) 25 0 50 75 100 150 125 VLINE (V) 0,0 0 1 2 3 Figure 5. Peak pulse power versus exponential Figure 6. Peak pulse power versus exponential pulse duration (maximum values) pulse duration (maximum values) 1000 PPP(W) 1000 PPP(W) T j initial = 25 °C T j initial = 25 °C 100 100 I/O 1 to I/O 2 10 10 1 tP (µs) 1 10 100 1000 Figure 7. Clamping voltage versus peak pulse current (maximum values) 10 I/O 2 to I/O 1 1 tP (µs) 1 10 100 Figure 8. Clamping voltage versus peak pulse current (maximum values) IPP (A) 10 IPP (A) 8/20 µs Tj initial = 25 °C 8/20 µs Tj initial = 25 °C I/O 2 to I/O 1 I/O 1 to I/O 2 1 1 VCL (V) VCL (V) 0,1 19 1000 20 21 22 23 24 0,1 13 14 15 16 17 18 19 20 21 22 23 24 DocID025558 Rev 2 3/13 13 Characteristics ESDAVLC8-1BT2Y Figure 9. Leakage current versus junction temperature (typical values) 100 Figure 10. Leakage current versus junction temperature (typical values) IR(nA) IR(nA) 100 VR =V RM = 3 V 10 VR =V RM = 3 V 10 I/O 1 to I/O 2 1 1 0,1 0,1 0,01 25 Tj (°C) 35 45 55 65 75 85 95 105 115 125 I/O 2 to I/O 1 Tj (°C) 0,01 25 Figure 11. S21 attenuation measurement result 0 dB -5 -10 -15 -20 -25 F (Hz) -30 100k 1M 10M 100M 1G 10 V/div 4/13 20 ns/div 55 65 75 85 95 105 115 125 IPP (A) I/O2 to I/O1 I/O1 to I/O2 VCL (V) 10 Figure 13. ESD response to ISO 10605 C = 150 pF, R = 330 Ω (+8 kV contact) 45 Figure 12. TLP measurements 26 24 22 20 18 16 14 12 10 8 6 4 2 0 , 35 15 20 25 30 35 40 Figure 14. ESD response to ISO 10605 C = 150 pF, R = 330 Ω (-8 kV contact) 10 V/div DocID025558 Rev 2 20 ns/div ESDAVLC8-1BT2Y Characteristics Figure 15. Response to ISO 7637-3 Pulse 3a (Us = -150 V) Figure 16. Response to ISO 7637-3 Pulse 3b (Us = +100 V) 10 V/div 5 V/div 50 ns/div 500 mA/div 50 ns/div 500 mA/div DocID025558 Rev 2 5/13 13 Package information 2 ESDAVLC8-1BT2Y Package information • Epoxy meets UL94, V0 • Lead-free packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 17. SOD882T dimension definitions L1 L2 b1 b2 PIN # 1 ID e A A1 E D 6/13 DocID025558 Rev 2 ESDAVLC8-1BT2Y Package information Table 3. SOD882T dimension values Dimensions Ref. Millimeters Min. Typ. Inches Max. Min. Typ. Max. A 0.30 0.40 0.012 0.016 A1 0.00 0.05 0.000 0.002 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 D 0.55 0.60 0.65 0.022 0.024 0.026 E 0.95 1.00 1.05 0.037 0.039 0.041 e 0.60 0.65 0.70 0.024 0.026 0.028 L1 0.20 0.25 0.30 0.008 0.010 0.012 L2 0.20 0.25 0.30 0.008 0.010 0.012 Figure 18. SOD882T footprint in mm (inches) 0.55 (0.022) Figure 19. SOD882T marking 0.55 (0.022) 0.50 (0.020) I/O 1 L I/O 2 0.40 (0.016) Note: Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. DocID025558 Rev 2 7/13 13 Package information ESDAVLC8-1BT2Y Figure 20. SOD882T tape and reel specifications Bar indicates Pin 1 2.0 1.50 4.0 3.5 1.15 8.0 1.75 0.20 2.0 0.70 User direction of unreeling DocID025558 Rev 2 X X X X 8/13 X All dimensions in mm X X 0.47 ESDAVLC8-1BT2Y Recommendation on PCB assembly 3 Recommendation on PCB assembly 3.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 21. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 22. Recommended stencil window position in mm (inches) 0.40 (0.016) 0.55 (0.022) 0.50 (0.020) 0.474 (0.019) 0.013 0.013 (0.00051) (0.00051) 2. 0.014 0.014 (0.00055) (0.00055) 0.522 (0.021) DocID025558 Rev 2 Lead footprint on PCB Stencil window opening 9/13 13 Recommendation on PCB assembly 3.2 3.3 3.4 10/13 ESDAVLC8-1BT2Y Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. DocID025558 Rev 2 ESDAVLC8-1BT2Y 3.5 Recommendation on PCB assembly Reflow profile Figure 23. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. DocID025558 Rev 2 11/13 13 Ordering information 4 ESDAVLC8-1BT2Y Ordering information Figure 24. Ordering information scheme ESDA VLC 8 - 1 B T2 Y ESD array Very low capacitance Breakdown voltage 8 = 8.5 Volts min Number of lines Directional B = Bidirectional Package T2 = Thin SOD882 Automotive Table 4. Ordering information Order code Marking(1) Package Weight Base qty Delivery mode ESDAVLC8-1BT2Y L SOD882T 0.81 mg 12000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location 5 Revision history Table 5. Document revision history 12/13 Date Revision Changes 09-Dec-2013 1 Initial release. 15-Jul-2014 2 Added Figure 13, Figure 14, Figure 15 and Figure 16. DocID025558 Rev 2 ESDAVLC8-1BT2Y IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID025558 Rev 2 13/13 13