ESDAXLC6-1BT2

ESDAXLC6-1BT2 Datasheet Single line ESD protection for high speed lines in 0402 Features • • • • • • Flow-through routing to keep signal integrity Ultra large bandwidth: 12 GHz Ultra low capacitance: 0.4 pF Extended operating junction temperature range: -55 °C to 150 °C RoHS compliant Complies with IEC 61000-4-2 - C = 150 pF, R = 330 Ω – ±16 kV (contact discharge) – ±30 kV (air discharge) Application The ESDAXLC6-1BT2 is a bidirectional single line TVS diode designed to protect the data line or other I/O ports against ESD transients such as: • Digital video interface • Ethernet • USB 2.0 and USB 3.0 • High speed communication buses • RF front-end Description Product status link ESDAXLC6-1BT2 The ESDAXLC6-1BT2 is an ESD device designed for high-speed lines protection. For automotive application, an AEC-Q101 qualified version is available see ESDAXLC6-1BT2Y. DS9261 - Rev 3 - May 2021 For further information contact your local STMicroelectronics sales office. www.st.com ESDAXLC6-1BT2 Characteristics 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value Unit Contact discharge 16 kV Air discharge 30 IEC 61000-4-2 (C = 150 pF, R = 330 Ω): VPP Peak pulse voltage PPP Peak pulse power dissipation (8/20 µs) 40 W IPP Peak Pulse current (8/20 µs) 1.3 A Tstg Storage temperature range -65 to +150 °C Tj Operating junction temperature range -55 to +150 °C TL Maximum lead temperature for soldering during 10 s 260 °C Figure 1. Electrical characteristics (definitions) Ipp Stand-off voltage Table 2. Electrical characteristics (values) (Tamb = 25° C) Symbol Min. Typ. Max. Unit 6 9 11 V nA VBR IR = 1 mA IR VR = 3 V 50 IPP = 1 A, 8/20 µs 17 VCL Rd CI/O-GND fC DS9261 - Rev 3 Test conditions IEC 61000-4-2 - C = 150 pF, R = 330 Ω +8 kV contact discharge, measured at 30 ns V 37 TLP, pulse duration 100 ns, 16 A 41 TLP, pulse duration 100 ns, 16 A 2 VI/O = 0 V, 200 MHz < f < 3 GHz, VOSC = 30 mV 0.4 S21 = -3 dB 12 Ω 0.5 pF GHz page 2/12 ESDAXLC6-1BT2 Characteristics (curves) 1.1 Characteristics (curves) Figure 2. Leakage current versus junction temperature Figure 3. Junction capacitance versus reverse applied voltage IR(nA) C(pF) 10 0.8 0.7 0.6 1 0.5 0.4 0.1 0.3 0.2 Tj(°C) 0.01 25 125 100 75 50 150 0.1 0 VR(V) 0 1 Figure 4. TLP 2 3 4 5 Figure 5. S21 attenuation I(A) 0 30 S 21 ( d B ) -1 20 -2 10 -3 0 -4 -10 -5 -20 -6 V(V) -30 -60 -40 -20 0 20 40 60 Figure 6. ESD response to IEC 61000-4-2 - C = 150 pF, R = 330 Ω (-8 kV contact discharge) DS9261 - Rev 3 F( H z) -7 100 M 300 M 1G 3G 10 G 30 G Figure 7. ESD response to IEC 61000-4-2 C = 150 pF, R = 330 Ω (+8 kV contact discharge) page 3/12 ESDAXLC6-1BT2 Characteristics (curves) Figure 8. H2 harmonic versus input power at 710 MHz Figure 9. H3 harmonic versus input power at 710 MHz Figure 10. H2 harmonic versus input power at 824 MHz Figure 11. H3 harmonic versus input power at 824 MHz Figure 12. H2 harmonic versus input power at 2400 MHz Figure 13. H3 harmonic versus input power at 2400 MHz DS9261 - Rev 3 page 4/12 ESDAXLC6-1BT2 Package information 2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 2.1 Package information Figure 14. Package outline A L1 b2 e D b1 E A1 L2 Table 3. Package mechanical data Dimensions Millimeters Ref. Min. DS9261 - Rev 3 Typ. Max. A 0.30 0.40 A1 0.00 0.05 L1 0.45 0.50 0.55 L2 0.45 0.50 0.55 D 0.95 1.00 1.05 E 0.55 0.60 0.65 e 0.60 0.65 0.70 b1 0.20 0.25 0.30 b2 0.20 0.25 0.30 page 5/12 ESDAXLC6-1BT2 Packing and marking information 2.2 Packing and marking information Figure 15. Marking layout Figure 16. Package orientation in reel X Pin1 Pin2 Taped according to EIA-481 Note: X: Refer to ordering information table for marking. Pocket dimensions are not on scale Pocket shape may vary depending on package On bidirectional devices, marking and logo may be not always in the same direction Figure 17. Tape leader and trailer dimensions End Carrier tape Top cover tape Figure 18. Tape and reel orientation Start 100 mm min 400 mm min 160 mm min Trailer Components Leader Figure 19. Reel dimensions (mm) Ø 180 max Figure 20. Inner box dimensions (mm) 30 14.4 2±0.5 Ø 13 205 Ø 60 Ø 20.2 min 205 DS9261 - Rev 3 page 6/12 ESDAXLC6-1BT2 Packing and marking information Figure 21. Tape outline Table 4. Tape and reel mechanical data Dimensions Millimeters Ref. DS9261 - Rev 3 Min. Typ. Max. D0 1.45 1.5 1.6 D1 0.35 F 3.45 3.5 3.55 K0 0.42 0.47 0.52 P0 3.9 4 4.1 P1 1.95 2 2.05 P2 1.95 2 2.05 W 7.9 8 8.3 page 7/12 ESDAXLC6-1BT2 Assembly recommendations 3 Assembly recommendations 3.1 Recommended footprint Figure 22. Recommended footprint in mm 0.4 0.55 0.5 0.55 1.5 Note: 3.2 Solder mask defined (SMD) recommended. Stencil opening design Stencil opening thickness: 75 μm / 3 mils Figure 23. Stencil opening recommendations 0.428 0.522 0.474 0.522 3.3 Solder paste 1. 2. 3. 4. DS9261 - Rev 3 Halide-free flux, qualification ROL0 according to ANSI/J-STD-004. “No clean” solder paste recommended. Tack force high enough to resist component displacement during PCB movement. Particles size 20-38 µm per IPCJ STD-005. page 8/12 ESDAXLC6-1BT2 Placement 3.4 Placement 1. 2. 3. 4. 3.5 PCB design preference 1. 2. 3.6 It is recommended to use leads recognition instead of package outline for accurate placement on footprint with adequate resolution tool. Tolerance of ±50 µm (25% offset allowed on the smallest dimension of the smallest pad) is recommended. 1.0 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. Any via around or inside the footprint area must be closed to avoid solderpaste migration in the via. Position and dimensions of the tracks should be well balanced. A symmetrical layout is recommended to prevent assembly troubles. Reflow profile Figure 24. ST ECOPACK recommended soldering reflow profile for PCB mounting 250 240-245 °C Temperature (°C) -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: DS9261 - Rev 3 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. O2 rate inside the oven must be below 500 ppm. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020. page 9/12 ESDAXLC6-1BT2 Ordering information 4 Ordering information Figure 25. Ordering information scheme ESDA XLC 6 - 1 B T2 ESD array Extra low capacitance Breakdown voltage 6 = 6 Volts min Number of lines Directional B = Bidirectional Package T2 = Thin SOD882 (0402) Table 5. Ordering information Order code Marking(1) Package Weight Base qty. Delivery mode ESDAXLC6-1BT2 T SOD882T (0402) 0.80 mg 12000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location DS9261 - Rev 3 page 10/12 ESDAXLC6-1BT2 Revision history Table 6. Document revision history DS9261 - Rev 3 Date Version Changes 04-Sep-2012 1 Initial release. 12-Aug-2013 2 Updated Figure 4, Figure 5, Figure 6, Figure 11 and Table 4. 10-May-2021 3 Updated SOD882T (0402) package information. Minor text changes. page 11/12 ESDAXLC6-1BT2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS9261 - Rev 3 page 12/12