ESDLIN03-1BWY
Automotive single-line Transil™,
transient voltage suppressor (TVS) for LIN bus
Datasheet - production data
Complies with the following standards
ISO 10605 - C = 150 pF, R = 330 Ω
– ±30 kV (air discharge)
– ±30 kV (contact discharge)
ISO 10605 - C = 330 pF, R = 330 Ω
– ±30 kV (air discharge)
– ±30 kV (contact discharge)
ISO 7637-3:
– Pulse 3a: Vs = -150 V
– Pulse 3b: Vs = +100 V
627/
Application
Figure 1. Functional schematic
LIN bus lines where electrostatic discharge and
other transients must be suppressed. This
product is compliant with most of automotive
interfaces.
Description
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The ESDLIN03-1BWY is a single-line Transil
specifically designed for the protection of the
automotive LIN bus lines against electrostatic
discharge (ESD) and transient voltages.
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Features
Single-line ESD and EOS protection
Stand-off voltage: 26.5 V
Bidirectional device
Max pulse power: 250 W (8/20 µs)
Low clamping factor VCL / VBR
Low leakage current
ECOPACK®2 compliant component
AEC-Q101 qualified
January 2016
This is information on a product in full production.
TM: Transil is a trademark of STMicroelectronics
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www.st.com
Characteristics
1
ESDLIN03-1BWY
Characteristics
Table 1. Absolute maximum ratings (Tamb = 25°C)
Symbol
VPP
Parameter
Electrostatic discharge
capability
ISO 10605 - C = 150 pF, R = 330 Ω :
Contact discharge
Air discharge
30
30
ISO 10605 - C = 330 pF, R = 330 Ω
Contact discharge
Air discharge
30
30
HBM MIL STD 883
30
PPP
Peak pulse power dissipation (8/20 µs)
IPP
Peak pulse current (8/20 µs)
Tj
Tstg
Value
Tj initial = Tamb
kV
250
W
3.7
A
Operating junction temperature range
-55 to +175
°C
Storage temperature range
-55 to +175
°C
Figure 2. Electrical characteristics (definitions)
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ESDLIN03-1BWY
Characteristics
Table 2. Electrical characteristics (values, Tamb = 25 °C)
Symbol
Test conditions
VRM
ESDLIN03-1BWY
VBR
IR = 1 mA
Min.
VRM = 5V
V
VRM = 24 V
1
nA
50
Tj = 125 °C
10
-39
ISO 7637-3 Pulse 3b (Us = +100 V)
39
IEC 61000-4-5 (8/20 µs), IPP = 1 A
37
IEC 61000-4-5 (8/20 µs), IPP = 3A
44
VR = 0 V DC, f = 1 MHz
T(1)
26.5
10
ISO 7637-3 Pulse 3a (Us = -150 V)
C
Unit
V
Tj = 25 °C
VRM = 5V
VCL
Max.
28.5
VRM = 24 V
IRM
Typ.
3
V
3.5
pF
9
10-4/°C
Voltage temperature coefficient
1. VBR at Tj = VBR at 25°C x (1 + αT x (Tj – 25))
Figure 3. Peak pulse current versus initial
junction temperature (maximum values)
Figure 4. Junction capacitance versus reverse
voltage applied
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Characteristics
ESDLIN03-1BWY
Figure 5. Peak pulse current versus clamping
voltage
Figure 6. Leakage current versus junction
temperature
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Figure 7. S21 attenuation measurement
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Figure 8. ESD response to ISO 10605 C = 150 pF, R = 330 Ω (+8 kV contact)
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Figure 9. ESD response to ISO 10605 C = 150 pF, R = 330 Ω (-8 kV contact)
Figure 10. Response to ISO 7637-3 Pulse 3a
(Us = -150 V)
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ESDLIN03-1BWY
Characteristics
Figure 11. Response to ISO 7637-3 Pulse 3b
(Us = +100 V)
Figure 12. TLP measurements
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Package information
2
ESDLIN03-1BWY
Package information
Epoxy meets UL94, V0
Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
2.1
SOT323-3L package information
Figure 13. SOT323-3L package outline
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ESDLIN03-1BWY
Package information
Table 3. SOT323-3L package mechanical data
Dimensions
Ref.
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.8
1.1
0.031
0.043
A1
0.0
0.1
0.0
0.004
b
0.25
0.4
0.01
0.016
c
0.1
0.26
0.004
0.01
D
1.8
2.0
2.2
0.071
0.079
0.086
E
1.15
1.25
1.35
0.045
0.049
0.053
e
0.65
0.026
H
1.8
2.1
2.4
0.071
0.083
0.094
L
0.1
0.2
0.3
0.004
0.008
0.012
ϴ
0
30°
0
30°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 14. SOT323-3L footprint dimensions in mm (inches)
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Package information
2.2
2.3
ESDLIN03-1BWY
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
Reflow profile
Figure 15. ST ECOPACK® recommended soldering reflow profile for PCB mounting
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Minimize air convection currents in the reflow oven to avoid component movement.
Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020.
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3
Ordering information
Ordering information
Figure 16. Ordering information scheme
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