ETC5054N/H

ETC5054 ETC5057 ® SERIAL INTERFACE CODEC/FILTER COMPLETE CODEC AND FILTERING SYSTEM (DEVICE) INCLUDING: – Transmit high-pass and low-pass filtering. – Receive low-pass filter with sin x/x correction. – Active RC noise filters – µ-law or A-law compatible COder and DECoder. – Internal precision voltage reference. – Serial I/O interface. – Internal auto-zero circuitry. A-LAW 16 PINS (ETC5057FN, 20 PINS) µ-LAW WITHOUT SIGNALING, 16 PINS (ETC5054FN, 20 PINS) MEETS OR EXCEEDS ALL D3/D4 AND CCITT SPECIFICATIONS ±5V OPERATION LOW OPERATING POWER - TYPICALLY 60 mW POWER-DOWN STANDBY MODE - TYPICALLY 3 mW AUTOMATIC POWER-DOWN TTL OR CMOS COMPATIBLE DIGITAL INTERFACES MAXIMIZES LINE INTERFACE CARD CIRCUIT DENSITY 0 to 70°C OPERATION ) s ( ct DIP16 (Plastic) ORDERING NUMBERS: ETC5057N ETC5054N c u d e t le o s b O - DESCRIPTION The ETC5057/ETC5054 family consists of A-law and µ–law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in the block diagram below, and a serial PCM interface. The devices are fabricated using doublepoly CMOS process. The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded A-law or µ–law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded A-law or µ–law code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz and is followed by a single-ended power amplifier capable of driving low impedance loads. The devices require 1.536 MHz, 1.544 ) s t( o r P SO16 (Wide) ORDERING NUMBERS: ETC5057D ETC5054D u d o r P e t e l o bs O March 2000 PLCC20 ORDERING NUMBERS: ETC5057FN ETC5054FN MHz, or 2.048 MHz transmit and receive master clocks, which may be asynchronous, transmit and receive bit clocks which may vary from 64 kHz to 2.048 MHz, and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats. 1/18 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. ETC5054 - ETC5057 PIN CONNECTIONS (Top view) DIP and SO PLCC BLOCK DIAGRAM c u d e t le ) s ( ct u d o r P e t e l o s b O 2/18 o s b O - o r P ) s t( ETC5054 - ETC5057 PIN DESCRIPTION Name Pin Type * N° N° DIP PLCC and SO (**) Function Description VBB S 1 1 Negative Power Supply GNDA VFRO GND O 2 3 2 3 VCC S 4 5 FSR I 5 6 Analog Ground Receive Filter Output Positive Power Supply Receive Frame Sync Pulse DR I 6 7 BCLKR/CLKSEL I 7 8 MCLKR/PDN I 8 9 Receive Data Input Shift-in Clock Receive Master Clock I 9 12 Transmit Master Clock BCLKX I 10 14 Shift-out Clock DX O 11 15 Transmit Data Output FSX I 12 16 TSX O 13 GSX r P e t e l o VFXI– VFXI+ s b O u d o Transmit Frame Sync Pulse 17 Transmit Time Slot 18 Gain Set Inverting Amplifier Input Non-inverting Amplifier Input O 14 I 15 19 I 16 20 All signals are referenced to this pin. Analog Output of the Receive Filter VCC = + 5 V ± 5 %. Enables BCLKR to shift PCM data into DR. FSR is an 8kHz pulse train. See figures 1, 2 and 3 for timing details. PCM data is shifted into DR following the FSR leading edge. Shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and receive directions (see table 1). This input has an internal pullup. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be but should be asynchronous with MCLKX, synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKR. c u d e t le ) s t( o r P o s b O - MCLKX ) s ( ct VBB = – 5 V ± 5 %. Shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX. The TRI-STATE PCM data output which is enabled by FSX. Enables BCLKX to shift out the PCM data on DX. FSX is an 8 kHz pulse train. See figures 1, 2 and 3 for timing details. Open drain output which pulses low during the encoder time slot. Recommended to be grounded if not used. Analog output of the transmit input amplifier. Used to set gain externally. Inverting Input of the Transmit Input Amplifier. Non-inverting Input of the Transmit Input Amplifier. (*) I: Input, O: Output, S: Power Supply (**) Pins 4,10,11 and 13 are not connected TRI-STATE® is a trademark of National Semiconductor Corp. 3/18 ETC5054 - ETC5057 FUNCTIONAL DESCRIPTION POWER-UP When power is first applied, power-on reset circuitry initializes the device and places it into the power-down mode. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLKR/PDN pin and FSX and/or FSR pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLKR/PDN pin high ; the alternative is to hold both FSX and FSR inputs continuously low. The device will power-down approximately 2 ms after the last FSX or FSR pulse. Power-up will occur on the first FSX or FSR pulse. The TRI-STATE PCM data output, DX, will remain in the high impedance state until the second FSX pulse. SYNCHRONOUS OPERATION For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLKX and the MCLKR/PDN pin can be used as a power-down control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In either case, MCLKX will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be applied to BCLKX and the BCLKR/CKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be selected as the bit clock for both the transmit and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLKR/CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX. Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the positive edge of BCLKX. After 8 bit clock periods, the ) s ( ct u d o r P e t e l o s b O Table 1: Selection of Master Clock Frequencies. BCLKR/CLKSEL Master Clock Frequency Selected ETC5057 ETC5054 Clocked 2.048 MHz 0 1.536 MHz or 1.544 MHz 1 (or open circuit) 2.048 MHz 4/18 1.536 MHz or 1.544 MHz 2.048 MHz 1.536 MHz or 1.544 MHz TRI-STATE DX output is returned to a high impedance state. With and FSR pulse, PCM data is latched via the DR input on the negative edge of BCLKX (or BCLKR if running). FSX and FSR must be synchronous with MCLKX/R. ASYNCHRONOUS OPERATION For asynchronous operation, separate transmit and receive clocks may be applied, MCLKX and MCLKR must be 2.048 MHz for the ETC5057, or 1.536 MHz, 1.544 MHz for the ETC5054, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronous with MCLKX, which is easily achieved by applying only static logic levels to the MCLKR/PDN pin. This will automatically connect MCLKX to all internal MCLKR functions (see pin description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FSX starts each encoding cycle and must be synchronous with MCLKX and BCLKX. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic levels shown in table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64 kHz to 2.048 MHz. c u d e t le ) s t( o r P SHORT FRAME SYNC OPERATION The device can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSX and FSR, must be one bit clock period long, with timing relationships specified in figure 2. With FSX high during a falling edge of BCLKX the next rising edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the DX output. With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. Both devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode. o s b O - LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods long, with timing relationships specified in figure 3. Based on the transmit frame sync, FSX, the device will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns (see fig. 1). The DX TRISTATE output buffer is enabled with the rising edge of FSX or the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKX rising ETC5054 - ETC5057 edges clock out the remaining seven bits. The DX output is disabled by the falling BCLKX edge following the eighth rising edge, or by FSX going low, which-ever comes later. A rising edge on the receive frame sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). Both devices may utilize the long frame sync pulse in synchronous or asynchronous mode. TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see figure 6. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unitygain filter consisting of RD active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to A-law (ETC5057) or µ– law (ETC5054) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2.5V peak (see table of transmission characteristics). The FSX frame sync pulse controls the sampling of the filter output, and then the successive-apABSOLUTE MAXIMUM RATINGS Symbol VCC VBB Parameter VCC to GNDA VIN, VOUT Toper Tstg VBB to GNDA Voltage at any Analog Input or Output Voltage at Any Digital Input or Output ) s ( ct proximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through DX at the next FSX pulse. The total encoding delay will be approximately 165 µs (due to the transmit filter) plus 125µs (due to encoding delay), which totals 290µs. Any offset vol-tage due to the filters or comparator is cancelled by sign bit integration. RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (ETC5057) or µ–law (ETC5054) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample and hold. The filter is then followed by a 2nd order RC active post-filter and power amplifier capable of driving a 600Ω load to a level of 7.2 dBm. The receive section is unity-gain. Upon the occurence of FSR, the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins, and 10µs later the decoder DAC output is updated. The total decoder delay is ∼ 10µs (decoder update) plus 110µs (filter delay) plus 62.5µs (1/2 frame), which gives approximately 180µs. A mute circuitry is a active during 10ms when power up. c u d e t le o s b O - o r P Value 7 Unit V –7 VCC + 0.3 to VBB – 0.3 VCC + 0.3 to GNDA – 0.3 V V V – 25 to + 125 – 65 to + 150 300 °C °C °C Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 seconds) u d o r P e t e l o ) s t( ELECTRICAL OPERATING CHARACTERISTICS VCC = 5.0 V ± 5 %, VBB = – 5.0 V ± 5%GNDA = 0 V, TA = 0 °C to 70 °C; Typical Characteristics Specified at VCC = 5.0 V, VBB = – 5.0 V, TA = 25 °C ; all signals are referenced to GNDA. s b O Symbol VIL VIH VOL VOH IIL IIH IOZ Parameter Input Low Voltage Input High Voltage Output Low Voltage IL = 3.2mA DX IL = 3.2mA, Open Drain TSX Output High Voltage IH = 3.2mA DX Input Low Current (GNDA ≤ VIN ≤ VIL, all digital inputs) Input High Current (VIH ≤ VIN ≤ VCC) except BCLKR/BCLKSEL Output Current in HIGH Impedance State (TRI-STATE) (GNDA ≤ VO ≤ VCC) DX Min. Typ. Max. 0.6 Unit V V 0.4 0.4 V V 2.4 –10 –10 10 10 V µA µA –10 10 µA 2.2 5/18 ETC5054 - ETC5057 ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices) Symbol Parameter Min. + - Typ. Max. Unit 200 nA IIXA Input Leakage Current (–2.5V ≤ V ≤ +2.5V) VFXI or VFXI – 200 RIXA Input Resistance (–2.5V ≤ V ≤ +2.5V) VFXI+ or VFXI- 10 ROXA Output Resistance (closed loop, unity gain) RLXA Load Resistance GSX CLXA Load Capacitance GSX VOXA Output Dynamic Range (RL ≥ 10KΩ) GSX AVXA Voltage Gain (VFXI+ to GSX) FUXA Unity Gain Bandwidth VOSXA Offset Voltage – 20 20 mV VCMXA Common-mode Voltage – 2.5 2.5 V MΩ 1 10 kΩ 50 ±2.8 V V/V 1 CMRRXA Common-mode Rejection Ratio 60 60 2 MHz ANALOG INTERFACE WITH RECEIVE FILTER (all devices) RORF Output Resistance RLRF Load Resistance (VF RO = ±2.5V) CLRF Load Capacitance VOSRO dB Output DC Offset Voltage s b O 6/18 ) s ( ct u d o r P e Power-down Current Power-down Current t e l o ICC1 IBB1 Active Current Active Current Min. o r P VFRO POWER DISSIPATION (all devices) Symbol ICC0 IBB0 e t le Parameter b O - so ) s t( dB c u d Parameter pF 5000 PSRRXA Power Supply Rejection Ratio Symbol Ω 3 Typ. Max. Unit 1 3 Ω Ω 600 500 pF 200 mV Typ. 0.5 0.05 Max. 1.5 0.3 Unit mA mA 6.0 6.0 9.0 9.0 mA mA – 200 Min. ETC5054 - ETC5057 TIMING SPECIFICATIONS Symbol Parameter Min. Typ. Max. 1.536 1.544 2.048 Unit 1/tPM Frequency of master clocks Depends on the device used and the BCLKR/CLKSEL Pin MCLKX and MCLKR tWMH Width of Master Clock High MCLKX and MCLKR 160 ns tWML Width of Master Clock Low MCLKX and MCLKR 160 ns tRM Rise Time of Master Clock MCLKX and MCLKR 50 ns tFM Fall Time of Master Clock MCLKX and MCLKR 50 ns tPB 15.725 ns Period of Bit Clock 485 tWBH Width of Bit Clock High (VIH = 2.2V) 160 tWBL Width of Bit Clock Low (VIL = 0.6V) 160 tRB Rise Time of Bit Clock (tPB = 488ns) tFB Fall Time of Bit Clock (tPB = 488ns) 488 MHz MHz MHz ns ns 50 ns 50 ns ) s t( tSBFM Set-up time from BCLKX high to MCLKX falling edge. (first bit clock after the leading edge of FSX) 100 tHBF Holding Time from Bit Clock Low to the Frame Sync (long frame only) 0 tSFB Set-up Time from Frame Sync to Bit Clock (long frame only) 80 tHBFI Hold Time from 3rd Period of Bit Clock Low to Frame Sync (long frame only) 100 tDZF Delay time to valid data from FSX or BCLKX, whichever comes later and delay time from FSX to data output disabled. (CL = 0pF to 150pF) 20 165 ns tDBD Delay time from BCLKX high to data valid. (load = 150pF plus 2 LSTTL loads) 0 180 ns tDZC Delay time from BCLKX low to data output disabled. 50 165 ns FSX or FSR tSDB Set-up time from DR valid to BCLKR/X low. Hold time from BCLKR/X low to DR invalid. tHOLD Holding Time from Bit Clock High to Frame Sync (short frame only) (s) e t le so ct du c u d o r P b O - tHBD ns ns ns ns 50 ns 50 ns 0 ns tSF Set-up Time from FSX/R to BCLKX/R Low (short frame sync pulse) - Note 1 80 ns tHF Hold Time from BCLKX/R Low to FSX/R Low (short frame sync pulse) - Note 1 100 ns tXDP Delay Time to TSXlow (load = 150pF plus 2 LSTTL loads) o r P e t e l o tWFL Minimum Width of the Frame Sync Pulse (low level) 64kbit/s operating mode) 140 160 ns ns s b O Note 1: For short frame sync timing FSX and FSR must go high while their respective bit clocks are high. Figure 1: 64kbits/s TIMING DIAGRAM (see next page for complete timing). FSx FSR 7/18 ETC5054 - ETC5057 Figure 2: Short Frame Sync Timing c u d e t le ) s ( ct u d o r P e t e l o s b O 8/18 o s b O - o r P ) s t( ETC5054 - ETC5057 Figure 3: Long Frame Sync Timing c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 9/18 ETC5054 - ETC5057 TRANSMISSION CHARACTERISTICS TA = 0 to 70°C, VCC = +5V ±5%, VBB = –5V ±5%, GNDA = 0V, f = 1.0KHz, VIN = 0dBm0 transmit input amplifier connected for unity-gain non-inverting (unless otherwise specified). AMPLITUDE RESPONSE Symbol tMAX GXA GXR GXAV GXRL GRA GRR Transmit Gain Variations with Level Sinusoidal Test Method Reference Level = – 10 dBm0 VFXI+ = – 40 dBm0 to + 3 dBm0 VFXI+ = – 50 dBm0 to – 40 dBm0 VFXI+ = – 55 dBm0 to – 50 dBm0 Receive Gain, Absolute (TA = 25°C, VCC = 5V, VBB = –5V) Input = Digital Code Sequence for 0dBm0 Signal at 1020Hz Receive Gain, Relative to GRA f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz Absolute Transmit Gain Variation with Temperature TA = 0 to +70°C Absolute Receive Gain Variation with Supply Voltage (VCC = 5 V ± 5 %, VBB = – 5 V ± 5 %) Receive Gain Variations with Level Sinusoidal Test Method; Reference input PCM code corresponds to an ideally encoded – 10 dBm0 signal PCM level = – 40 dBm0 to + 3 dBm0 PCM level = – 50 dBm0 to – 40 dBm0 PCM level = – 55 dBm0 to – 50 dBm0 (s) GRAT t c u od GRAV GRRL r P e t e l o s b O 10/18 Min. Receive Output Drive Level (RL = 600Ω) Typ. Unit Vrms 2.492 2.501 VPK VPK 0.15 dB – 40 – 30 – 26 – 0.2 – 0.1 0.15 0.05 0 – 14 – 32 dB 0.1 dB 0.05 dB – 0.2 – 0.4 – 1.2 0.2 0.4 1.2 dB dB dB – 0.15 0.15 dB – 0.35 – 0.35 – 0.7 0.20 0.05 0 – 14 dB dB dB dB – 0.1 0.1 dB – 0.05 0.05 dB – 0.2 – 0.4 – 1.2 0.2 0.4 1.2 dB dB dB – 2.5 2.5 V – 2.8 – 1.8 – 0.15 – 0.35 – 0.7 – 0.05 e t le c u d o r P – 0.1 o s b O - Max. 1.2276 – 0.15 Absolute Transmit Gain Variation with Temperature TA = 0 to +70°C Absolute Transmit Gain Variation with Supply Voltage (VCC = 5 V ± 5 %, VBB = – 5 V ± 5 %) GXAT VRO Parameter Absolute levels - nominal 0 dBm0 level is 4 dBm (600 Ω) 0 dBm0 Max Overload Level 3.14 dBm0 (A LAW) 3.17 dBm0 (U LAW) Transmit Gain, Absolute (TA = 25 °C, VCC = 5 V, VBB = – 5 V) Input at GSX = 0 dBm0 at 1020 Hz Transmit Gain, Relative to GXA f = 16 Hz f = 50 Hz f = 60 Hz f = 180 Hz f = 200 Hz f = 300 Hz - 3000 Hz f = 3300 Hz f = 3400 Hz f = 4000 Hz f = 4600 Hz and up, Measure Response from 0 Hz to 4000 Hz ) s t( ETC5054 - ETC5057 TRANSMISSION (continued) ENVELOPE DELAY DISTORTION WITH FREQUENCY Symbol Parameter Min. Typ. Max. Unit µs DXA Transmit Delay, Absolute (f = 1600Hz) 290 315 DXR Transmit Delay, Relative to DXA f = 500Hz - 600Hz f = 600Hz - 800Hz f = 800Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz 195 120 50 20 55 80 130 220 145 75 40 75 105 155 DRA Receive Delay, Absolute (f = 1600Hz) 180 200 DRR Receive Delay, Relative to DRA f = 500Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz – 25 – 20 70 100 145 90 125 175 – 40 – 30 Symbol NXP NRP NXC Parameter Transmit Noise, P Message Weighted (A LAW, VFXI + = 0 V) Receive Noise, P Message Weighted (A LAW, PCM code equals positive zero) Transmit Noise, C Message Weighted µ LAW (VFXI + = 0 V) o r P Min. e t le 1) o s b O - Receive Noise, C Message Weighted (µ LAW, PCM Code Equals Alternating Positive and Negative Zero) Noise, Single Frequency f = 0 kHz to 100 kHz, Loop around Measurement, VFXI + = 0 Vrms NRC NRS PPSRX NPSRX PPSRR (s) d o r P e t e l o NPSRR s b O t c u Positive Power Supply Rejection, Transmit (note 2) VCC = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz Negative Power Supply Rejection, Transmit (note 2) VBB = – 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz Positive Power Supply Rejection, Receive (PCM code equals positive zero, VCC = 5.0 VDC + 100mVrms) f = 0Hz to 4000Hz f = 4KHz to 25KHz f = 25KHz to 50KHz Negative Power Supply Rejection, Receive (PCM code equals positive zero, VBB = 5.0 VDC + 100mVrms) f = 0Hz to 4000Hz f = 4KHz to 25KHz f = 25KHz to 50KHz µs µs c u d NOISE µs ) s t( Typ. – 74 Max. – 69 Unit dBm0p – 82 12 – 79 15 dBm0p dBmC0 8 11 dBrnC0 – 53 dBm0 40 dBp 40 dBp 40 40 36 dBp dB dB 40 40 36 dBp dB dB 11/18 ETC5054 - ETC5057 TRANSMISSION CHARACTERISTICS (continued) NOISE (continued) Symbol Parameter Min. SOS Spurius out-of-band Signals at the Channel Output Loop around measurement, 0dBm0, 300Hz - 3400Hz input applied to DR, measure individual image signals at DX 4600Hz - 7600Hz 7600Hz - 8400Hz 8400Hz - 100,000Hz Typ. Max. Unit – 32 – 40 – 32 dB dB dB Max. Unit DISTORTION Symbol STDX or STDR Parameter Min. Typ. Signal to Total Distortion (sinusoidal test method) Transmit or Receive Half-channel Level = 3.0dBm0 Level = 0dBm0 to –30dBm0 Level = –40dBm0 33 36 29 30 14 15 XMT RCV XMT RCV Level = –55dBm0 SFDX Single Frequency Distortion, Transmit (TA = 25°C) SFDR Single Frequency Distortion, Receive (TA = 25°C) e t le IMD Intermodulation Distortion Loop Around Measurement, VFXI+ = –4dBm0 to –21dBm0, two Frequencies in the Range 300Hz - 3400Hz CROSSTALK ) s ( ct o s b O - Symbol CTX-R Parameter Transmit to Receive Crosstalk, 0 dBm0 Transmit Level f = 300Hz to 3400Hz, DR = Steady PCM Mode CTR-X Receive to Transmit Crosstalk, 0 dBm0 Receive Level f = 300Hz to 3400Hz, (note 2) o r P e c u d o r P Min. du ) s t( dBp –46 dB –46 dB –41 dB Typ. Max. Unit – 90 – 75 dB – 90 – 70 dB Notes: 1) Measured by extrapolation from distortion test results. 2) PPSRX, NPSRX, CTR-X is measured with a –50dBm0 activating signal applied at VFXI+. t e l o s b O ENCODING FORMAT AT DX OUTPUT µLaw A-Law (including even bit inversion) VIN (at GSX) = +Full-scale 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 VIN (at GSX) = 0V 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VIN (at GSX) = – Full-scale 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 12/18 ETC5054 - ETC5057 APPLICATION INFORMATION POWER SUPPLIES While the pins at the ETC505X family are well protected against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any-other connections are made. In applications where the printed circuit board may be plugged into a "hot" socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1µF supply decoupling capacitors should be connected from this common ground point to VCC and VBB as close to the device as possible. For best performance, the ground point of each CODEC/FILTER on a card should be connected to a common card ground in star formation, rather than via a ground bus. This common ground point should be decoupled to VCC and VBB with 10µF capacitors. Figure 4: T-PAD Attenuator R3 = Z1 . Z 2  N − 1  √   N  2 2     N2 − 1 R3 = Z1  2   N − 2NS + 1  RECEIVE GAIN ADJUSTMENT For applications where a ETC505X family CODEC/filter receive output must drive a 600Ω load, but a peak swing lower then ± 2.5V is required, the receive gain can be easily adjusted by inserting a matched T-pad or π –pad at the output. Table II lists the required resistor values for 600Ω terminations. As these are generally nonstandard values, the equations can be used to compute the attenuation of the closest pratical set of resistors. It may be necessary to use unequal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation. Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a good return loss. For example a 30dB return loss against 600Ω is obtained if the output impedance of the attenuator is in the range 282Ω to 319Ω (assuming a perfect transformer). c u d e t le ) s t( o r P Table 2 : Attenuator Tables For Z1 = Z2 = 300 Ω (all values in Ω).  N2 + 1   R1 = Z1  2 Z1 . Z2  −2 √ N − 1  N   Z1.Z2  2 R2 = 2 √  N − 1 Where: N = s b O ) s ( ct u d o r P e POWERIN  √  POWEROUT t e l o and: S =  N    2 N − 1 √Z1  Z2  Also : Z = √ ZSC . ZOC Where ZSC = impedance with short circuit termination and ZOC = impedance with open circuit termination. Figure 5: Π-PAD Attenuator o s b O dB R1 R2 R3 R4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 20 1.7 3.5 5.2 6.9 8.5 10.4 12.1 13.8 15.5 17.3 34.4 51.3 68 84 100 115 129 143 156 168 180 190 200 210 218 233 246 26k 13k 8.7k 6.5k 5.2k 4.4k 3.7k 3.3k 2.9k 2.6k 1.3k 850 650 494 402 380 284 244 211 184 161 142 125 110 98 77 61 3.5 6.9 10.4 13.8 17.3 21.3 24.2 27.7 31.1 34.6 70 107 144 183 224 269 317 370 427 490 550 635 720 816 924 1.17k 1.5k 52k 26k 17.4k 13k 10.5k 8.7k 7.5k 6.5k 5.8k 5.2k 2.6k 1.8k 1.3k 1.1k 900 785 698 630 527 535 500 473 450 430 413 386 366 13/18 ETC5054 - ETC5057 Figure 6: Typical Synchronous Application. c u d e t le ) s ( ct u d o r P e t e l o s b O 14/18 o s b O - o r P ) s t( ETC5054 - ETC5057 mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 10.1 10.5 0.398 0.413 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 K c u d e t le o s b O L ) s ( ct o r P e t e l o bs 16 du o r P SO16 Wide 0˚ (min.)8˚ (max.) B ) s t( h x 45 A e K A1 C H D 9 O E 1 8 15/18 ETC5054 - ETC5057 mm DIM. MIN. a1 0.51 B 0.77 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 Z u d o r P e 16/18 e t le 0.050 ) s ( ct t e l o c u d 0.130 1.27 s b O OUTLINE AND MECHANICAL DATA o s b O - o r P DIP16 ) s t( ETC5054 - ETC5057 mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 F 0.38 0.015 G 0.101 M 1.27 0.050 M1 1.14 0.045 e t le ) s ( ct M1 3 o r P e M1 5 t e l o bs du 2 1 20 o s b O 18 M F 17 e 16 7 15 8 O M 19 6 9 o r P PLCC20 B 4 c u d 0.004 ) s t( 10 11 A 12 E 14 13 d2 d1 PLCC20ME G (Seating Plane Coplanarity) D 17/18 ETC5054 - ETC5057 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. 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