EVAL-L9779WD-SPI

L9779WD-SPI Multifunction IC for engine management system Datasheet - production data  Protected low-side (high current) – OUT5, 6, 7  Protected low-side (low current) – OUT20  IGBT pre-drivers (IGN1 to 4) with parallel input  Parallel input IN1 to IN7 to drive OUT1 to OUT7  Configurable power stages CPS – Stepper motor driver/ high-side - low-side (OUTA to D) *$3*36 HiQUAD-64  Thermal warning and shutdown  Serial interface – SPI 16-bit frame – ISO9141 interface (K-Line) Features  5 V logic regulator  High speed CAN transceiver  3.3 V logic regulator  VDA 2.0 compliance with 3 level Watchdog  5 V tracking sensor supply  Package: HiQUAD-64  Smart reset function  Power latch with Secure Engine Off (SEO) functionality, to safely complete driver switch off procedure  Flying wheel interface function (VRS) with adaptive time and amplitude control  Protected low-side relay driver – OUT13 to 18, MRD  Protected low-side (injector drivers) – OUT1 to 4 Description The L9779WD-SPI is an integrated circuit designed for automotive environment and implemented in BCD6S technology. It is conceived to provide all basic functions for standard engine management control units. It is assembled in the HiQUAD-64 power package. Table 1. Device summary Order code Package Packing L9779WD-SPI HiQUAD-64 Tray L9779WD-SPI-TR HiQUAD-64 Tape and Reel May 2015 This is information on a product in full production. DocID027721 Rev 2 1/141 www.st.com Contents L9779WD-SPI Contents 1 Detailed features description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 5.1 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Latch-up test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.1 Low battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.2 Normal battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.3 High battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.4 Load dump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Ignition switch, main relay, battery pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 Power-up/down management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 6.2.1 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.2 Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Smart reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.1 6.4 Thermal shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.7 Main relay driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.8 6.7.1 Main relay driver functionality description . . . . . . . . . . . . . . . . . . . . . . . 44 6.7.2 MRD scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low-side switch function (LSa, LSb, LSd) . . . . . . . . . . . . . . . . . . . . . . . . 50 6.8.1 2/141 Smart reset circuit functionality description . . . . . . . . . . . . . . . . . . . . . . 29 LSa function OUT 1 to 5 (Injectors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DocID027721 Rev 2 L9779WD-SPI Contents 6.8.2 LSb function OUT6, 7 (O2 heater) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.8.3 LSc function OUT20 (low current drivers) . . . . . . . . . . . . . . . . . . . . . . . 55 6.8.4 LSd function OUT13 to 18 (relay drivers) . . . . . . . . . . . . . . . . . . . . . . . 57 6.9 LSa, LSb, LSc, LSd diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.10 Ignition pre-drivers (IGN1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.11 6.12 6.10.1 Ignition pre-drivers functionality description . . . . . . . . . . . . . . . . . . . . . . 65 6.10.2 Ignition pre-driver diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Configurable power stages (CPS) (OUTA to OUTD) . . . . . . . . . . . . . . . . 67 6.11.1 Configurable power stages functionality description . . . . . . . . . . . . . . . 67 6.11.2 Diagnosis of configurable power stages (CPS) . . . . . . . . . . . . . . . . . . . 71 6.11.3 Diagnosis of CPS [OUTA to OUTD] when configured as H-bridges . . . 71 6.11.4 Diagnosis of CPS OUTA, B, C, D when configured as single low side power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ISO serial line (K-LINE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.12.1 6.13 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.13.1 6.14 6.15 6.16 ISO serial line (K-LINE) functionality description . . . . . . . . . . . . . . . . . . 80 CAN transceiver functionality description . . . . . . . . . . . . . . . . . . . . . . . 83 Flying wheel interface function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.14.1 Flying wheel interface functionality description . . . . . . . . . . . . . . . . . . . 88 6.14.2 Auto-adaptive sensor filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.14.3 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.14.4 Diagnosis test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Monitoring module (watchdog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.15.1 WDA - Watchdog (algorithmic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.15.2 Monitoring module - WDA Functionality . . . . . . . . . . . . . . . . . . . . . . . . 99 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.16.1 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.16.2 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.16.3 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 CONFIG_REG1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 CONFIG_REG2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 CONFIG_REG3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 CONFIG_REG4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 CONFIG_REG5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 CONFIG_REG6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 CONFIG_REG7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 WD_ANSW/WDA RESP/CONFIG_REG8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 DocID027721 Rev 2 3/141 4 Contents L9779WD-SPI CONFIG_REG9/SPI RESPTIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 CONFIG_REG10 (CPS Configuration register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 IDENT_REG/DIA_REG[1:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 DIA_REG6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 DIA_REG7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DIA_REG8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 DIA_REG9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 DIA_REG10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 DIA_REG11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 DIA_REG12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 DIA_REG13/WDA_RESPTIME. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 DIA_REG14/REQULO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 DIA_REG15/REQUHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 DIAG_REG16/RST_AB1_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 CONTR_REG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 CONTR_REG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 CONTR_REG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 CONTR_REG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.1 8 4/141 HiQUAD-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DocID027721 Rev 2 L9779WD-SPI List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 KEY_ON pin electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 RST pin external components required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 RST pin electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Temperature information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Voltage regulators external components required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 VB Power supply electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Linear 5 V regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Linear 3.3 V regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5V tracking sensor supply electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Main relay driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LSa electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LSa diagnosis electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LSa diagnosis electrical characteristics (OUT 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LSb electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LSb diagnosis electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LSc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LSc diagnosis electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 LSd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LSd diagnosis electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Fault encoding condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Ignition pre-drivers electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Configuration of the stepper motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Half bridge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Half bridge 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Half bridge 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Half bridge 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Stepper configuration electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Electrical and diagnosis characteristics of OUTA, B, C, D when configured as single power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Electrical characteristics of OUTA, B, C, D when configured as single power stages connected in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CPS table single mode parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Three configurations of CONFIG_REG10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ISO serial line (K-LINE) functionality electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . 81 CAN transceiver electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 CAN transceiver timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Pick voltage detector precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Hysteresis threshold precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SPI command possible configuration of different option of VRS function. . . . . . . . . . . . . . 92 VRs typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Diagnosis test electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DocID027721 Rev 2 5/141 6 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. 6/141 L9779WD-SPI WDA_INT electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 State for = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Reset-behaviour of , AB1 and . . . . . . . . . . . . . . . . . . . . . . . . . 104 Expected responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Reset behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 CLOCK_UNLOCK_SW_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 START_REACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 HiQUAD-64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DocID027721 Rev 2 L9779WD-SPI List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Configuration supplied by VB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power-up/down management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Non-permanent supply power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Permanent supply power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-down sequence without power latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-down sequence without power latch mode and PSOFF = 1 . . . . . . . . . . . . . . . . . . 25 Power-down sequence with power latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power-down sequence with power latch mode and KEY_ON toggle . . . . . . . . . . . . . . . . . 27 KEY_ON voltage vs. status diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Smart reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 RST pin as a function of VDD5 (if CONFIG_REG6 bit3 = Low) . . . . . . . . . . . . . . . . . . . . . 32 Structure regulators diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Graphic representation of the calculation method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Circuit and PCB layout suggested . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VB overvoltage diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 VDD5 overvoltage diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VDD5 vs battery: ramp-up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 VDD5 vs battery (ramp-down diagram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Main relay driver controlled by L9779WD-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Scenario 1a: Standard on/off MRD driver with NO power latch mode bit PSOFF = 0 . . . . 45 Scenario 1b: Standard on/off MRD driver with NO power latch mode bit PSOFF = 1 . . . . 46 Scenario 2: Standard on/off MRD driver with power latch mode bit PSOFF = 0 . . . . . . . . 46 Scenario 3a: Deglitch concept on KEY_ON at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Scenario 3b: Deglitch concept on KEY_ON during ON phase . . . . . . . . . . . . . . . . . . . . . . 47 Scenario 4: Non standard on, KEY_ON removed before VB present . . . . . . . . . . . . . . . . 47 Scenario 5: MRD overcurrent without VB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Scenario 6: permanent MRD overcurrent with VBPOR restart . . . . . . . . . . . . . . . . . . . . . . 48 Scenario 7 (temporary MRD overcurrent with VB POR restart) . . . . . . . . . . . . . . . . . . . . . 48 Scenario 8 (temporary MRD overcurrent with VB µC commands restart) . . . . . . . . . . . . . 49 LSa function OUT 1 to 5 (Injectors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LSb function OUT6, 7 (O2 heater) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LSc function OUT20 (low current drivers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LSd function OUT13 to 18 (relay drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Behavior of OUT13, 14, 21, 25 with VB = VB_UV for a time shorter than Thold and with a valid ON condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Behavior of OUT13, 14, 21, 25 with VB = UB_UV for a time longer than Thold and with a valid ON condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Behavior of OUT13, 14, 21, 25 with VB that drops lower than POR threshold during cranking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LSx diagnosis circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Fault encoding condition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LSx ON/OFF slew rate control diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Ignition-pre drivers (IGN1 to 4) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Ignition-pre drivers (IGN1 to 4) diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Stepper motor operation diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DocID027721 Rev 2 7/141 8 List of figures Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. 8/141 L9779WD-SPI Stepper motor driver: H-bridge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Stepper motor driver: H-bridge2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Stepper motor driver “off” diagnosis time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Stepper motor driver diagnosis I-V relationship diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Open load detection during “on” phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Open load detection during “on” phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Short to GND detection during “on” phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ISO serial line (K-LINE) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ISO serial line switching waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ISO serial line: short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 CAN transceiver diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 CAN transceiver switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 CAN transceiver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Flying wheel interface circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Auto adaptative hysteresis diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 VRS interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Auto-adaptive time filter (rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Adaptive filter function when the SPI bit are 00 or 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Adaptive Filter Function when the SPI bit are 10 or 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Variable reluctance sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 VRs typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Hall effect sensor configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Hall effect sensor configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Diagnosis test diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 WDA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Monitoring cycle diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4-bit Markov chain diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Timing characteristics diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 HiQUAD-64 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 DocID027721 Rev 2 L9779WD-SPI 1 Detailed features description Detailed features description  Package –     5 V logic regulator – 5 V precision voltage regulator (± 2%) with external NMOS – Max current regulated: 400 mA – Charge pump capacitor at pin CP is used to drive the gate of the external NMOS transistor 3.3 V logic regulator – 3.3 V precision voltage regulator (± 2%) with over-current protection – Max current regulated: 100 mA 5 V tracking sensor supply – 2 x 5 V tracking sensor supply with protection and diagnosis on SPI – Short-circuit to Vbat/GND fully protected – Max current regulated: 2 x 100 mA Smart reset –     Main Reset monitoring VB_UV Logic voltage management and safety control Watch dog – Main reset management 5 V voltage monitoring safety output disable – SPI controllable query and answer watch dog compliant with VDA2.0 level 3 (enabled by default) Power latch –  HiQUAD-64 L9779WD-SPI is switched on by KEY_ON signal and switched off by logic OR of KEY_ON signal and SPI bit Secure engine off mode (default) switches off the drivers in the following order: – OUT1 through to OUT4 in 225 ms (typical) – OUT13 and OUT14 in 600 ms (typical) Flying wheel interface function (VRS) – The VRS is the interface between the microprocessor and the magnetic pick-up or variable reluctance sensor that collects the information coming from the flying wheel – Adaptive filtering on amplitude and timing adapts better the device response to VRS input switching Protected low-side driver – LSa (OUT1 to 5) 4 Ch. serial IN via SPI and parallel IN, Rdson = 0.72 Ohm @150 °C, Vcl = 58 V ±5, Imax = 2.2 A; 1 Ch. serial IN via SPI and parallel IN, Rdson = 0.72 Ohm @150°C, Vcl = 58 V ±5, Imax = 3 A; – LSb (OUT6, 7) 2 Ch. serial IN via SPI and parallel IN, Rdson = 0.47 Ohm @150°C, Vcl = 45 V ±5, Imax = 5 A DocID027721 Rev 2 9/141 140 Detailed features description L9779WD-SPI Full diagnosis on SPI (2 bit for each channel) and voltage slew rate control. When an over current fault occurs, the driver switches off with faster slew rate in order to reduce the power dissipation. – LSc (OUT20) 1 Ch serial IN via SPI, Imax = 50 mA  LSD (OUT13 to 18, MRD) 6 Ch. serial IN via SPI, Rdson = 1.5 Ohm @150 °C, Vcl = 48 V, Imax = 600 mA (2 of them with low battery voltage function); 1 main relay driver Rdson = 2.4 Ohm @150 °C, Vcl = 48 V, Imax = 600 mA With full diagnosis on SPI (2 bit for each channel) and voltage slew-rate control. When an over current fault occurs, the driver switches off with faster slew rate in order to reduce the power dissipation.  Ignition pre-drivers (IGN1 to 4) with parallel input – 4 x ignition pre-drivers with full diagnostic.  SPI  1 x Stepper motor driver designed for a double winding coil motor, used for engine idle speed control. The stepper driver is made by 4 independent half bridgeS each one with: – 1 high-side driver, Rdson =1.5 Ohm, Imax = 600 mA – 1 low-side driver, Rdson = 1.5 Ohm, Imax = 600mA The low-side drivers could be connected in parallel. Low-side and high-side drivers implement voltage SR control to minimize emission. Two high-side drivers have the low battery voltage function.  Thermal shutdown – 1 x Thermal shutdown (Tj > 175 °C = Tsd) if Tj > Tsd: VTRK1, 2 are turned off. – 1 x Thermal shutdown (Tj > 175 °C = Tsd) if Tj > Tsd: OUT1 to 10, OUT13 to 20, OUTA to D, IGN1 to 4 are turned off. – 1 x Thermal Shutdown (Tj > 175 °C = Tsd) if Tj > Tsd: V3V3 is turned off. – 1 x Thermal shutdown (Tj > 175 °C = Tsd) if Tj > Tsd: MRD is turned off (if battery present). There are 5 temperature sensors for OT2 (OUT1..10, OUT13…20, OUT21…28, IGN1…4 are turned off) in different Layout position, they are logically “AND” in case of thermal shutdown.  ISO9141 interface –  ISO9141 serial interface (K-Line) CAN transceiver The CAN bus transceiver allows the connection of the microcontroller, with CAN controller unit, to a high speed CAN bus with transmission rates up to 1Mbit/s for exchange of data with other ECUs. 10/141 DocID027721 Rev 2 L9779WD-SPI 2 Block diagram Block diagram Figure 1. Block diagram /63, 9% %DQGJDS 9UHJXODWRUOLQHDU 9EJ 9% 9 9 9LQWHUQDOVXSSO\ P$ 9'' 9EJ 9'' 9% 9''  .H\RQGHWHFWLRQDQG ILOWHULQJ .( 1k(1) 38 WDA WDA Interrupt Signal Output: open drain DGT input 7 VRSN Negative VRS input Analog Input 1.65 V Internal polarization 6 VRSP Positive VRS input Analog Input 1.65 V Internal polarization 8 OUT_VRS Digital VRS output DGT Output Open drain 44 CAN_TX Can transceiver input (from TX µP) DGT Input - 43 CAN_RX Can transceiver output (to RX µP) DGT Output - 42 CAN_H Bi-dir protected CAN_H wire Analog Input/Output - 41 CAN_L Bi-dir protected CAN_L wire Analog Input/Output - ISO9141 logical input DGT Input IPu =20 µA Bi-dir protected Kline wire Analog Input/Output Open drain ISO9141 logical output DGT Output Open drain VRS CAN ISO9141 47 K_TX 45 K_LINE 46 K_RX Low side drivers 60 OUT1 Output low-side 1 for R , L Load(Injector) Power output Open drain 61 OUT2 Output low-side 2 for R , L Load(Injector) Power output Open drain 25 OUT3 Output low-side 3 for R , L Load(Injector) Power output Open drain DocID027721 Rev 2 13/141 140 Pins description L9779WD-SPI Table 2. Pins description (continued) Pin# Name 28 OUT4 26 Function Type Polarization/note Output low-side 4 for R, L Load(Injector) Power output Open drain PGND3 Power GND PGND1 - 27 PGND4 Power GND PGND2 - 57 OUT5 Output low-side 5 for R , L Load(High current) Power output Open drain 56 OUT6 Outputlow-side 6 for R , L Load(Heater) Power output Open drain 29 OUT7 Output low-side 7 for R , L Load(Heater) Power output Open drain 30 OUT13 Output low-side 13 for Relay Power output Open drain 31 OUT14 Output low-side 14 for relay Power output Open drain 54 OUT15 output low-side 15 for relay Power output Open drain 24 OUT16 Output low-side 16 for relay Power output Open drain 32 OUT17 Output low-side 17 for relay Power output Open drain 55 OUT18 Output low-side 18 for relay Power output Open drain 58 PGND3 Power GND PGND3 - 59 PGND4 Power GND PGND4 - IGBT pre-driver 22 IGN1 Output ignition driver 1 Power output - 62 IGN2 Output ignition driver 2 Power output - 63 IGN3 Output ignition driver 3 Power output - 64 IGN4 Output ignition driver 4 Power output - Main relay driver Power output Open drain Output low-side 20 Power output Open drain Main relay driver 23 MRD Low current drivers (50 mA) 40 OUT20 Parallel input 39 IN1 Parallel input for OUT1 DGT Input - 48 IN2 Parallel input for OUT2 DGT Input - 37 IN3 Parallel input for OUT3 DGT Input - 36 IN4 Parallel input for OUT4 DGT Input - 35 IN5 Parallel input for OUT5 DGT Input - 34 IN6 Parallel input for OUT6 DGT Input - 14/141 DocID027721 Rev 2 L9779WD-SPI Pins description Table 2. Pins description (continued) Pin# Name 33 IN7 49 Function Type Polarization/note Parallel input for OUT7 DGT Input - PWM (IN8) PWM input for stepper motor driving DGT Input - 19 IGNI1 Parallel input for IGN1 DGT Input - 18 IGNI2 Parallel input for IGN2 DGT Input - 15 IGNI3 Parallel input for IGN3 DGT Input - 14 IGNI4 Parallel input for IGN4 DGT Input - SPI interface 51 SCK SPI clock input DGT Input - 53 CS SPI chip select DGT Input - 50 DIN SPI data input DGT Input - 52 DO SPI data output DGT Output - Stepper motor driver 13 OUTA Stepper Power output - 16 OUTB Stepper Power output - 17 OUTC Stepper Power output - 20 OUTD Stepper Power output - 21 GND Stepper GND GND - 1. External components required. Note: OUT11 and OUT12 are not valid. DocID027721 Rev 2 15/141 140 DocID027721 Rev 2 ' *1' & Q) *1' (B)B'*% (B)B'*% & Q) 9 9 *1' S) S) *1' . 5 . 287B956 95,1 - - 95,1 S) *1' &        73 95,1  73 95,1   S) 5 *1' .  & 5 .  73 73 &$1B7; &$1B5; .B5; .B7; &$1B/ &$1B+  73 5(6(7    5(6(7 -3 5(6(7 9'' 5     &/. &6 63,B'2 & Q) 5 . 7R  WKH X& )URP WKH X& 7R  WKH X& 7R  WKH X& )URP WKH X& *1' & & S) & .B/,1( )URP WKH X& )URP WKH X& 7R  WKH X& )URP WKH X& )URP WKH X& *1' 677+5$ '    -3 ,*1 9563 9561 287B956 &$1B/ &$1B+ &$1B7; &$1B5; .B5; .B/,1( .B7; &/. &6 '2 3:0 ',1 :'$ 567 975. 975. 9 .( 28 V), the charge pump will be switched off automatically no matter the cp_off bit status. Figure 19. VDD5 overvoltage diagram 6$$ 6TH?6$$?/6?HIGH 6TH?6$$?/6?LOW 4HE6$$?/6 FLAGISCLEARED AFTERU# READING 6$$?/6 )NTERNAL RESETFOR DRIVERS REGISTER $RIVERS /UTPUT T?6$$?/6 /. T?6$$?/6 /&& -2$ /54 /54 /. /. .OAUTOMATICSWITCH ON AFTER6$$OVERVOLTAGE U#SENDSCOMMAND 34!24ANDWRITES #/.42/,2%' /. 66 234 '!0'03 40/141 DocID027721 Rev 2 L9779WD-SPI Functional description Figure 20. VDD5 vs battery: ramp-up diagram 6B ;6=  6B .ORMAL"ATTERY   6DD    ;S= 2AMP UPTO.ORMAL"ATTERY '!0'03 Figure 21. VDD5 vs battery (ramp-down diagram) 6B ;6=  .ORMAL"ATTERY 6B   6DD    ,OW"ATTERYTO,OW4EMPERATURE#RANKING"ATTERY 2AMP $OWN ;S= '!0'03 DocID027721 Rev 2 41/141 140 Functional description L9779WD-SPI Table 15. Linear 3.3 V regulator electrical characteristics Pin V3V3 V3V3 Symbol Parameter Test condition Typ Max Unit V3V3 Output voltage 3.3 V IV3V3 = 5-100 mA VB = 6-18 V 3.23 3.3 3.36 V V3V3 Output voltage 3.3 V Square wave on V3V3, IV3V3= ±20 mA; f0 = 5 kHz; tr = tf = 0.5µs; within the output current range 3.2 3.3 3.36 V Srpower-up5 Output voltage slew rate at power-up IV3V3 = 12.5 mA Cout = 4.7 µF 4 12 20 V/ms IV3V3_MAX Output current limitation V3V3 = 3 V V3V3 VB = 6-18 V 200 - 500 mA Vline_3 Line regulation voltage IV3V3 = 5-100 mA 6V < VB < 18 V - - 25 mV Vload_3 Load regulation voltage IV3V3 = 5-100 mA 6V < VB < 18 V - - 25 mV V3V3Drift Total output 3V3 voltage drift Cout = 4.7 µF (parameter validated by reliability test) - - 100 mV SVRV3V3 Supply voltage 3.3 V rejection Cout = 4.7 µF; 4 Vpp, VB mean 9 V, f = 20 kHz 40 - - dB Vdrop_out - VDD5 = 3.3 V; IV3V3 =100 mA - - 200 mV Max overshoot at switch on - - - 3.45 V Max overshoot exiting from cranking*1 Not tested, it is guaranteed by design - - 3.45 V Tested by scan - - 1 ms V3V3_OS - Delay between VDD5> TD_Start_V3V VDD_UV_high and 3 V3V3 switch on 42/141 Min DocID027721 Rev 2 L9779WD-SPI Functional description Table 16. 5V tracking sensor supply electrical characteristics Pin Symbol Parameter Test condition Min Typ Max Unit VDD5 -20 - VDD5 +20 mV 160 - 400 mA Output voltage tracking error VB = 6-18 V 1 mA < IVTRK < 100 mA Output current limitation VTRK1,2 VTRK = -1V VLINE_trk Line regulation voltage VTRK VB = 6-18 V 1 mA < IVTRK < 100 mA Ctrk = 1 µF - - 20 mV Vload_ trk Load regulation voltage VTRK VB = 6-18 V 1 mA < IVTRK < 100 mA Ctrk = 1 µF - - 20 mV Isink_VTRK Short circuit reverse current Output shorted to Vbat +2 V - - 4 mA 101 - 5.3 - - V 40 - - dB VB = 4.8 V; IVTRK1,2 = 100 mA - - 3600 mΩ Cload  470 nF tested with 1 µF - - 5.5 V Cload < 470 nF tested with 100 nF - - 6 V 48 64 80 µs VTRK IVTRK_MAX VTRK_1 VTRK_2 ITH_UVTRK Over current threshold VTRK VB = 6-18 V VTH_OVTRK V threshold over voltage VTRK Ramp on tracking output Cout = 4.7 µF; VDD5 = 5 V 4 Vpp, VB mean 9 V, f = 20 kHz Supply voltage tracking SVR_VTRK rejection Rdson Vos Vov_filter - Over shoot during power up Overvoltage filter time Test by scan DocID027721 Rev 2 IVTRK_MAX mA 43/141 140 Functional description 6.7 L9779WD-SPI Main relay driver Figure 22. Main relay driver controlled by L9779WD-SPI 6BAT ,OAD RELAY 07,?%. +%9 6" $RIVER  PROTECTION -2$ '!0'03 6.7.1 Main relay driver functionality description Main relay driver MRD is controlled by L9779WD-SPI depending on the voltage levels at pins KEY_ON, VB and the power latch mode set by the µC as described in the previous sections. The output stage MRD for main-relay-control is realized with a low-side-switch with integrated clamping at VCL voltage realized with a zener diode. When VB is present (VB>VB_LV) the MRD driver is protected, in ON condition, against the over temperature fault. When the temperature is above junction the MRD is switched off. After HYSTERESIS the MRD returns to normal operation automatically. In case of MRD short to battery without VB present i.e. during start-up sequence, when the current exceeds the IOVC value, this pin will be switched off after a certain filter time TFILTEROVC; to turn on MRD again it is necessary a high to low transition on KEY_ON pin. Refer to scenario 5 (Figure 29). In case of MRD short to battery with VB present i.e. during normal mode, when the current exceeds the IOVC value, this pin will be switched off after a certain filter time TFILTEROVC; the uC can try to turn on the MRD using the command MRD_REACT until the VB voltage is above VB_UV. Below this threshold the MRD retries to switch on, then if the fault is still present the MRD switches off and to turn it on again it is necessary a high to low transition on KEY_ON pin. Refer to scenario 6-7-8 (Figure 30, 31 and 32). In every condition the bit MRD_OVC reports that the MRD is currently off due to a previous over current event. Diagnosis of MRD short to ground may be done as described in the power up/down management unit, switching off the MRD keeping alive all other regulators. 44/141 DocID027721 Rev 2 L9779WD-SPI Functional description Table 17. Main relay driver electrical characteristics Pin Symbol Min Typ Max Unit Iload = 0.4 A; Vbat = 0 & 13.5 V - - 2.4  Output leakage current Vpin = 13.5 V; Vbat = 0 & 13.5 V - - 10 µA Voltage S/R on/off R = 21 , C = 10 nF; Vbat = 0 & 13.5 V 1 - 10 V/µs Output clamping voltage Vbat = 0 & 13.5 V 42 - 55 V Imax Output current Design info - 0.6 A IOVC Over current threshold Vbat = 0 & 13.5 V 0.7 - 1.4 A Over current filtering time Test by SCAN 5.25 7 8.75 us VB threshold for MRD active Vbat = 0 & 13.5 V - - 4.15 V PWclampSP Clamp single pulse ATE test Iload = 0.5 A; single pulse - - 15 mJ PWclampRP Clamp repetitive pulses reliability test Iload = 0.25 A Freq =1 Hz; 1 Mpulse - - 4 mJ IOUTlk MRD VS/R Vcl TFILTEROVC VB_UV 6.7.2 Test condition Drain –source resistance RDS-on MRD Parameter MRD scenarios Figure 23. Scenario 1a: Standard on/off MRD driver with NO power latch mode bit PSOFF = 0 +%9?/. T+%9 T+%9  -2$ 6" 0/2( 6"6"?56?( 0/2 6$$ 234 T '!0'03 DocID027721 Rev 2 45/141 140 Functional description L9779WD-SPI Figure 24. Scenario 1b: Standard on/off MRD driver with NO power latch mode bit PSOFF = 1 +%9?/. T+%9 T+%9 -2$ 6"?56?, 6" 0/2( 6"6"?56?( 0/2 6$$?56?, 6$$ 234 T '!0'03 Figure 25. Scenario 2: Standard on/off MRD driver with power latch mode bit PSOFF = 0 T+%9 T+%9 3WITCHEDOFFBY U#BIT07,?%. -2$ 6" 0/2 6$$ 234 T '!0'03 Figure 26. Scenario 3a: Deglitch concept on KEY_ON at start-up +%9?/. T+%9 -2$ 6" 0/2 T 6$$ '!0'03 46/141 DocID027721 Rev 2 L9779WD-SPI Functional description Figure 27. Scenario 3b: Deglitch concept on KEY_ON during ON phase +%9?/. T+%9 T+%9 -2$ 6" 0/2 6$$ T '!0'03 Figure 28. Scenario 4: Non standard on, KEY_ON removed before VB present +%9?/. T+%9 T+%9 -2$ 6" 0/2 6$$ T '!0'03 Figure 29. Scenario 5: MRD overcurrent without VB +%9?/. T+%9 4&),4%26# T+%9 -2$ 4HISSIGNALKEEPS THE-2$OFFUNTIL +%9?/.LOW )NTERNAL /VER#URR?-2$ LATCH 3HORTTO6"ON -2$ &!5,4 02%3%.4 6" 0/2 6$$ T '!0'03 DocID027721 Rev 2 47/141 140 Functional description L9779WD-SPI Figure 30. Scenario 6: permanent MRD overcurrent with VBPOR restart +%9?/. T+%9 .ORESETFOR-2$?/6# AFTERREADING -2$ T+%9 )NTERNAL /VER#URR?-2$ LATCH 4&,)4%26# -2$?/6# &!5,4 02%3%.4 3HORTTO6"ON -2$ 6" 0/2 6$$ T '!0'03 Figure 31. Scenario 7 (temporary MRD overcurrent with VB POR restart) +%9?/. T+%9 -2$ 4&),4%26# -2$?/6# 3HORTTO6"ON -2$ &!5,4 02%3%.4 6" 0/2 6$$ T '!0'03 48/141 DocID027721 Rev 2 L9779WD-SPI Functional description Figure 32. Scenario 8 (temporary MRD overcurrent with VB µC commands restart) —#READSTHE -2$?/6#FLAG +%9?/. —#SWITCHONTHE -2$BY -2$?2%!#4BIT T+%9 -2$ T+%9 -2$?/6# 3HORTTO6"ON -2$ &!5,4 02%3%.4 6" 0/2 6$$ T '!0'03 DocID027721 Rev 2 49/141 140 Functional description L9779WD-SPI 6.8 Low-side switch function (LSa, LSb, LSd) 6.8.1 LSa function OUT 1 to 5 (Injectors) Figure 33. LSa function OUT 1 to 5 (Injectors) 6BAT 30)?$IAG?REG 0ROTECTION $IAGNOSIS 2ESET? , 30)?#MD?,3A ,OAD ).* /UT?,3A $RIVER /%INT ).TO *$3*36 LSa functionality description LSa are 5 protected low-side drivers with diagnosis and over current protection circuit. They are driven by logical-AND of SPI control bit and dedicated parallel input IN1...IN5. The maximum current for OUT1 to 4 is 2.2 A while for OUT5 is 3 A. When Reset_L9779 signal or OUT_DIS bit is asserted OUT_LSa is switched off. When an over current fault occurs, the driver switches off with faster slew rate in order to reduce the power dissipation. The turn on/off time is fixed and the slew-rate is controlled. Max Cload = 20 nF. Table 18. LSa electrical characteristics Pin Symbol Min Typ Max Unit Drain source resistance Iload = 1.25 A - - 0.72  IOUTlk Output leakage current Vpin = 13.5 V - - 10 µA Voltage S/R on/off Load: 8 , 10 nF From 80% to 30% of VOUT 2 - 6 V/µs FAST VR/S off when an OVC fault happens Load: 8 , 10 nF From 80% to 30% of VOUT 5 - 20 V/µs TTurn-on_ LSa Turn-on delay time From command to 80% VOUT, Load: 8 , 10 nF - - 6 µs TTurn-off_ LSa Turn-off delay time From command to 30% VOUT, Load: 8 , 10 nF - - 6 µs Output clamping voltage Iload = 1.25 A 53 58 63 V - - 25 mJ VS/R GateKill Vcl PWclampSP 50/141 Test condition RDS-on LSa VS/R OUT 1 to 5 Parameter Clamp single pulse ATE test Iload = 1.25 A single pulse DocID027721 Rev 2 L9779WD-SPI Functional description Table 18. LSa electrical characteristics (continued) Pin Symbol PWclampRP OUT 1 to 4 Reverse voltage PWclampSP OUT5 PWclampRP Parameter Test condition Min Typ Max Tc ≤ 30°C; I_OUT_n < 1.8 A 13 Mio cycles - - 7.5 Tc ≤ 65°C; I_OUT_n < 1.4 A 130 Mio cycles - - 4 Tc ≤ 80°C; I_OUT_n < 1.4 A 214 Mio cycles - - 4 Clamp repetitive pulses Tc ≤ 100°C; I_OUT_n < 1.4 A Freq = 50 Hz (to be verified) 175 Mio cycle - - 4 Tc ≤ 115°C; I_OUT_n < 1.4 A 45 Mio cycle - - 4 Tc ≤ 130°C; I_out_n < 1.0 A 65 Mio cycle - - 3 Tc ≤ 145°C; I_out_n < 1.0 A 6 Mio cycle - - 3 -0.5 - -1.2 Iload = 1.25 A single pulse - - 25 Tc < 30°C; I_OUT5 < 0.7 A 21 Mio cycles - - 17 Tc < 65°C; I_OUT5 < 0.7 A 70 Mio cycles - - 14 Tc < 80°C; I_OUT5 < 0.7 A 115.5 Mio cycles - - 14 Tc < 90°C; I_OUT5 < 0.7 A 63 Mio cycles - - 14 Tc < 100°C; I_OUT5 < 0.7 A 31.5 Mio cycles - - 14 Tc < 105°C; I_OUT5 < 0.7 A 10.5 Mio cycles - - 14 Tc < 110°C; I_OUT5 < 0.7 A 7 Mio cycles - - 14 Tc < 115°C; I_OUT5 < 0.7 A 5.95 Mio cycles - - 14 Tc < 120°C; I_OUT5 < 0.7 A 5.25 Mio cycles - - 12 Tc < 125°C; I_OUT5 < 0.7 A 4.9 Mio cycles - - 12 Tc < 130°C; I_OUT5 < 0.7 A 4.55 Mio cycles - - 12 Body diode reverse current voltage drop (valid for OUT5 I = -2.2 A also) Clamp single pulse Clamp repetitive pulses Freq = 30 Hz DocID027721 Rev 2 Unit mJ V mJ 51/141 140 Functional description L9779WD-SPI Table 18. LSa electrical characteristics (continued) Pin OUT5 Symbol PWclampRP Parameter Clamp repetitive pulses Freq = 30 Hz Test condition Min Typ Max Tc < 135°C; I_OUT5 < 0.7 A 4.55 Mio cycles - - 12 Tc < 140°C; I_OUT5 < 0.7 A 3.5 Mio cycles - - 12 Tc < 145°C; I_OUT5 < 0.7 A 3.5 Mio cycles - - 12 Unit mJ Table 19. LSa diagnosis electrical characteristics Pin Symbol Ropen load Min resistor value open Not tested load detection Min Typ Max Unit 500 - - k Output current Not tested - 2.2 - A IOVC Over current threshold - 3 - 6 A Over current filtering time Tested by scan 2 3 4 µs Filtering open load and Tested by scan short to gnd diag. off 35 50 65 µs Td_mask Diagnosis Mask time after switch-off Tested by scan 300 - 500 µs VHVT Open load threshold voltage - VOutopen +120mV - 3 V Open load output voltage Open load condition 2.3 - 2.7 V VLVT Output short-circuit to GND voltage range threshold - 1.9 - VOutopen -200mV V IOUT_PD Output diagnostic pull down current Off state Vpin = 5 V 50 - 110 µA IOUT_PU Output diagnostic pull up current Off state Vpin = 1.5 V 110 160 210 µA Open load threshold current - 30 - 90 µA TFILTERdiaggoff VOutopen OUT 1 to 5 Test condition Imax TFILTEROVC OUT 1 to 5 Parameter Itopen For OUT 5 only the following parameters are different respect to OUT1 to 4. Table 20. LSa diagnosis electrical characteristics (OUT 5) Pin OUT 5 52/141 Symbol Parameter Test condition Imax Output current Not tested IOVC Over current threshold - DocID027721 Rev 2 Min Typ Max Unit - 3 - A 3.7 - 6.9 A L9779WD-SPI 6.8.2 Functional description LSb function OUT6, 7 (O2 heater) Figure 34. LSb function OUT6, 7 (O2 heater) 6BAT 30)?$IAG?REG  0ROTECTION $IAGNOSIS ,OAD 2ESET?, 30)?#MD?,3B %.?,OW2ES /UT?,3B $RIVER ). *$3*36 LSb functionality description LSb are 2 protected low-side drivers with diagnosis and over current protection circuit. They are driven by logical-AND of SPI control bit and dedicated parallel input IN6, IN7. The turn on/off time is fixed and the slew-rate is controlled. When an over current fault occurs, the driver switches off with faster slew rate in order to reduce the power dissipation. The turn on/off time is fixed and the slew-rate is controlled. Max Cload = 20 nF. Table 21. LSb electrical characteristics Pin Symbol Parameter Test condition T = -40°C, Iload = 3 A RDS-on LSb Drain source resistance T = 25°C, Iload = 3 A T = 130°C, Iload = 3 A OUT 6, 7 IOUTlk Output leakage current - VS/R Voltage S/R on/off R = 4.5 , C = 10 nF From 80% to 30% of VOUT VS/R GateKill FAST VR/S off when an Load: 8 , 10 nF OVC fault happens From 80% to 30% of VOUT Min Typ Max Unit 0.05 - 0.16  0.13 - 0.23  0.21 - 0.47  - - 10 µA 0.5 - 2.5 V/µs 5 - 20 V/µs TTurn-on_ LSb Turn-on delay time From command to 80% VOUT Load: 4.5 , 10 nF - - 7.5 µs TTurn-off_ LSb Turn-off delay time From command to 20% VOUT Load: 4.5 , 10 nF - - 7.5 µs 41 45 49 V - - 25 mJ Vcl PWclampSP Output clamping voltage Iload = 1.5 A Clamp single pulse ATE Iload = 1.5 A; single pulse test DocID027721 Rev 2 53/141 140 Functional description L9779WD-SPI Table 21. LSb electrical characteristics (continued) Pin Symbol Parameter Clamp repetitive pulses Freq = 5 Hz Reliability Test PWclampRP OUT 6, 7 Reverse voltage Body diode reverse current voltage drop Test condition Min Typ Max Tc < 30 °C; I_OUT_n < 1.8 A 13 Mio cycles - - 7.5 Tc < 65°C; I_OUT_n < 1.4 A 130 Mio cycles - - 4 Tc < 80°C; I_OUT_n < 1.4 A 214 Mio cycles - - 4 Tc < 100°C; I_OUT_n < 1.4 A 175 Mio cycle - - 4 Tc < 115°C; I_OUT_n < 1.4 A 45 Mio cycle - - 4 Tc < 130°C; I_OUT_n < 1.0 A 65 Mio cycle - - 3 Tc IOVC for t > TFILTEROVC the driver is switched off and the fault is set, latched and reset every Read Diag operation. When the fault occurs the driver is switched off with a controlled slew-rate. The driver switches on AGAIN in the following conditions: – If command goes LOW and then HIGH again – If command remains active the driver is switched automatically on at every Read Diag operation. Short to GND: Not available. Open Load: Not available. Channel “off” Short to Vb: Not available. Short to GND & open load: In open load condition an internal circuit drives the OUTx voltage to VOUTOPEN with a maximum pull-up/down current of IOUT_PU and IOUT_PD. Diagnosis is done comparing driver output voltage with internal voltage thresholds VHVT and VLVT: if the voltage is below VLVT a short to GND is detected, if the voltage is above VLVT and below VHVT an open load is detected and if the voltage is above VHVT no fault is present. Diagnosis status is masked for Td_mask time after the off event occurs to allow the output voltage to reach the proper value. Short to GND and open load are filtered with TFILTERdiagoff time. Diag status is latched and reset at every Read Diag operation. 62/141 DocID027721 Rev 2 L9779WD-SPI Functional description For LSc(OUT20) the IOUT_PD/IOUT_PU can be switched off by OFF_LCDR bit and therefore the Open Load and Short To GND detections are not available. Figure 40. LSx diagnosis circuit 6BAT ,OAD 6DD )/54?05 &ILTER $IAGNOSIS  PROTECTION /UT?,3X )/54?0$ &ILTER 2 ESET?, $RIVER 30)?# MD?,3X %.? ,OW2 ES  /%?INT *$3*36 Table 27. Fault encoding condition Bit n+1 Bit n Description 1 1 Power stage OK no Fail 0 1 Open Load OL 1 0 Short circuit to VB/over current SGB 0 0 Short circuit to GND SCG Figure 41. Fault encoding condition diagram 6?/54X LOW SIDE .ORMAL .ORMAL FUNCTION 6 6(64MIN 6/54/0%. MAX 6/54/0%. 6/54/0%.MIN /PEN ,OAD /PEN,OAD 6,64MAX 6 3HORT TO 3HORTTO '.$ '!0'03 DocID027721 Rev 2 63/141 140 Functional description L9779WD-SPI Figure 42. LSx ON/OFF slew rate control diagram 4ON ;6=; 6= 4OFF ,OW3IDE6OUT 32ON 32OFF 6OUT,OW3IDE ,OGICCONTROLL ,OGICCONTROLL ;MS= ;!=; 6= )GATE )ON )SRON 6GATE 6GATE ;MS= )SROFF )GATE )OFF '!0'03 6.10 Ignition pre-drivers (IGN1 to 4) Figure 43. Ignition-pre drivers (IGN1 to 4) circuit 6" 6$$ )'.X )'.)X ,/')# /6%2 4%-0 $%4%#4)/. /0%.,/!$ #,+ $/ $) #3 30) &),4%2 3(/244/6" 3(/244/'.$ $%4%#4)/. *$3*36 64/141 DocID027721 Rev 2 L9779WD-SPI 6.10.1 Functional description Ignition pre-drivers functionality description The 4 ignition pre-drivers are push-pull output with diagnosis and over current protection circuit. They can drive IGBT Darlington transistors. The load is switched on with a current and switched off with I_LS_cont current. They are driven by logical-AND of SPI control bit and dedicated parallel input IGN1...IGN4. When Reset_L9779 signal or OUT_DIS bit is asserted, output IGNx becomes high impedance. By SPI command it is possible to have the low-side stage always off, in this case there is an external pull down resistor that discharges The IGNx output in Off phase. This Bit is present in CONFIG_REG2 bit0 and its name is LS_IGN_OFF. Table 28. Ignition pre-drivers electrical characteristics Pin Symbol VDD5 Parameter Test condition Min Typ Max Unit 5.1 V Supply voltage range Info only 4.9 - Output voltage high level I_cont = 15 mA 4.35 - Leakage current - -10 - 10 µA I_lim High-side current limitation - 19 - 33 mA I_LS_cont LS path continuous current capability Add also the RDSON Test - - 30 mA - 3 - 14  Vign Ileak_out I_LS_RD LS RDSON S on V IOVC High side over current detection - 7 - 14 mA VLVT Output short-circuit to Gnd threshold voltage - 1.6 1.8 2 V - VDD5 +0.1V - VDD5 +2V - 100 - 850 µA - - 10 µs 50 - 100 µs IGN1 to 4 Vign_scb SCB detection voltage Iol OL detection current - Tdon Output on delay time CIgn = 10 nF OVC/Open load diagnosis filter time, Test by scan - Output on rise time CIgn = 10 nF - - 10 µs Output off delay time CIgn = 10 nF - - 10 µs Output off fall time CIgn = 10 nF - - 10 µs Rload Resistive load For info only 1 - 10 kΩ Cout Output capacitance loads For info only 4 - 15 nF Tign_filt Tr Tdoff Tf DocID027721 Rev 2 65/141 140 Functional description L9779WD-SPI Figure 44. Ignition-pre drivers (IGN1 to 4) diagram 6ALID30)DATAF RAME TIME TR TDON TDOFF TF 6) '.X 6) '. 6) '. TIME 6) '. 6.10.2 '!0'03 Ignition pre-driver diagnosis Each channel locally detects and writes its own fault or no-fault condition (codified on 2 bit according to Table 27: Fault encoding condition). The detected faults are:  IGNx short circuit to battery (SCB)  IGNx open load (OL)  IGNx short to GND (SCG) Short to GND This diagnosis is made in two different ways based on the status of IGN_DIA_SGEN. If IGN_DIA_SGEN = 1 When the IGNx is on, if for a time longer than Tign_filt, the current is bigger than IOVC, the short to GND fault is detected and the IGNx output becomes high impedance, the fault is latched and is reset at every Read Diag operation. If IGN_DIA_SGEN = 0 When the IGNx is on, if for a time longer than Tign_filt, the voltage of IGNx is lower than VLVT, the short to GND fault is detected and the IGNx output becomes high impedance, the fault is latched and is reset every Read Diag operation. The high impedance is removed and IGNx is driven by the command: – after a Read Diag operation – if command is switched OFF and ON again. Open load When IGNx is on, if for a time longer than Tign_filt, the current is below Iol the open-load fault is detected, latched and it is reset at every Read Diag operation. IGNx remains always driven. 66/141 DocID027721 Rev 2 L9779WD-SPI Functional description Short circuit to battery When the load is on, if the voltage of IGNx is bigger than the Vign_scb threshold for a time longer than Tign_filt the SCB fault is detected and the output IGNx becomes high impedance. When the load is off, if the voltage of IGNx is bigger than the Vign_scb threshold for a time longer than Tign_filt the SCB fault is detected and the output IGNx becomes high impedance. The SCB fault has a higher priority with respect to the OL fault. According to the IGN_DIA_MODE bit, two behaviours are possible: 1. Latch mode The fault is latched and is reset at every Read Diag operation. The high impedance is removed and IGNx is driven by the command: 2. – after a Read Diag operation – if the command is switched OFF and ON again. No latch mode The fault is not latched and if the voltage of IGNx is lower than the Vign_scb threshold for a time longer than Tign_filt the fault state disappears and the high impedance is removed. 6.11 Configurable power stages (CPS) (OUTA to OUTD) 6.11.1 Configurable power stages functionality description L9779WD-SPI half bridges with 1 low side N-channel power stage and 1 high side Pchannel power stages [OUTA to OUTD] that can be arranged as follows using the CPS_CONF bit (default H-bridge):  The low side of each half can be connected in parallel to obtain a low side driver with lower Rdson resistance. For three reasons outputs are switched in parallel: a) to increase current capability (please see electrical characteristic) b) to reduce power dissipation (please see electrical characteristic) c) to increase clamp energy capability (please see electrical characteristic) The max. clamping energy is probably less than the sum of the corresponding max. clamping energies. Parallel connection of Low-side power stages is possible as the control bit to turn-on and off the power stages is allocated in the same register. Unlike the H-bridge configuration, no coherency check is done. When configured for stepper motor driving the motor movement is controlled through bit EN, DIR and PWM input SPI bit (see Table 29). In single power stage configuration HS and LS power stages (OUT21...OUT28) can be used as single power stages, and any of them can be connected in parallel to each other (same type). DocID027721 Rev 2 67/141 140 Functional description L9779WD-SPI Stepper is controlled by the logic AND between PWM input pin and PWM SPI bit. Thus to control it by PWM input, SPI PWM bit must be set first, and to do it by SPI PWM bit, PWM input pin must be set first. If the bit EN=1, the writing of bit PWM from 0 to 1 leads to the next step of the turn on sequence. The writing of bit PWM to 0 left unchanged the MOS of the bridge that is ON. The step is done only if the PWM bit goes from 0 to 1. The order of the turn-on sequence is defined by the bit DIR. Table 29. Configuration of the stepper motor PWM EN DIR H-bridge 1 Power on H-bridge 2 Power on X 0 X None None 1 1 1 OUTA_HS, OUTB_LS OUTD_HS, OUTC_LS 1 1 1 OUTA_HS, OUTB_LS OUTC_HS, OUTD_LS 1 1 1 OUTB_HS, OUTA_LS OUTC_HS, OUTD_LS 1 1 1 OUTB_HS, OUTA_LS OUTD_HS, OUTC_LS 1 1 0 OUTA_HS, OUTB_LS OUTD_HS, OUTC_LS 1 1 0 OUTB_HS, OUTA_LS OUTD_HS, OUTC_LS 1 1 0 OUTB_HS, OUTA_LS OUTC_HS, OUTD_LS 1 1 0 OUTA_HS, OUTB_LS OUTC_HS, OUTD_LS The initial stepper position, after power-on, is the one with OUTA_HS, OUTB_LS ON in Hbridge1 and with OUTD_HS, OUTC_LS ON in Hbridge2. If configured as H-bridges the internal logic prohibits that the low-side and the high-side switch of the same half-bridge will be switched on simultaneously. In the below diagram the stepper motor operation is available. 68/141 DocID027721 Rev 2 L9779WD-SPI Functional description Figure 45. Stepper motor operation diagram 7RITING$)2BIT 7RITING$)2BIT 7RITING%.BIT 7RITING%.BIT 7RITING07-BITFROMTO 7RITING07-BITFROMTO 4SETTLE /54/. /54! /54/. /54/. /54" /54/. /54/. /54# /54/. /54/. /54$ /54/. *$3*36 The writing of DIR bit and PWM bit cannot be done in the same time, at least two consecutive SPI frames are necessary.(if done the stepper will move one step in the old direction). The writing of EN bit and PWM bit cannot be done in the same time, at least two consecutive SPI frames are necessary. (If done it is supposed that only the EN bit has been received). Table 30. Half bridge 1 H-bridge1 OUTA Comment Nominal current Ron max Switch off current (min.) Clamping (typ.) High-side P-Ch 0.6 A 1.7  1A N/A Low-side N-Ch 0.6 A 1.5  1A 45 V DocID027721 Rev 2 69/141 140 Functional description L9779WD-SPI Table 31. Half bridge 2 H-bridge2 OUTB Comment Nominal current Ron max Switch off current (min.) Clamping (typ.) High-side P-Ch 0.6 A 1.7  1A N/A Low-side N-Ch 0.6 A 1.5  1A 45 V Table 32. Half bridge 3 H-bridge3 OUTC Comment Nominal current Ron max Switch off current (min.) Clamping (typ.) High-side P-Ch 0.6 A 1.7  1A N/A Low-side N-Ch 0.6 A 1.5  1A 45 V Table 33. Half bridge 4 H-bridge4 OUTD Comment Nominal current Ron max Switch off current (min.) Clamping (typ.) High-side P-Ch 0.6 A 1.7  1A N/A Low-side N-Ch 0.6 A 1.5  1A 45 V Figure 46. Stepper motor driver: H-bridge1 6"!4 #-$?/54 #-$?/54 /54" /54! #-$?/54 #-$?/54 '.$ *$3*36 Figure 47. Stepper motor driver: H-bridge2 6"!4 #-$?/54 #-$?/54 /54# /54$ #-$?/54 #-$?/54 '.$ *$3*36 70/141 DocID027721 Rev 2 L9779WD-SPI 6.11.2 Functional description Diagnosis of configurable power stages (CPS) All CPS have fault diagnostic functions:  Short-circuit to battery voltage: (SCB) can be detected if switches are turned on  Short-circuit to ground: (SCG) can be detected if switches are turned off  Open load: (OL) can be detected if switches are turned off  Over temperature: (OT) will be detected with the general thermal warning(OT2) Diagnosis is different for configuration as full-bridges or as single power stages. The faults are coded in different way and are stored in diagnostic registers. In each configuration the registers can be read via SPI. With the beginning of each read cycle the registers are cleared automatically. In each configuration there is one central diagnostic bit F2 for fault occurrence at any output. 6.11.3 Diagnosis of CPS [OUTA to OUTD] when configured as H-bridges Stepper motor driver OFF diagnosis (output in high impedance state). In OFF condition Short to GND/Short to VB or Open Load condition is continuously detected through a deglitch filter Tdgc_off, after Tmask_step masking time to filter ON/ OFF transition. To avoid false diagnostic due to motor residual movement, the off command (EN bit=0) must be sent Tsettle time after the last valid on command PWM bit written to 1 (one couple of HS and LS switched on). A fault longer than deglitch time is latched. Off state diagnostic fault can be overwritten by on state fault. Off state fault does not prevent the stepper from switching on. The latched fault is cleared by reading the diagnosis data registers via SPI - and so resetting the diagnosis registers. An Off state due to a wrong command sent by SPI interface does not activate the Off diagnosis. Stepper motor driver ON diagnosis (Output driven by SPI CONTR_REG bit) In ON condition when over current fault is detected and validated after digital filtering time Tdgc_ON, the bridge is turned OFF and the fault is latched. The bridge is turned ON again by SPI command. The latched fault is cleared by reading the diagnosis data registers via SPI and so resetting the diagnosis registers. Over current fault has higher priority over OFF condition faults. Each Bridge has dedicated fault diagnosis register H1_DIAG, H2_DIAG. In ON condition if the current in the load current is lower than I_OPEN_LOAD for a time longer than Tdgc_ol_on, an Open load condition is detected It could be necessary two steps of the stepper motor operation to detect the real kind of fault, in this case as first diagnosis the fault is "Fault detection running" and with the next PWM command it is possible to understand if the fault is an OPEN LOAD or an OVERCURRENT/SHORT to GND. DocID027721 Rev 2 71/141 140 Functional description L9779WD-SPI The Faults "DETECTION_RUNNING" & " OPEN LOAD" are latched during the during rise & fall edge of low-side driver command, if the fault disappeared during these phases the fault condition is no latched: – The FAULT DETECTION RUNNING is no latched, the fault comes back to 0 if the current becomes higher than open load threshold, before the switch off of low-side driver. – The FAULT OPEN LAOD is no latched, the fault comes back to 0 if the current becomes higher than open load threshold, before the switch off of low-side driver. A diagnostic read will clear the “fault detection running” flag. Anyway the diagnostic will restart. Figure 48. Stepper motor driver “off” diagnosis time diagram /54!/54# 6" 6" (64( 6/54./2,64( TIME 4MASKSTEP /54"/54$ 6" 6/54./2- ,64( ,64( TIME /. /&& /0%.,/!$ !FTERFILTERTIME4DGC?OFF 72/141 DocID027721 Rev 2 3(/244/6" !FTERFILTERTIME 3(/244/'.$ !FTERFILTERTIME *$3*36 L9779WD-SPI Functional description Figure 49. Stepper motor driver diagnosis I-V relationship diagram ,'66B287BRQ 287$287& —$ 9% +97+ —$ —$ 9'' 287$287& ,'66B287BRQ 287%287' —$ —$ 9% /97+ —$ 287%287' 67* 1250$/ 67% *$3*36 Note: this wave shows the I/V relationship of pin current and pin voltage when OUTA(OUTC) short to OUTB(OUTD) and force the pin voltage from 0 V to VB in typical condition. For example, when pin voltage of OUTA = OUTB = 1.5 V, the pull up/down current is about -50 µA for OUTA and about 14 µA for OUTB. When pin voltage of OUTA = OUTB = 5 V, the pull up/down current is about 40 µA for OUTA and about 220 µA for OUTB. DocID027721 Rev 2 73/141 140 Functional description L9779WD-SPI Figure 50. Open load detection during “on” phase /54!" /54#$ )?,/!$ )?/0%.?,/!$ 4DGC?OL?ON 4DGC?OL?ON &!5,4$%4%#4)/.25..).' ./&!5,4 ./&!5,4 ,OW3IDE$RIVER#OMMAND   /54!" /54#$ )?,/!$ )?/0%.?,/!$ 4DGC?OL?ON 4DGC?OL?ON &!5,4$%4%#4)/.25..).' /0%.?,/!$ ./&!5,4 '!0'03 Figure 51. Open load detection during “on” phase #HANGESLOW SIDEDRIVERCOMMAND #HANGESLOW SIDEDRIVERCOMMAND /54!" /54#$ \)LOAD\ /PENLOAD/. &AULT(APPENS !NDITISVALIDATED !FTER4DC?OL?ON &!5,4 $%4%#4)/. 25..).' ,!4#(%$ ,ATCHED/PEN ,OAD/N&AULT )?/0%.?,/!$ 4DGC?OL?ON $)!'./3)3 ./&!5,4 &!5,4$%4%#4)/.25..).' /0%.,/!$ /.,!4#(%$ '!0'03 74/141 DocID027721 Rev 2 L9779WD-SPI Functional description Figure 52. Short to GND detection during “on” phase #HANGESLOWSIDEDRIVERCOMMAND /54!" /54#$ )LOADFROM/54"TO/54! "! /540543(IGH : "! 4DGC?OL?ON 4DGC ?/. \)LOAD\ &AULTAPPEARS ,ATCHED&AULT CLEAREDBY DIAGNOSIS READING )?3# )?/0%.?,/!$ 4DGC?OL?ON &!5,4 $%4%#4)/. 25..).' $)!'./3)3 ./&!5,4 ./ &!5,4 3(/244/'.$ 3(/244/'.$ '!0'03 Table 34. Stepper configuration electrical characteristics Pin Symbol Test condition Min Typ Max Unit OUT(21,22), OUT(23,24), OUT(25,27), OUT(26,28) output voltage OUT(21,22) short to OUT(23,24); OUT(25,27) short to OUT(26,28); 2.3 - 2.7 V HVTH Diagnostic high threshold Driver in OFF condition VOutnorm +120mV - 3 V LVTH Diagnostic low threshold Driver in OFF condition 1.9 - VOutnorm -200mV V IOVC Over current threshold - 1 - 2.1 A Output open load threshold current - 10 - 90 mA Output diagnostic IOUT_PD_A+B pull down current or C+D OFF STATE Vpin = 5 V 200 - 350 µA Output diagnostic IOUT_PU_A+B pull up current OFF or C+D STATE Vpin = 1.5 V 50 - 150 µA Open load resistor threshold Application note 150 - - kΩ Tdgc_ON Deglitch filter time in ON condition Test by scan -25% 10 +25% µs Tdgc_OFF - Test by scan -25% 125 +25% µs Tdgc_ol_on - Test by scan -25% 20 +25% µs VOutnorm OUT A to D I_OPEN_LOAD Ropenl Parameter DocID027721 Rev 2 75/141 140 Functional description L9779WD-SPI Table 34. Stepper configuration electrical characteristics (continued) Pin Symbol OUT21…28 Test condition Min Typ Max Unit -25% 1 +25% ms Tmask_step - Test by scan Tsettle - For information only; No tested 100 - - ms Operating frequency For information only; No tested 50 - - µs T_PWM 6.11.4 Parameter Diagnosis of CPS OUTA, B, C, D when configured as single low side power stages For the low side the diagnosis is the same as LSd (see Section 6.9). Each channel locally detects and writes its own fault or no-fault condition (codified on 2 bit according to Table 27: Fault encoding condition).  Short circuit to battery or overcurrent for all the outputs during ON condition.  Open load or short to GND during OFF condition. The faults are latched and reset at every Read Diag operation. In OFF condition the first fault detected is latched and can be overwritten only by the ON condition fault. 76/141 DocID027721 Rev 2 L9779WD-SPI Functional description Electrical and diagnosis characteristics of OUTA, B, C, D when configured as single power stages Same parameter and diagnosis function as LSd. Table 35. Electrical and diagnosis characteristics of OUTA, B, C, D when configured as single power stages Pin Symbol Parameter Min Typ Max Unit RDS-on LSd Drain source resistance Iload = 0.6 A - - 1.5  IOUTlk Output leakage current Vpin = 13.5 V - - 10 µA Voltage S/R On/off R = 21 Ω, C = 10nF From 80% to 30% of VOUT 2 - 6 V/us Fast VR/S off when an OVC fault happens Load: 8 Ω, 10nF - from 80% to 30% of VOUT 5 - 30 V/µs TTurn-On_ LSd Turn-on delay time From command to 80% VOUT Load: 21 Ω, 10nF - - 6 µs TTurn-Off_ LSd Turn-off delay time From command to 30% VOUT Load: 21 Ω, 10nF - - 6 µs 46 48 50 V Iload = 0.6A; single pulse - - 15 mJ Tc  30 °C; I_OUT_n < 0.45 A 1 Mio cycles - - 6.5 Tc < 80°C; I_OUT_n  0.3A 25 Mio cycle - - 6.5 VS/R VS/R GateKill Vcl OUTA, OUTB, OUTC, OUTD PWclampSP PWclampRP Test condition Output clamping voltage Iload = 0.6A Clamp single pulse ATE test Clamp repetitive pulses Freq = 1 Hz (to be verified) Reliability Tc < 100°C; Test I_OUT_n < 0.3A 20 Mio cycle Tc < 130 °C; I_OUT_n < 0.3 A 5 Mio cycle Reverse voltage Body diode reverse current voltage drop I = -0.6 A DocID027721 Rev 2 mJ - - 6.5 - - 5.5 -0.5 -1 -1.1 V 77/141 140 Functional description L9779WD-SPI Electrical characteristics of OUTA, B, C, D when configured as single power stages connected in parallel When the low side drivers are connected in parallel (in pair) to obtain a low side driver with a lower resistance, OUTA with OUTB and OUTC with OUTD, for example the following parameters are valid: Table 36. Electrical characteristics of OUTA, B, C, D when configured as single power stages connected in parallel Pin Symbol Imax Test condition Typ Max Unit Not tested - 1.2 - A RDS-on LSd Drain source resistance Iload = 1.2 A - - 0.75  IOUTlk Output leakage current - - 10 µA VS/R Voltage S/R on/off 2 - 6 - TTurn-on Turn-on delay time - - 6 µs TTurn-off Turn-off delay time - - 6 µs Over current threshold 2 - 4.2 A (1) Clamp single pulse Iload = 1 A; single pulse(1) - - 25 mJ PWclampRP Clamp repetitive pulses Reliability note: Iload = 0.6 A Freq =10 Hz; 36 Mpulse (1000h) - - 12 mJ IOUT_PD Output diagnostic pull down current off state Vpin = 5 V 50 - 110 µA IOUT_PU Output diagnostic pull up current off state -210 - -108 µA Vclamp Delta clamping voltage between low side to be parallelized -250 - +250 mV PWclampSP (1) 1. Not to be tested, already covered by single low side measure and guaranteed by design. 78/141 Min Output current IOVC OUTA, OUTB, OUTC, OUTD Parameter DocID027721 Rev 2 L9779WD-SPI Functional description (CPS) CONFIG_REG10 Table 37. CPS table single mode parallelism Enable by Diagnostic The table configuration will be active if confi_reg7-bit4 is configured at Zero (Default at 1) If not specified Output Drivers are set as single (not in parallel with any other) Over Current mask time increased to 8 µs 1 0 0 0 OUT22 and OUT24 and OUT27 and OUT28 Low side Parallel OUT24 OUT22 2 LSSingle 0 + 2 LSPar 0 0 1 0 OT27 and OUT28 single + OUT22 and OUT24 parallel OUT24 OUT22 2 LSPar + 2 LSPar 0 0 1 0 0 OT27 and OUT28 single + OUT22 and OUT24 parallel OUT24, OUT22, OUT27 OUT27 3 LSPar 1 1 1 0 0 OUT24 and OUT27 and OUT28 parallel OUT24 Register bit 4Low 7 3 2 1 0 0 OUT24 There are three configurations of CONFIG_REG10 register which allow enabling HS drivers. These configurations shall be used by taking care of not switching on HS and LS drivers simultaneously on the same OUTx path. Note that for Parallel HS configurations, HS diagnostic current is doubled. These configurations allow enabling HS drivers and LS drivers in CPS mode 0 0 0 0 0 0 0 0 Single drivers can be enabled by sending related command Diagnostic 7 6 5 4 3 2 1 0 Enable by Table 38. Three configurations of CONFIG_REG10 register CMD_OUTx OUTx 0 0 0 1 0 0 1 0 OUT25 and OUT26 parallel + OUT22 and OUT24 parallel + all others Single OUT24,OUT25 OUT22 0 0 1 1 0 1 1 0 OUT21 and OUT23 parallel + OUT27 and OUT28 parallel + all others Single OUT23, OUT27 OUT27 Note: When those four single Lside and four single Hside are configured as parallel configuration, for example 2 single Lside stage to 1 Lside stage or 4 single Lside stage to 1 Lside stage, the Rdson could be 1/2 or 1/4 as one single stage, the over current threshold could be roughly double or 4 times as single stage, but the over current detected filter time will be increased to 2 times as single stage from 4 µs typical to 8 µs typical by L9779WD-SPI itself, because each single stage will switch on its own overcurrent threshold no matter the configuration for off stage diagnostic, all thresholds will be kept as single stage whatever the configuration of those 4 Lside/Hside. DocID027721 Rev 2 79/141 140 Functional description 6.12 L9779WD-SPI ISO serial line (K-LINE) Figure 53. ISO serial line (K-LINE) circuit 6" )3/3%2)!, ,).% 6$$?)/ %XTERNAL RESISTOR +?28 TO—# +?,).% 6$$ +?48 FROM—# '!0'03 6.12.1 ISO serial line (K-LINE) functionality description The ISO serial line is an interface containing one bidirectional line for communication between the µP and an external diagnosis tester or antitheft device. In case of ground loss the outputs K_LINE get in high impedance state and can withstand a negative voltage up to -18 V. Short circuit to Vb protection is provided: if the K_LINE pin is shorted to battery the output is switched off after a delay of tfilter_K_LINE and it is necessary an input change to turn on it again. The negative transition at K_LINE pin can be driven with slew-rate limitation for optimizing the EMI behavior. This slew-rate limitation must be enabled via the ISO_SRC bit. The K_TX signal is ignored (K_LINE pin to high level) until the RST pin is asserted. KLINE can work up to 250kHz input frequency in typical application condition. 80/141 DocID027721 Rev 2 L9779WD-SPI Functional description Table 39. ISO serial line (K-LINE) functionality electrical characteristic Pin K_TX Symbol Parameter Test condition Max Unit K_TX input low voltage - -0.3 - 1.1 V VKTXH K_TX input high voltage - 2.3 - VDD +0.3 V TX_KLINE pull-up resistor - 50 - 250 kΩ ITXsink Transmitter input sink current K_LINE = 0, K_TX = High - - 5 µA VKOUTL Transmitter output low voltage Isink_K_LINE = 35 mA, K_TX = Low -1 - 1.5 V Transmitter short circuit current K_LINE = VB, K_TX = Low 60 - 165 mA Test by SCAN 7 10 13 µs Reverse battery or GND loss current Key_on = VB = 0 V K_LINE = -18 V - - 10 mA Under voltage current Key_on = High, K_TX = Low, VB = 13.5 V, K_LINE = -1V - - 1 mA Receiver input hysteresis - 0.08*VB - 0.3*VB V VKINH Receiver input high voltage - 0.7* VB - VB V VKINL Receiver input low voltage - -1 - 0.35*VB V From off to on: VB = 13.5 V, Rext = 510 Ω C = 10 nF to GND 5.3 - 8.8 V/µs RTX_KPU Tfilter_K_LINE Overcurrent filter time IKREV VKH VK_SR K_line voltage slew rate From on to off Depends on external RC load - Transmitter fall time CK_LINE = 10 nF, RK_LINE = 510  - - 10 µs VKRXL K_RX output low voltage VDD_IO = 5 V or 3.3 V Isink = 2 mA - - 0.5 V VKRXH K_RX output high voltage VDD_IO = 5 V or 3.3 V Isource = 2 mA VDD_IO -0.5 - - V T_rK K_RX rise time from 10% to 90% With 20 pF capacitive load - - 2 µs T_fK K_RX fall time from 90% to 10% 20 pF capacitive load - - 2 µs Transmitter turn-on delay time CK_LINE = 10 nF, RK_LINE = 510  - - 5 µs T_fT K_RX K_TX, K_LINE Typ VKTXL IKOS K_LINE Min Tp_HLT DocID027721 Rev 2 81/141 140 Functional description L9779WD-SPI Table 39. ISO serial line (K-LINE) functionality electrical characteristic (continued) Pin K_LINE, K_RX Symbol Parameter Test condition Min Typ Max Unit TpHLK K_RX turn-on delay time Cload = 20 pF - - 4 µs TpLHK K_RX turn-off delay time Cload = 20 pF - - 4 µs Figure 54. ISO serial line switching waveform 6$$( +?48  6 TP(,4 6"  +?,).%    6 TF4 TP(,+ 6$$( TP,(+   +?28    6 TF+  TR+ '!0'03 Figure 55. ISO serial line: short circuit protection 6$$( +?48 6 )3# )?+,).% ! 6" +?,).% 6 3(/24#)2#5)44/6" 82/141 DocID027721 Rev 2 '!0'03 L9779WD-SPI 6.13 Functional description CAN transceiver Figure 56. CAN transceiver diagram #!.3%2)!,,).% 6$$ 6 $$ 0/7%2 #/.42/, #!.?48 6$$ #!.?28 #!.(  #!., 28?%#( / '!0'03 6.13.1 CAN transceiver functionality description The CAN bus transceiver allows the connection with a microcontroller through a high speed CAN bus with transmission rates up to 1Mbit/s. The transceiver has one logic input pin (CAN_TX), one logic output pin (CAN_RX) and two input/output pins for the electrical connections to the two bus wires (CANH and CANL). The microcontroller sends data to the CAN_TX pin and it receives data from the CAN_RX pin. In case of power loss (VB pin disconnected) or ground loss (GND pins disconnected), the transceiver doesn't disturb the communication of the remaining transceivers connected to the bus. If CANL is shorted to ground, the transceiver is able to operate with reduced EMI/RFI performances. TX or RX=0 means Dominant state of CANH and CANL; TX or RX=1 means Recessive state compliant to ISO11898-2.  Speed communication up to 1Mbit/s  Function range from +40 V to -18 V DC at CAN pins  GND disconnection fail safe at module level  GND shift operation at system level  ESD: Immunity against automotive transients per ISO7637 specification  Matched output slopes and propagation delay. The CAN_TX signal is ignored (CAN to recessive state) until the RST pin is asserted. DocID027721 Rev 2 83/141 140 Functional description L9779WD-SPI CAN error handling The L9779WD-SPI provides the following 4 error handling features that are realized in different stand alone CAN transceivers / micro controllers to switch the application back to normal operation mode. If one of the below fault happens the status bit CAN_ERROR is set. The error handling features can be disabled through the CAN_ERR_DIS bit. 1. Dominant CAN_TX time out If CAN_TX is in dominant state (low) for t > tdom (TxD) the transmitter will be disabled, status bit will be latched and can be read and cleared by SPI. The transmitter remains disabled until the status register is cleared. 2. CAN permanent recessive If CAN_TX changes to dominant (low) state but CAN bus (CAN_RX pin) does not follow for 4 times, the transmitter will be disabled, status bit will be latched and can be read and cleared by SPI. The transmitter remains disabled until the status register is cleared. 3. CAN permanent dominant If the CAN bus state is dominant (low) for t > tCAN a permanent dominant status will be detected. The status bit will be latched and can be read and cleared by SPI. The transmitter will not be disabled. 4. CAN_RX permanent recessive If CAN_RX pin is clamped to recessive (high) state, the controller is not able to recognize a bus dominant state and could start messages at any time, which results in disturbing the overall bus communication. Therefore, if RX_ECHO does not follow CAN_TX for 4 times the transmitter will be disabled. The status bit will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared. CAN transceiver electrical characteristics Table 40. CAN transceiver electrical characteristics Pin Symbol Test conditions Min Typ Max Unit VTX_CANLOW Input voltage dominant level Active mode -0.3 - 1.1 V VTX_CANHIGH Input voltage recessive level Active mode 2.3 - VDD +0.3 V VTX_CANHYS VTX_CANHIGHVTX_CANLOW Active mode 0.25 0.5 - V RTX_CANPU CAN_TX pull up resistor Active Mode 50 - 250 k - 0.5 V - - V CAN_TX VRX_CANLOW Output voltage dominant level VRX_CANHIGH Output voltage recessive level CAN_RX 84/141 Description Active mode, VDD_IO = 5 V or 3.3 V, 2 mA VDD_IO -0.5 DocID027721 Rev 2 L9779WD-SPI Functional description Table 40. CAN transceiver electrical characteristics (continued) Pin Symbol Description Test conditions VCANHdom CANH voltage level in dominant state VCANLdom CANL voltage level in dominant state Differential output voltage in dominant VDIFF,domOUT state: VCANHdomVCANLdom VCM Driver symmetry: VCANHdom+VCANLdo Active mode; VTXCAN = VTXCANLOW; RL = 60 Ω RL = 60 Ω; CSPLIT = 4.7 nF; m CAN_H CAN_L VCANHrec CANH voltage level in recessive state VCANLrec CANL voltage level in recessive state VDIFF,recOUT Differential output voltage in recessive state: VCANHrecVCANLrec VCANHL,CM Common mode bus voltage IOCANH,dom IOCANL,dom Min Typ Max Unit 2.75 - 4.5 V 0.5 - 2.25 V 1.5 - 3 V 0.9* 1.1* V VCANSUP CANSUP VCANSUP V 2 2.5 3 V 2 2.5 3 V -50 - 50 mV -12 - +12 V Active mode; CANH output current VTX_CAN = VTX_CANLOW; in dominant state VCANH = 0 V -100 -75 -45 mA Active mode; CANL output current VTX_CAN = VTX_CANLOW; in dominant state VCANL = 5 V 45 75 100 mA Input leakage current Unpowered device; VBUS = 5 V 0 - 250 µA Rin Internal resistance Active mode VTX_CAN = VTX_CANHIGH; No load 25 - 45 kΩ Rin,diff Differential internal resistance Active mode & STBY mode; VTX_CAN = VTX_CANHIGH; No load 50 - 85 kΩ Cin Internal capacitance Guaranteed by design - 20 - pF Cin,diff Differential internal capacitance Guaranteed by design - 10 - pF VTHdom Differential receiver threshold voltage recessive to dominant state Active mode - - 0.9 V ILeakage VTX_CAN = VTX_CANHIGH; No load Application info: Measured with respect to the ground of each CAN node DocID027721 Rev 2 85/141 140 Functional description L9779WD-SPI Table 40. CAN transceiver electrical characteristics (continued) Pin CAN_H CAN_L Symbol Description Test conditions Min Typ Max Unit 0.5 - - V VTHrec Differential receiver threshold voltage dominant to recessive state Active mode SRH CANH slew rate between 10% and 90% - 5 - 35 V/µs SRL CANL slew rate between 10% and 90% - 5 - 35 V/µs DIFF_SR Slew rate difference between CANH and CANL - - - 60 % SRVDIFF Slew rate of Vdiff = VCANH-VCANL - 12 - 100 V/µs VTHdom - VTHrec hysteresis - 25 - 50 mV VTHhys Table 41. CAN transceiver timing characteristics Symbol tTXpd,hl tTXpd,lh tdom(TX_CAN) tCAN 86/141 Description Propagation delay TX_CAN to RX_CAN (High to Low) Guaranteed by design. Propagation delay TX_CAN to RX_CAN (Low to High) Guaranteed by design. Test conditions Min Typ Max Unit Active mode; 50% VTX_CAN to 50% VRX_CAN; CL=100 pF; CRX_CAN = 15 pF; RL = 60 Ω; 0 - 255 ns CRX_CAN = 100 pF @Troom and Tcold - - 265 ns CRX_CAN = 100 pF @Thot - - 275 ns Active mode; 50% VTX_CAN to 50% VRX_CAN; CL = 100 pF; CRX_CAN = 15 pF; RL = 60 Ω; 0 - 255 ns CRX_CAN = 100 pF @Troom and Tcold - - 265 ns CRX_CAN = 100 pF @Thot - - 275 ns TX_CAN dominant time-out Tested by scan 525 700 875 µs CAN permanent dominant time-out Tested by scan - 700 - µs DocID027721 Rev 2 L9779WD-SPI Functional description Figure 57. CAN transceiver switching waveforms 6 T48PDHL 6 #!.?48   6 T48PDLH 6  6 #!.?28  6 '!0'03 Figure 58. CAN transceiver test circuit #!.?48 6#!.( #!.( #!. 7 42!.3#%)6%2 P& 7 #!.?28 #!., N& 6#!., P& '!0'03 DocID027721 Rev 2 87/141 140 Functional description 6.14 L9779WD-SPI Flying wheel interface function Figure 59. Flying wheel interface circuit 6230 %N?, &CK?623 6DD )REF 2ELUCTANCE6ARIABLE (ALLEFFECT 3ENSOR 0ASSIVE &ILTER 623. 3-!24 623 /54?623 3ERIALINTERFACE $IAGNOSIS PROGRAMMING 623VOLTAGE !UTOADAPTATIVE )NT?VRS (YSTERESIS !UTOADAPTATIVE 4IMEFILTERINGBLOCK /UT?VRS '!0'03 6.14.1 Flying wheel interface functionality description The flying wheel interface is an interface between the microprocessor and the flying wheel sensor: it handles signals coming from magnetic pick-up sensor or Hall Effect sensor and feeds the digital signal to Microcontroller that extracts flying wheel rotational position, angular speed and acceleration. This circuit implements an auto adaptative hysteresis and filter time algorithm that can be configured via SPI using VRS_mode bit. If the auto adaptive hysteresis is OFF the hysteresis value can be selected using VRS_Hyst bit. If fault is present (OL / SC GND / SC VB) the functionality is not guaranteed. 6.14.2 Auto-adaptive sensor filter Two main VRS configuration sets are available for VRS, by mans of CONFIG_REG1 register: fully adaptive VRS mode (default) and limited adaptive VRS mode. Auto-adaptative hysteresis (fully adaptive mode) When enabled the auto adaptative hysteresis works as described below. Input signals difference is obtained through a full differential amplifier; its output, DV signal, is fed to peak detection circuit and then to A/D converter implemented with 4 voltage comparators (5 levels) (Pvi). Output of A/D is sent to Logic block (Table 43: Hysteresis threshold precision) that implements correlation function between Peak voltage and hysteresis value; hysteresis value is used by square filtering circuit which conditions DV signal. 88/141 DocID027721 Rev 2 L9779WD-SPI Functional description Figure 60. Auto adaptative hysteresis diagram (YSTERESIS3QUARER#IRCUITAND 4EMPORAL&ILT ERING  623VOLTAGE )NT ?VRS ? $6 (YSTERESIS 6ALUE ( ( 06I (YSTERESIS 3ELECTION 4ABLE 0EAK$ETECTION #IRCUIT !$CONVERTER 06 (YSTERESYSOUTPUT CURRENT (  (  (  (  (   06 06 06 06 1UANTIZEDPEAKDETECTOR OUTPUTVOLTAGE;M6= '!0'03 Figure 61. VRS interface block diagram .RKP 9563 6:,7&+ 6(1625 99  .RKP &/$03 9&0 ',$* .RKP $GDSWLYH)LOWHU  ILOWHUWLPHRQULVLQJHGJHDQG PDVNLQJWLPHRQIDOOLQJHGJH  ILOWHU WLPHRQERWKULVLQJDQGIDOOLQJHGJH $GDSWLYH)LOWHU &203  .RKP 9561 9 6SLELWV   )$8/7 PX[ 6SLELWV   99 3HDN 'HWHFWRU 7KUHVKROG 6HOHFWRU 'HFRGHU &XUUHQW *HQHUDWRU '!0'03 DocID027721 Rev 2 89/141 140 Functional description L9779WD-SPI Table 42. Pick voltage detector precision Pick voltage [PV] Min Typ Max Unit PV1 600 930 1300 mV PV2 1200 1600 1950 mV PV3 1990 2300 2600 mV PV4 2660 3000 3380 mV Table 43. Hysteresis threshold precision Value Hysteresis current [H] Note: Unit Correspondent value on 20 kΩ ext. resistor Unit Min Typ Max Typ HI1 3 5 7 µA 100 mV HI2 7 10 13.5 µA 200 mV HI3 12.8 17 23 µA 347 mV HI4 23 32 41 µA 644 mV HI5 35 51 65 µA 1020 mV For a single IC, there is no overlap of parameters PVX (PV1 7 and sequencer-run RST_CNT new 000 .. 111 no = RST_CNT old ‘0’, no monitoring module reset 000 .. 110 yes = RST_CNT old + 1 ‘1’, thus monitoring module reset 111 yes = RST_CNT old =111 ‘0’, no monitoring module reset WD_RST In a factory testmode the pin [WDA] is always active '0'; the internal signal is not changed by the factory testmodes. Note: There is no impact on internal power stages from active pin [WDA] in factory testmode. DocID027721 Rev 2 103/141 140 Functional description L9779WD-SPI Table 50. Reset-behaviour of , AB1 and Signal Reset source Reset state WDA_INT RST_UV ‘1‘, i.e. pin WDA is active AB1 RST_UV ‘0‘, i.e. inactive WD_RST RST_UV ‘0‘, i.e. inactive Response comparison The 2-bit counter counts the received bytes of the 32-bit response and controls the generation of the expected response. Its default value is "11" (corresponds to "waiting for RESP_BYTE3"). The flag is set '1' when a response byte is incorrect. The flag remains '0' if the 32-bit response is correct. The ERROR COUNTER is updated with the flag. The default state of the flag is '0'. The 2-bit counter and the flag are reset to their corresponding default values at a sequencer-run. The reset condition of the counter and the flag are the corresponding default states. Procedure of the sequential response comparison: = "11": switch the expected response for RESP_BYTE3 to the comparator Write access: RESP_BYTE3 Set to "10", update flag = "10": switch the expected response for RESP_BYTE2 to the comparator Write access: RESP_BYTE2 set to "01", update flag = "01": switch the expected response for RESP_BYTE1 to the comparator Write access: RESP_BYTE1 set to "00", update flag = "00": switch the expected response for RESP_BYTE0 to the comparator Write access: RESP_BYTE0 Start sequencer (SEQU_START signal), set to "11", update flag (update ERROR COUNTER) Sequencer clears flag to '0 SEQU_START = 104/141 (RESP_CNT1) AND RESP_CNT0) AND “response byte write” DocID027721 Rev 2 L9779WD-SPI Functional description Expected Responses: RESP_SOLL7 = REQU2 XOR RESP_CNT0 RESP_SOLL6 = REQU0 XOR RESP_CNT0 RESP_SOLL5 = REQU3 XOR RESP_CNT0 RESP_SOLL4 = REQU1 XOR RESP_CNT0 RESP_SOLL3 = ((REQU2 XOR REQU0) XOR REQU3) XOR RESP_CNT1 RESP_SOLL2 = ((REQU0 XOR REQU3) XOR REQU1) XOR RESP_CNT1 RESP_SOLL1 = ((REQU2 XOR REQU0) XOR REQU1) XOR RESP_CNT1 RESP_SOLL0 = (RESP_CNT1 XOR REQU3) XOR REQU0 Table 51. Expected responses question REQU (3-0) RESP_BYTE3 RESP_BYTE2 RESP_BYTE1 RESP_BYTE0 0 FF 0F F0 00 1 B0 40 BF 4F 2 E9 19 E6 16 3 A6 56 A9 59 4 75 85 7A 8A 5 3A CA 35 C5 6 63 93 6C 9C 7 2C DC 23 D3 8 D2 22 DD 2D 9 9D 6D 92 62 A C4 34 CB 3B B 8B 7B 84 74 C 58 A8 57 A7 D 17 E7 18 E8 E 4E BE 41 B1 F 01 F1 0E FE DocID027721 Rev 2 105/141 140 Functional description L9779WD-SPI Reset behaviour All monitoring module registers are reset by RST_UV The following monitoring module components are also reset by RST_PRL: Table 52. Reset behaviour Component: Reset Condition: ERROR COUNTER 110b Register for “EC>7” ‚0‘ Register RESPTIME Maximum value: 0011 1111b timer state Note: “000...00” The signal RST_PRL (partial reset) is active when RST or SW_RST (Softreset) is active. Access during a sequencer-run A sequencer-run (which means the same as a monitoring cycle) is initiated by the writing of a response (i.e. all answer bytes ) or a write to or by reaching "end of time window". It must not be interrupted by a new access, i.e. the monitoring module completes the action already started:  A sequencer-run was initiated by a "response write": The sequencer completes its task with the data of the previous access and the new data are ignored.  A sequencer-run was initiated by a "response-time write": The sequencer uses the response-time of the previous access, the error counter is correspondingly incremented by one and the bit (REQUHI register) is set and the new data are ignored. will be reset by reading and by the next start of a sequencer run (not reset by the sequencer run that is started by a "response-time write"!)  A sequencer-run was initiated by "end of time window": The sequencer finishes the started run, the error counter is incremented by one and the new data are ignored. The writing of a response-time during a sequencer-run must not set the bit (REQUHI register). The new response-time value is also not accepted. The writing of a response during a sequencer-run must not set the bit, the new response is also not accepted. Clock and time references The monitoring module must work independently of the micro-controller clock so that it can monitor the timing of the micro-controller. Therefore, a separate oscillator is necessary. This oscillator is integrated in the L9779WD-SPI and provides a clock CLK1 for the monitoring module. Clocked with CLK1, a divider generates the base time of 101*1/f_clk = 101 * 1/64kHz = 1.58 ms for the response-time and 8 * 101*1/64kHz =8* 1.58 ms = 12.6 ms for the fixed time window. Accuracy of CLK1 is ±5% (or better). The response-time is adjustable by the controller in the range 0ms to about 100ms (register RESPTIME). The response-time can be calculated with the equation responsetime=(1+101*RESPTIME)*1/f_clk (where f_CLK depends on CONFIG6 bit1 value: if High default- f_clk = 64 kHz, if Low f_clk = 39 kHz). The RESPTIME register is set to '0011 1111'b after a reset. The ERROR COUNTER is incremented by one if the controller changes the response-time. If the response-time is set 106/141 DocID027721 Rev 2 L9779WD-SPI Functional description to 0ms, then the ERROR COUNTER is incremented by one even if a correct response is received within the time window. The maximum error reaction time is given by: maximum response-time, response at the end of a time-window and ERROR COUNTER 0 ' 5 * (100ms + 12.6ms) = 563ms. Note that clock-tolerances have to be taken into account additionally. Watchdog influence on power up/down management unit The watchdog AB1 counter is increased every time the watchdog error counter is EC > 7, which means it has an overflow. If the AB1 counter reaches the value of 7 and a further error occurs, the system will be switched off same as it would happen in case of the already existing PWL_EN_TIMEOUTN signal. Watchdog influence on smart power reset WDA has influence on the RST pin only if the WDA error counter is EC > 7 and the resulting reset signal "WD_RST" is enabled by SPI configuration bit "INIT_WDR" in WR_RESPTIME command. Watchdog influence on Lsa functions (Section 6.8.1) For LSa functions OUT1, OUT2, OUT3, OUT4 (not OUT5). In case of an internal WDA event (e.g. the WDA error counter is EC > 4 which results in the signal WDA_INT being set) or in case of the WDA pin being pulled low externally, the output stages OUT1, OUT2, OUT3, OUT4 go to inactive state. Watchdog influence on LSd functions OUT13, OUT14 (starter relay drivers) Section 6.8.4 In case of an internal WDA event (e.g. the WDA error counter is EC > 4 which results in the signal WDA_INT being set) or in case of the WDA pin being pulled low externally, the OUT13 and OUT14 stages go to inactive state after the time delay THOLD if the WDA event is still active. Watchdog influence on Ignition drivers IGN1, IGN2, IGN3, IGN4 In case of an internal WDA event (e.g. the WDA error counter is EC > 4 which results in the signal WDA_INT being set) or in case of the WDA pin is pulled low externally, the output stages go to inactive state. Watchdog influence on CAN transceiver The WDA has influence on the CAN if the SPI configuration bit CAN_TDI is set. Once the CAN_TDI bit is set, in case of an internal WDA event (e.g. the WDA error counter is EC > 4 which results in the signal WDA_INT being set) or in case of the WDA pin is pulled low externally, the CAN goes to receive-only mode (RxOnly). DocID027721 Rev 2 107/141 140 Functional description 6.16 L9779WD-SPI Serial interface The L9779WD-SPI offers the possibility to communicate with a £gC using the Serial Peripheral Interface (SPI). The serial communication is used: 6.16.1  to set the parameter  to read diagnosis  to activate, to deactivate and to use the Query/Answer protocol  to activate, to deactivate and to use the low side drivers  to activate test mode (ST reserved) SPI interface The SPI interface consists of an input shift register, output shift register and four control signals. DIN is the data input to the input shift register. DO is the data output from the output shift register. SCK is the clock source input while CS is the active low chip select input. 6.16.2 SPI protocol All SPI communications are executed in exact 16 bit increments. The L9779WD-SPI contains a data validation method through the SCK input to keep transmissions with not exactly 16 bits from being written to the device. The SCK input counts the number of received clocks and should the clock counter exceed or count fewer than 16 clocks, the received message is discarded without changes to internal registers. The general format of the 16 bit transmission for global SPI interface is shown here below: D15 DIN DO X D14 D13 D12 D11 D10 ADD(4) ADD(3) ADD(2) ADD(1) ADD(0) D9 D8 X SPI ADD(4) ADD(3) ADD(2) ADD(1) ADD(0) W/R error D7 D6 D5 D4 D3 D2 D1 D0 DATA IN or SUBADDRESS (if ADD[4:0]= 0x10) Parity DATA OUT Parity Data to the device (i.e. DIN) consists of a five address bit, eight data bit and data parity. DIN data is the data to be written to the register indicated by address bit. Data returned from the device (i.e. DO) consists of SPI error bit, five address bit, eight data bit and data parity. DO data will be the contents of the register indicated by the address bits. The communications is controlled through CS, enabling and disabling communication. When CS is at logic high, all SPI communication I/O is tri-stated and no data is accepted. When CS is low, data is latched on the rising edge of SCLK and data is shifted on the falling edge. The DIN pin receives serial data from the master with MSB first. Likewise for DO, data is read MSB first, LSB last. The failed transmission is indicated in the SPI_ERR bit. Table 55 reports register addresses. Registers differ between write-only and read-only registers. Write-only registers return all zeroes in MISO DO-DATA OUT field of next frame, with the exception of CLOCK_UNLOCK_RSRST and START_REACT, which return LOCK and OUT_DIS status bit. 108/141 DocID027721 Rev 2 L9779WD-SPI Functional description Read-only registers (ID and Diagnostic) have unique address 0x10 and are selected by 5bit sub-address in MOSI DI-DATA IN field. MISO DO returns 1 at D9 bit and 5bit sub address in ADD[4:0] field. Timing characteristics Figure 73. Timing characteristics diagram WQRGDWD WODJ &6 WVFONOV WOHDG WFVQ WVFON WVFONKV 6&/. WD '2 06%287 WVXV WKV WGLV '21¶7 &$5( /6%287 '$7$ 06%,1 ', WVK WKR WYV WU WI '$7$ /6%,1 *$3*36 Table 53. Timing characteristics Symbol Parameter Conditions Min Max Units fop Transfer frequency Design Information - 8 MHz tsclk SCK period Design Information 125 - ns tlead Enable Lead time Design Information 525 - ns tlag Enable lag time Design Information 50 - ns tsclkhs SCK high time Design Information 38 - ns tsclkls SCK low time Design Information 38 - ns tsus DIN input setup time Design Information 20 - ns ths DIN input hold time Design Information 20 - ns ta DO access time 50 pF load - 60 ns dis DO disable time 50 pF load - 100 ns t vs DO output valid time 50 pF load - 66 ns ho DO output hold time 50 pF load 0 - ns tr DO rise time 50 pF load - 30 ns tf - 30 ns t t DO fall time 50 pF load tcsn CS negated time Design Information 640 - ns tsh SCK hold time Design Information 20 - ns CS noise glitch rejection time - 50 300 ns SPI interframe time Design Information 1.5 - µs tcsgrt tnodata DocID027721 Rev 2 109/141 140 Functional description L9779WD-SPI Electrical characteristics - Pin SCK Symbol CS Min Typ Max Unit - -0.3 - 1.1 V SCKH High input level - 2.3 - VDD5 +0.3 V VHYST Hysteresis - 0.1 - - V Input current - - 5 µA SCKL Low input level - -0.3 - 1.1 V SCKH High input level - 2.3 - VDD5 +0.3 V VHYST Hysteresis - 0.1 - - V Input current - - - 5 µA VDO_L DO output low level Isink current = 2 mA - - 0.5 V VDO_H DO output high level Isource current = 2 mA VDD5 -0.5 - - V ENL Low input level - -0.3 - 1.1 V ENH High input level - 2.3 - VDD5 +0.3 V VHYST Hysteresis - 0.1 - - V Input current - - - 5 µA Pull up resistor - 50 - 250 k IIN RPU 6.16.3 Test condition Low input level IIN DO Parameter SCKL IIN DIN Table 54. Electrical characteristics SPI registers Table 55. SPI registers Register 110/141 R/W Address CONFIG_REG1 W 0x01 CONFIG_REG2 W 0x02 CONFIG_REG3 W 0x03 CONFIG_REG4 W 0x04 CONFIG_REG5 W 0x05 CONFIG_REG6 W 0x06 CONFIG_REG7 W 0x07 CONFIG_REG9/SPI RESPTIME W 0x11 CONFIG_REG10/CPS W 0x12 DocID027721 Rev 2 Description Configuration registers L9779WD-SPI Functional description Table 55. SPI registers (continued) Register R/W Address LOCK_UNLOCK_SW_RST W 0x0C Disable writing of all configuration bits/ software reset for the device START_REACT W 0x0D Enable power stages/MRD reactivate Communicate the WD appropriate answer to WD query/U1A9 WDA Response to query WD_ANSW/WDA RESP CONFIG_REG8 W 0x0E CONTR_REG1 W 0x08 CONTR_REG2 W 0x09 CONTR_REG3 W 0x0A CONTR_REG4 W 0x0B Description Control register to switch on/off the OUT Following Registers have 0x10+subaddress SPI format IDENT_REG R 0x10+0x00 DIA_REG1 R 0x10+0x01 DIA_REG2 R 0x10+0x02 DIA_REG3 R 0x10+0x03 DIA_REG4 R 0x10+0x04 DIA_REG5 R 0x10+0x05 DIA_REG6 R 0x10+0x06 DIA_REG7 R 0x10+0x07 DIA_REG8 R 0x10+0x08 DIA_REG9 R 0x10+0x09 DIA_REG10 R 0x10+0x0A DIA_REG11 R 0x10+0x0B DIA_REG12 R 0x10+0x0C Diagnostic register 12 DIA_REG13 R 0x10+0x0D WDA RESPTIME DIA_REG14 R 0x10+0x0E WDA REQULO DIA_REG15 R 0x10+0x0F WDA REQUHI DIA_REG16 R 0x10+0x10 DocID027721 Rev 2 Identifier (000) Diagnosis information of device WDA RST_AB1_CNT 111/141 140 Functional description L9779WD-SPI Command register Table 56. CLOCK_UNLOCK_SW_RST Bit DIN DO 15 X SPI ERROR 14 ADD(4) ADD(4) 13 ADD(3) ADD(3) 12 ADD(2) ADD(2) 11 ADD(1) ADD(1) 10 ADD(0) ADD(0) 9 X 0 8 X 0 7 X 0 6 X 0 5 X 0 4 X 0 3 X 0 2 SW_RESET 0 1 LOCK LOCK 0 Odd Parity Odd Parity This command disables (“lock”) writing of all configuration registers. The commands have no relevant data as command data bit – they may be set to ‘1’ or ‘0’. Default state is configuration registers not locked. The content of lockable bit is valid both if the bits are locked or if they are unlocked. Writing data to the bit is possible if the bits are unlocked; the new values become valid during the execution of the write command. This command generates a L9779WD-SPI internal reset initiated by the µC’s software (“software reset”) that clears all the configuration and diagnostic registers and switch-off all the drivers. The command has no relevant data as command data bit – they may be set to ‘1’ or ‘0’. Table 57. START_REACT 112/141 Bit DIN DO 15 X SPI ERROR 14 ADD(4) ADD(4) 13 ADD(3) ADD(3) 12 ADD(2) ADD(2) 11 ADD(1) ADD(1) DocID027721 Rev 2 L9779WD-SPI Functional description Table 57. START_REACT (continued) Bit DIN DO 10 ADD(0) ADD(0) 9 X 0 8 X 0 7 X 0 6 X 0 5 X 0 4 X 0 3 STOP 0 2 START 0 1 MRD_REACT OUT_DIS 0 Odd Parity Odd Parity The command START sets the bit to ‘0’. With = ‘0’ the outputs [OUT1...OUT10] [OUT13…OUT28] and [IGN1...IGN4] can be activated using control registers. After a reset (default state) the bit is =’1’ and the outputs are disabled (so any SPI data frame writing control registers is ignored and the power stages are all switched off). The command has no relevant data as command data bit – they may be set to ‘1’ or ‘0’. This command allows the µC turning on the MRD if it is switched off due to over current. DocID027721 Rev 2 113/141 140 Functional description L9779WD-SPI Configuration registers CONFIG_REG1 7 Configuration register 1 6 5 1 0 RESERVED 4 VRS mode MRD_OT_DID - W W Address: 0 0001 Type: W (write access: WRITE_CONFIG1) Reset: 0000 1000 3 2 [7:5] RESERVED [4:2] RESERVED [1] VRS mode: 0 = limited adaptive (default) 1 = full adaptive [0] MRD_OT_DIS: Disables OT switch_off for MRD: 0 = MRD OT switches off the driver 1 = MRD OT does NOT switch off the driver CONFIG_REG2 7 6 Configuration register 2 5 1 0 RESERVED 4 Charge pump OFF LS_IGN_OFF - W W Address: 0 0010 Type: W (write access: WRITE_CONFIG2) Reset: 3 0000 1000 [7:5] RESERVED [4:2] RESERVED [1] Charge pump OFF 0= ON (default) 1= OFF [0] LS_IGN_OFF Control LS stage of IGN driver 0 = normal behaviour 1 = LS of IGN driver always OFF 114/141 DocID027721 Rev 2 2 L9779WD-SPI Functional description CONFIG_REG3 7 6 Configuration register 3 5 4 3 2 RESERVED 1 0 EN_FALLING_FILT - HYS_FB_SEL W Address: 0 0011 Type: W (write access: WRITE_CONFIG3) Reset: 0000 1000 [7:5] RESERVED [4:2] RESERVED [1] EN_FALLING_FILT: 0 = Falling edge filter disabled 1 = Falling edge filter enabled [0] HYS_FB_SEL: 0 = VRS hyst. Feedback connected before adaptative filter 1 = VRS hyst. Feedback connected after adaptative filter DocID027721 Rev 2 115/141 140 Functional description L9779WD-SPI CONFIG_REG4 7 Configuration register 4 6 5 PWL_TIMEOUT_CONF[2:0] 4 OFF_LCDR 3 2 RESERVED W 0 LOCK - Address: 0 0100 Type: W (write access: WRITE_CONFIG4) Reset: 1 ISO_SRC W 0000_0010 [7:5] PWL_TIMEOUT_CONF[2:0]: Power latch mode time-out configuration. 000: Disabled (default) 001: 4.7 minutes ±5% 010: 9 minutes ±5% 011: 19 minutes ±5% 100: 28 minutes ±5% 101: 37 minutes ±5% 110: 75 minutes ±5% 111: 470 ms ±5% [4] OFF_LCDR: Off state diagnosis for Low-current drive 1 = Off state diagnosis and the bias current of OUT20 is active 0 = Off state diagnosis and the bias current of OUT20 is disabled [3:2] RESERVED [1] ISO_SRC: Slew-rate control for the ISO9141 serial interface (K-Line) 0 = No slew rate limitation 1 = Slew-rate limitation active [0] LOCK: Lock bit status. Set by LOCK command and cleared with UNLOCK command 1 = ALL configuration registers are locked and cannot be changed 0 = all configuration registers can be changed 116/141 DocID027721 Rev 2 L9779WD-SPI Functional description CONFIG_REG5 Configuration register 5 7 6 5 4 3 2 1 0 RESERVED RESERVED VRS_DIAG VRS_MODE1 VRS_MODE0 VRS_HYST2 VRS_HYST1 VRS_HYST0 - - W Address: 0 0101 Type: W (write access: WRITE_CONFIG5) Reset: 1101_1000 [7:6] RESERVED: not used [5] If fully adaptive mode selected: VRS diag: VRS diagnosis enable 1: diagnosis function is enabled 0: diagnosis function is disabled If limited adaptive mode selected: Forces VRS minimum hysteresis (5 μA) 1: minimum hysteresis forced 0: normal operation as per VRS_HYST configuration [4:3] VRS_MODE 00: Internal auto-adaptive hysteresis OFF, internal auto-adaptive filter time OFF 01: Internal auto-adaptive hysteresis ON, internal auto-adaptive filter time OFF 10: Internal auto-adaptive hysteresis OFF, internal auto-adaptive filter time ON 11: Internal auto-adaptive hysteresis ON, internal auto-adaptive filter time ON [2:0] VRS_HYST 000: Hys current = 17 µA (Hys VRS = 347 mV with 10 k ext resistors) [default] 001: Hys current = 5 µA (Hys VRS=100mV with 10 k ext resistors) 010: Hys current = 10 µA (Hys VRS=200mV with 10 k ext resistors) 011: Hys current = 17 µA (Hys VRS=347mV with 10 k ext resistors) 100: Hys current = 32 µA (Hys VRS=644mV with 10 k ext resistors) 101: Hys current = 51 µA (Hys VRS=967mV with 10 k ext resistors) 110: Hys current = 17 µA (Hys VRS=347mV with 10 k ext resistors) 111: Hys current = 0 µA (used only for test purpose) Note: When VRS limited amplitude adaptive mode is set, VRS_HYST limits the minimum hysteresis to the set value. When VRS limited mode is set, filter time must be enabled at operation start, and shall never be disabled afterwards. When VRS limited mode is set, VRS diagnostic function is not available. DocID027721 Rev 2 117/141 140 Functional description L9779WD-SPI CONFIG_REG6 Configuration register 6 7 6 5 4 3 2 1 0 CAN_ERR_EN NL_RST PWL_EN_N/ SEO_EN_N PSOFF VDD5_UV RST mask VDD5_UV WDA mask WDA time base setting (RESPTIME) PWL/SEO timeout W Address: 0 0110 Type: W (write access: WRITE_CONFIG6) Reset: 0010 0010 [7] CAN_ERR_EN: CAN error handling 1: CAN error handling enabled 0: CAN error handling disabled [6] NL_RST: Reset generation during Power latch mode when KEY_ON 0 --> 1 1: reset generated 0: reset not generated [5] PWL_EN_N: Power latch mode enable PWL_EN_N/SEO_EN_N: Power latch/secure engine off mode enable 1: power latch mode function is disabled (default) 0: power latch mode function is enabled [4] PSOFF: Power supply off (VDD5, VTRK1, VTRK2, Charge-pump, internal supply) when KEY_ON = 0 and PWL_EN_N = 0 0: switch off power supply and switch off MRD 1: do not switch off power supply and switch off MRD [3] VDD5_UV RST mask 1: mask VDD5_UV with generating RST event 0: mask removed (default), VDD5_UV event generates RST [2] VDD5_UV WDA mask 1: mask VDD5_UV with generating WDA event 0: mask removed (defualt). Any VDD5_UV event pulls WDA pin low and disables safety drivers [1] WDA time base setting This bit selects the RESPTIME time base 1: (default) sets time base to 1/64 kHz 0: sets time base to 1/39 kHz [0] PWL/SEO timeout 0: PWL timeout counter has priority over SEO (default) 1: SEO timeout counter has priority over PW 118/141 DocID027721 Rev 2 L9779WD-SPI Functional description 6 IGN_DIA_MODE IGN_DIA_SGEN 5 4 3 2 1 0 TD_MASK_X2 CPS/Stepper Unlock OUTA_HS_EN_LB 7 Configuration register 7 OUTC_HS_EN_LB CONFIG_REG7 OUT14_EN_LB OUT13_EN_LB W Address: 0 0111 Type: W (write access: WRITE_CONFIG7) Reset: 0101 0000 [7] IGN_DIA_MODE: IGN diagnosis mode for short to battery: 1: latch mode 0: no latch mode [6] IGN_DIA_SGEN: IGN diagnosis enable for short to ground: 1: Current diagnosis enabled 0: Voltage diagnosis disabled [5] TD_MASK_X2: 0: Td_mask as specified in respective tables for OUT13 to OUT28 1: Td_mask doubled for OUT13 to OUT28 [4] CPS/Stepper Unlock bit: 1: Stepper mode selected (default) 0: CPS mode selected [3] OUTC_HS_EN_LB: Low battery function enable 1: LB function is enabled for OUTC_HS 0: LB function is disabled for OUTC_HS [2] OUTA_HS_EN_LB: Low battery function enable 1: LB function is enabled for OUTA_HS 0: LB function is disabled for OUTA_HS [1] OUT14_EN_LB: Low battery function enable 1: LB function is enabled for OUT14 0: LB function is disabled for OUT14 [0] OUT13_EN_LB: Low battery function enable 1: LB function is enabled for OUT13 0: LB function is disabled for OUT13 Note: The bit OUTA_HS, OUTC_HS_EN_LB has priority over the CPS_CONFx bit, this means that if one of OUT21,25_EN_LB is set to 1 the OUT21…28 become independent power stages. DocID027721 Rev 2 119/141 140 Functional description L9779WD-SPI WD_ANSW/WDA RESP/CONFIG_REG8 7 6 5 4 RESP RESP RESP RESP Configuration register 8 3 2 1 0 RESP RESP RESP RESP W Address: 0 1110 Type: W Reset: [7:0] RESP: the answer of the µC to the monitoring module question of the U-Chip - to the U-Chipinternal logic of the monitoring module. CONFIG_REG9/SPI RESPTIME Configuration register 9 7 6 5 4 3 2 1 0 INIT_WDR CAN_TDI RESPTIME RESPTIME RESPTIME RESPTIME RESPTIME RESPTIME W Address: 1 0001 Type: W Reset: [7] IINIT_WDR (enable WDA reset) [6] CAN_TDI (disable CAN in case of WDA event) [5:0] RESPTIME of the monitoring module 120/141 DocID027721 Rev 2 L9779WD-SPI Functional description CONFIG_REG10 (CPS Configuration register) 7 6 5 4 Configuration register 10 3 2 1 0 see Table 37 CPS_CONF W Address: 1 0010 Type: WR_CPS Reset: [7:1] See Table 37 [0] CPS_CONF (CPS mode is enabled if REG7 bit4 is cleared first) 1: OUTA...OUTD are configured as 2 full-bridge for stepper motor driving (default) 0: OUTA...OUTD are configured as half bridges IDENT_REG/DIA_REG[1:5] 7 DIA_REG1 DIA_REG2 6 5 OUT4_DIAG 0 Diagnostic register 1, 2, 3, 4, 5 4 3 OUT3_DIAG 0 OUT7_DIAG DIA_REG3 OUT14_DIAG OUT13_DIAG DIA_REG4 OUT18_DIAG OUT17_DIAG DIA_REG5 1 0000 Subaddress: 0000 0001, 0000 0010, 0000 0011, 0000 0100, 0000 0101 Type: R (Read only) Reset: 0000 0000 1 OUT5_DIAG 1 0 OUT16_DIAG OUT20_DIAG 0 OUT1_DIAG OUT6_DIAG WDA_STATUS RESERVED Address: 2 OUT2_DIAG 0 OUT15_DIAG 0 0 DIA_REG1:[7:6] OUT4_DIAG: Diagnosis bit of power stage OUT4 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG1:[5:4] OUT3_DIAG: Diagnosis bit of power stage OUT3 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DocID027721 Rev 2 121/141 140 Functional description L9779WD-SPI DIA_REG1:[3:2] OUT2_DIAG: Diagnosis bit of power stage OUT2 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG1:[1:0] OUT1_DIAG: Diagnosis bit of power stage OUT1 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG2:[7:6] 00 DIA_REG2:[5:4] OUT7_DIAG: Diagnosis bit of power stage OUT7 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG2:[3:2] OUT6_DIAG: Diagnosis bit of power stage OUT6 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG2:[1:0] OUT5_DIAG: Diagnosis bit of power stage OUT5 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG3:[7:6] OUT14_DIAG: Diagnosis bit of power stage OUT14 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG3:[5:4] OUT13_DIAG: Diagnosis bit of power stage OUT13 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG3:[3] WDA STATUS: status of WDA pin, not latched DIA_REG3:[2] RESERVED: not used DIA_REG3:[1:0] 00 DIA_REG4:[7-6] OUT18_DIAG: Diagnosis bit of power stage OUT18 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL 122/141 DocID027721 Rev 2 L9779WD-SPI Functional description DIA_REG4:[5-4] OUT17_DIAG: Diagnosis bit of power stage OUT17 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG4:[3-2] OUT16_DIAG: Diagnosis bit of power stage OUT16 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG4:[1-0] OUT15_DIAG: Diagnosis bit of power stage OUT15 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG5:[7:4] RESERVED: All bit read 1 DIA_REG5:[3-2] OUT20_DIAG: Diagnosis bit of power stage OUT20 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG5:[1-0] 00 Note: All diagnosis bits (including OT1, F1, OT2, F2) will be cleared automatically by reading – i.e. if a diagnosis bit indicates a fault this fault has occurred after the last read access to this register. DocID027721 Rev 2 123/141 140 Functional description L9779WD-SPI Diagnostic register 6 and 7 DIA_REG6 Diagnostic register 6 7 Configured as single power stages 6 OUT24_DIAG 5 4 3 OUT23_DIAG Configured as H bridge OUT22_DIAG H1_DIAG Address: 1 0000 Subaddress: 0000 0110 Type: R (Read only) Reset: 0000 0000 Configured as single power stages [7-6] OUT24_diag[1:0]: Diagnosis bit of OUT24 00: Short-circuit to ground 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL [5-4] OUT23_diag[1:0]: Diagnosis bit of OUT23 00: Short-circuit to VB 01: Open load (OL) 10: Short-circuit to GND 11: Power stage OK NO FAIL [3-2] OUT22_diag[1:0]: Diagnosis bit of OUT22 00: Short-circuit to ground 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL [1-0] OUT21_diag[1:0]: Diagnosis bit of OUT21 00: Short-circuit to VB 01: Open load (OL) 10: Short-circuit to GND 11: Power stage OK NO FAIL Configured as H bridge [7-0] H1_diag[7:0]: Diagnosis bit of H1 bridge 00000001: Short to Ground (OFF) 00000101: Short to VBAT (OFF) 00000100: Open Load (OFF) 00000010: Open Load (ON) 00000011: Over current (ON) 00000111: Fault detection running (ON) 11111111: Power stages OK NO FAULT All other combinations: NOT USED 124/141 2 DocID027721 Rev 2 1 0 OUT21_DIAG L9779WD-SPI Functional description DIA_REG7 Diagnostic register 7 7 Configured as single power stages 6 OUT28_DIAG 5 4 3 OUT27_DIAG Configured as H bridge 2 OUT26_DIAG 1 0 OUT25_DIAG H2_DIAG Address: 1 0000 Subaddress: 0000 0111 Type: R (Read only) Reset: 0000 0000 Configured as single power stages [7-6] OUT28_DIAG[1:0]: Diagnosis bit of OUT28 00: Short-circuit to ground 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL [5-4] OUT27_DIAG[1:0]: Diagnosis bit of OUT27 00: Short-circuit to ground 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL [3-2] OUT26_DIAG[1:0]: Diagnosis bit of OUT26 00: Short-circuit to VB 01: Open load (OL) 10: Short-circuit to GND 11: Power stage OK NO FAIL [1-0] OUT25_DIAG[1:0]: Diagnosis bit of OUT25 00: Short-circuit to VB 01: Open load (OL) 10: Short-circuit to GND 11: Power stage OK NO FAIL Configured as H bridge [7-0] H2_diag[7:0]: Diagnosis bit of H2 bridge 00000001: Short to Ground (OFF) 00000101: Short to VBAT (OFF) 00000100: Open Load (OFF) 00000010: Open Load (ON) 00000011: Over current (ON) 00000111: Fault detection running (ON) 11111111: Power stages OK NO FAULT All other combinations: NOT USED DocID027721 Rev 2 125/141 140 Functional description L9779WD-SPI DIA_REG8 7 Diagnostic register 8 6 5 IGN4_DIAG[1:0] IGN3_DIAG[1:0] Address: 1 0000 Subaddress: 0000 1000 Type: R (Read only) Reset: 4 3 2 IGN2_DIAG[1:0] 0000 0000 [7:6] IGN4_DIAG[1:0]: Diagnosis bit of IGN4 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage ok NO FAIL [5:4] IGN3_DIAG[1:0]: Diagnosis bit of IGN3 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage ok NO FAIL [3:2] IGN2_DIAG[1:0]: Diagnosis bit of IGN2 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage ok NO FAIL [1:0] IGN1_DIAG[1:0]: Diagnosis bit of IGN1 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage ok NO FAIL 126/141 DocID027721 Rev 2 1 0 IGN1_DIAG[1:0] L9779WD-SPI Functional description DIA_REG9 Diagnostic register 9 7 6 5 4 KEY_ON_ STATUS MRD_OVC VRS_STAT VRS_DIAG 3 2 VTRK2_DIAG[1:0] 1 0 VTRK1_DIAG[1:0] R/W Address: 1 0000 Subaddress: 0000 1001 Type: R (Read only) Reset: 0000 0000 [7] KEY_ON_STATUS 1: KEY_ON voltage above KEY_ON_H 0: KEY_ON voltage below KEY_ON_L [6] MRD_OVC 1: Current MRD status is OFF due to previous Over current 0: Current MRD status is ON (no OVC detected) [5] VRS_STAT 1: Diag ON 0: Diag OFF [4] VRS_DIAG 0: No Fault 1: Generic fault detected [3-2] VTRK2_DIAG[1:0]: Diagnosis bit of VTRK2 00: Not used 01: Overload condition/out of regulation 10: Overvoltage (OV) or over temperature (OT) (Lower priority respect to Overload condition) 11: Sensor supply VTRK ok NO FAIL [1-0] VTRK1_DIAG[1:0]: Diagnosis bit of VTRK1 00: Not used 01: Overload condition/out of regulation 10: Overvoltage (OV) or over temperature (OT) (Lower priority respect to overload condition) 11: Sensor supply VTRK OK NO FAIL DocID027721 Rev 2 127/141 140 Functional description L9779WD-SPI DIA_REG10 Diagnostic register 10 7 6 5 4 3 2 1 0 TNL_RST F1 CRK_RST F2 VDD5_OV V3V3_UV OUT_DIS OV_RST Address: 1 0000 Subaddress: 0000 1010 Type: R (Read only) Reset: 0000 0000 [7] TNL_RST 0: No reset generated 1: Reset generated by TNL [6] F1 0: No fault 1: any fault occurred in OUT1...10, OUT13...20, IGN1…4 [5] CRK_RST 0: No reset generated 1: Reset generated by VDD_UV (tTHOLD) [2] CAN_ERROR 0: No fault 1: fault present (one of the 4 possible error on CAN) [1] WD_FAULT_LATCHED 1: WDA has generated a RST event 0: no event [0] 0 DocID027721 Rev 2 129/141 140 Functional description L9779WD-SPI Diagnostic register 12 7 6 5 4 3 RESERVED WD_FAULT_LATCHED DIA_REG12 SEO OUT1-4 SEO OUT1314 WD_FAULT Address: 1 0000 Subaddress: 0000 1100 Type: R (Read only) Reset: 0000 0000 2 1 RESERVED 0 KEY_ON_FLT [7] RESERVED [6] WDA_FAULT latched: 1: WDA has generated a RST event 0: no event [5] SEO event when the OUT1-4 are switched off after 225 ms [4] SEO event when the OUT13-14 after 600ms when KEY is OFF [3] WDA_FAULT not latched: 1: WDA has generated a RST event (the DIA_REG12 is read by READ_DATA 7 but the bit WD_FAULT_LATCHED is reset by READ_DATA5). 0: no event [2:1] RESERVED: not used [0] KEY_ON_FLT: Key on after filter 130/141 DocID027721 Rev 2 L9779WD-SPI Functional description Watchdog related SPI registers SPI registers WDA_RESPTIME,REQULO, REQUHI, RST_AB1_CNT are defined as here below: DIA_REG13/WDA_RESPTIME Diagnostic register 13 7 6 5 4 3 2 1 0 0 0 RESPTIME5 RESPTIME4 RESPTIME3 RESPTIME2 RESPTIME1 RESPTIME0 R Address: 1 0000 Subaddress: 0000 1101 Type: R (Read only) Reset: 0011 1111b (reset source: Bit 5-0: RST_UV, RST_PRL; Bit 6-7: RST_UV) [7] 0 [6] 0 [5-0] RESPTIME (5-0): Response-time = (1+ 101*RESPTIME(5-0)) * 1/f_clk with f_clk = 64kHz The error counter is incremented by one on a controller write access to this register! not locked by command LOCK may be written by the command WR_RESPTIME DIA_REG14/REQULO Diagnostic register 14 7 6 5 4 3 2 1 0 WDA_INT ERR_CNT2 ERR_CNT1 ERR_CNT0 REQU3 REQU2 REQU1 REQU0 R Address: 1 0000 Subaddress: 0000 1110 Type: R (Read only) Reset: 1110 0000b (reset source: Bit 6-4: RST_UV, RST_PRL; Bit 7, 3-0: RST_UV) [7] WDA_INT: '1': ERROR COUNTER > 4 [6-4] ERR_CNT (2-0): value of the ERROR COUNTER [3-0] REQU (3-0): 4-bit question DocID027721 Rev 2 131/141 140 Functional description L9779WD-SPI DIA_REG15/REQUHI Diagnostic register 15 7 6 5 4 3 2 1 0 RESP_CNT1 RESP_CNT0 RESP_ERR RESP_Z0 CHRT W_RESP NO_RESP RESP_TO_EAR LY R Address: 1 0000 Subaddress: 0000 1111 Type: R (Read only) Reset: 1100 0000b (reset source: RST_UV, Bit 4 additionally RST_PRL) [7-6] RESP_CNT(1-0): '1': Response before time window was opened; reset to zero at sequencer-run1(1) [5] RESP_ERR: '1': 1 byte of the 32-bit response is incorrect(1) [4] RESP_Z0: '1': Controller set response-time to 0ms; a correct response within the time window nevertheless increments the error counter by one '0': Response-time is greater than 0ms [3] CHRT: '1': Controller has changed response-time; reset to zero after a read access and after the next sequencer run [2] W_RESP: '1': incorrect response in value; reset to zero at sequencer-run (1) [1] NO_RESP: '1': no response; timer is restarted automatically; reset to zero after a read access [0] RESP_TO_EARLY: '1': Response before time window was opened; reset to zero at sequencer-run (1) 1. Sequencer-run: A sequencer-run is initiated by the writing of a complete response (RESP_BYTE3…RESP_BYTE0) or by writing of a response-time or by reaching the end of a time window. In case WDA reference time base (1/f_clk) has to be changed to f_clk = 39 kHz, CONFIG6 bit1 has to be written to 0 before sequencer-run is started. RESP_TO_EARLY = '1': monitoring module has received a response before beginning of the time window and therefore this was rejected. Reception of a response means "end of reception of RESP_BYTE0" after the other response bytes (i.e. RESP_BYTE3, RESP_BYTE2, RESP_BYTE1 - in this order!) have been received. NO_RESP = '1': monitoring module has received no response at all or a response too late after the time window already closed. However, a response too late might be read as RESP_TO_EARLY, as a too late response is at the same time a too early response concerning the next WDG cycle. Which results in the NO_RESP monitoring being overwritten by a RESP_TO_EARLY monitoring. This means that no "end of reception of RESP_BYTE0" was detected before the end of the time window - neither during the time window nor before beginning of the time window. (Remember: RESP_BYTE0 is the last of four response bytes!) 132/141 DocID027721 Rev 2 L9779WD-SPI Functional description W_RESP = '1': an error occurred during the sequencer run before. RESP_ERR = '1': an error occurred during the actual sequencer run. The bit will be set to '1' after receiving any incorrect answer byte and will remain '1' until the end of the actual sequencer run (no matter if the other answer bytes in this sequencer run are correct or not). At the end of a sequencer run the error bit W_RESP will be set to the actual value of RESP_ERR, and thereafter the error bit RESP_ERR will be cleared to '0'. RESP_CNT = '11': waiting for RESP_BYTE3 RESP_CNT = '10': waiting for RESP_BYTE2 (after RESP_BYTE3 was received) RESP_CNT = '01': waiting for RESP_BYTE1 (after RESP_BYTE2 was received) RESP_CNT = '00': waiting for RESP_BYTE0 (after RESP_BYTE1 was received) DIAG_REG16/RST_AB1_CNT Diagnostic register 16 7 6 5 4 3 2 1 0 0 0 AB1_CNT2 AB1_CNT1 AB1_CNT0 RST_CNT2 RST_CNT1 RST_CNT0 R Address: 1 0000 Subaddress: 0001 0000 Type: R (Read only) Reset: 0000 0000b (reset source: Bit 6…0: only RST_UV; RST_PRL has no effect) [7] 0 [6] 0 [5-3] AB1_CNT (2-0) [2-0] RST_CNT (2-0) reset counter RST_CNT DocID027721 Rev 2 133/141 140 Functional description L9779WD-SPI Control registers CONTR1 to 4 They control the output stages OUT1…10, OUT13…20, OUT21…28 and IGNn. CMD = 1 OUTPUT ONCMD = 0 OUTPUT OFF CONTR_REG1 Control register 1 7 6 5 4 CMD_OUT1 CMD_OUT2 CMD_OUT3 CMD_OUT4 3 2 1 0 CMD_OUT5 CMD_OUT20 RESERVED RESERVED W Address: 0 1000 Type: Via DATA frame Reset: 0000 0000 (ALL outputs switched OFF) [7] CMD_OUT1 1: OUT1 - Power stage switched ON 0: OUT1 - Power stage switched OFF [6] CMD_OUT2 1: OUT2 - Power stage switched ON 0: OUT2 - Power stage switched OFF [5] CMD_OUT3 1: OUT3 - Power stage switched ON 0: OUT3 - Power stage switched OFF [4] CMD_OUT4 1: OUT4 - Power stage switched ON 0: OUT4 - Power stage switched OFF [3] CMD_OUT5 1: OUT5 - Power stage switched ON 0: OUT5 - Power stage switched OFF [2] CMD_OUT20 1: OUT20 - Power stage switched ON 0: OUT20 - Power stage switched OFF [1] RESERVED [0] RESERVED 134/141 DocID027721 Rev 2 L9779WD-SPI Functional description CONTR_REG2 Control register 2 7 6 5 4 3 2 1 0 CMD_OUT15 CMD_OUT14 DON'T CARE RESERVED CMD_IGN1 CMD_IGN2 CMD_IGN3 CMD_IGN4 Address: 0 1001 Type: Via DATA frame Reset: 0000 0000 (ALL outputs switched OFF) [7] CMD_OUT15 1: OUT15 - Power stage switched ON 0: OUT15 - Power stage switched OFF [6] CMD_OUT14 1: OUT14 - Power stage switched ON 0: OUT14 - Power stage switched OFF [5] DON'T CARE [4] RESERVED [3] CMD_IGN1 1: IGN1 - Power stage switched ON 0: IGN1 - Power stage switched OFF [2] CMD_IGN2 1: IGN2 - Power stage switched ON 0: IGN2 - Power stage switched OFF [1] CMD_IGN3 1: IGN3 - Power stage switched ON 0: IGN3 - Power stage switched OFF [0] CMD_IGN4 1: IGN4 - Power stage switched ON 0: IGN4 - Power stage switched OFF DocID027721 Rev 2 135/141 140 Functional description L9779WD-SPI CONTR_REG3 Control register 3 7 6 CPS_CONF = 0 CMD_OUT22 CPS_CONF = 1 CMD_OUT21 DIR ENABLE Address: 0 1010 Type: Via DATA frame Reset: 5 4 3 2 1 0 CMD_OUT16 CMD_OUT13 CMD_OUT17 CMD_OUT18 CMD_OUT7 CMD_OUT6 0000 0000 (ALL outputs switched OFF) 0 CMD_OUT6 1: OUT6 - Power stage switched ON 0: OUT6 - Power stage switched OFF 1 CMD_OUT7 1: OUT7 - Power stage switched ON 0: OUT7 - Power stage switched OFF 2 CMD_OUT18 1: OUT18 - Power stage switched ON 0: OUT18 - Power stage switched OFF 3 CMD_OUT17 1: OUT17 - Power stage switched ON 0: OUT17 - Power stage switched OFF 4 CMD_OUT13 1: OUT13 - Power stage switched ON 0: OUT13 - Power stage switched OFF 5 CMD_OUT16 1: OUT16 - Power stage switched ON 0: OUT16 - Power stage switched OFF 6 CMD_OUT21 1: OUT21 - Power stage switched ON (High side driver) 0: OUT21 - Power stage switched OFF Note: If CPS_CONF=0 (single power stages configuration) ENABLE 0: stepper motor driver disabled 1: stepper motor driver enabled Note: If CPS_CONF=1(stepper motor driving configuration) 7 CMD_OUT22 1: OUT22 - Power stage switched ON Note: If CPS_CONF=0 (single power stages configuration) 0: OUT22 - Power stage switched OFF DIR 0: forward direction 1: backward direction Note: if CPS_CONF=1(stepper motor driving configuration) Note: The meaning of some CONTR_REG3 bit depends on the configuration of bit CPS_CONF of CONF_REG1. 136/141 DocID027721 Rev 2 L9779WD-SPI Functional description CONTR_REG4 Control register 4 7 CPS_CONF = 0 CPS_CONF = 1 Address: 6 RESERVED 5 4 3 2 1 CMD_OUT28 CMD_OUT27 CMD_OUT26 CMD_OUT25 CMD_OUT24 0 CMD_OUT23 PWM 0 1011 Type: Reset: 0000 0000 (ALL outputs switched OFF) [6-7] RESERVED: NOT used [5] CMD_OUT28 1: OUT28 Power stage switched ON 0: OUT28 Power stage switched OFF [4] CMD_OUT27 1: OUT27 Power stage switched ON 0: OUT27 Power stage switched OFF [3] CMD_OUT26 1: OUT26 - Power stage switched ON (High side driver) 0: OUT26 - Power stage switched OFF [2] CMD_OUT25 1: OUT25 - Power stage switched ON (High side driver) 0: OUT25 - Power stage switched OFF [1] CMD_OUT24 1: OUT24 - Power stage switched ON 0: OUT24 - Power stage switched OFF [0] If CPS_CONF=0 (single power stages configuration) CMD_OUT23 1: OUT23 Power stage switched ON 0: OUT23 Power stage switched OFF if CPS_CONF=1(stepper motor driving configuration) PWM 1 0: no step change in the driving sequence 0 1: step change in the driving sequence (next step applied) Note: The meaning of some CONTR_REG4 bit depends on the configuration of bit CPS_CONF of CONF_REG1. DocID027721 Rev 2 137/141 140 Package information 7 L9779WD-SPI Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 HiQUAD-64 package information Figure 74. HiQUAD-64 package outline 1 F $ $ ( 1 $ E ) 0 $ % H ( %277209,(: VOXJWRSYLHZ ' %  ( ( ( *$8*(3/$1( F VOXJ ERWWRPVLGH $ 6 /  VHDWLQJSODQH  & &RSODQDULW\  (VOXJOHQJKW $ ' ' *$3*36 B)B0 138/141 DocID027721 Rev 2 L9779WD-SPI Package information Table 58. HiQUAD-64 package mechanical data Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A - - 3.15 - - 0.1240 A1 0 - 0.25 0 - 0.0098 A2 2.50 - 2.90 0.0984 - 0.1142 A3 0 - 0.10 0 - 0.0039 b 0.22 - 0.38 0.0087 - 0.0150 c 0.23 - 0.32 0.0091 - 0.0126 (2) D 17.00 - 17.40 0.6693 - 0.6850 D1 13.90 14.00 14.10 0.5472 0.5512 0.5551 D2 2.65 2.80 2.95 0.1043 0.1102 0.1161 E 17.00 - 17.40 0.6693 - 0.6850 13.90 14.00 14.10 0.5472 0.5512 0.5551 E2 2.35 - 2.65 0.0925 - 0.1043 E3 9.30 9.50 9.70 0.3661 0.3740 0.3819 E4 13.30 13.50 13.70 0.5236 0.5315 0.5394 e - 0.65 - - 0.0256 - F - 0.12 - - 0.0047 - G - 0.10 - - 0.0039 - L 0.80 - 1.10 0.0315 - 0.0433 N - - 10° - - 10° s 0° - 7° 0° - 7° (1) E1 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm (.006inc.). DocID027721 Rev 2 139/141 140 Revision history 8 L9779WD-SPI Revision history Table 59. Document revision history 140/141 Date Revision Changes 08-Apr-2015 1 Initial release. 08-May-2015 2 Updated Table 30, 31, 32 and 33 for the pins OUTA/B/C/D (High-side) the “Ron max” value is changed in 1.7 Ω. DocID027721 Rev 2 L9779WD-SPI IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027721 Rev 2 141/141 141