EVAL6472H

EVAL6472H Fully integrated stepper motor driver based on the L6472 Data brief Features ■ Voltage range from 8 V to 45 V ■ Phase current up to 3 Ar.m.s. ■ SPI with daisy chain feature ■ SW input ■ FLAG and BUSY LED indicators ■ Adjustable supply voltage compensation ■ Suitable for use in combination with STEVALPCC009V2 Description EVAL6472H The EVAL6472H demonstration board is a fully integrated microstepping motor driver. In combination with the STEVAL-PCC009V2 communication board and the dSPIN evaluation software, the board allows the user to investigate all the features of the L6472 device. In particular, the board can be used to regulate the L6472 parameters in order to fit application requirements. The EVAL6472H supports the daisy chain configuration making it suitable for the evaluation of the L6472 in the multi-motor applications. March 2012 Doc ID 022980 Rev 1 For further information contact your local STMicroelectronics sales office. 1/11 www.st.com 11 Board description 1 EVAL6472H Board description Table 1. EVAL6472H specifications Parameter Value Supply voltage (VS) 8 to 45 V Maximum output current (each phase) 3 Ar.m.s. Logic supply voltage (VREG) Externally supplied: 3.3 V Internally supplied: 3 V typical Logic interface voltage (VDD) Externally supplied: 3.3 V or 5 V Internally supplied: VREG Low level logic input voltage 0V High level logic input voltage VDD(1) Operating temperature -25 to +125 °C L6472H thermal resistance junction-to-ambient 21 °C/W typical 1. All logic inputs are 5 V tolerant. Figure 1. Jumpers and connectors location FLAG LED (Red) Power supply connector (8 V - 45 V) Application reference area JP1: VDD supply from master SPI connector BUSY LED (Amber) JP3: Daisy chain termination Slave SPI connector Master SPI connector JP2: VDD to VREG connection External switch connector (SW input) OSCIN/OSCOUT connector Motor supply voltage compensation partitioning regulation (ADCIN input) Phase A connector Phase B connector AM10289V1 2/11 Doc ID 022980 Rev 1 EVAL6472H Board description Table 2. Jumpers and connectors description Name Type M1 Power supply Motor supply voltage M2 Power output Bridge A outputs M3 Power output Bridge B outputs CN1 SPI connector Master SPI CN2 SPI connector Slave SPI CN3 NM connector OSCIN and OSCOUT pins CN4 NM connector External switch input TP1 (VS) Test point Motor supply voltage test point TP2 (VDD) Test point Logic interface supply voltage test point TP3 (VREG) Test point Logic supply voltage/L6470 internal regulator test point TP5 (GND) Test point Ground test point TP6 (GND) Test point Ground test point TP8 (STCK) Test point Step clock input test point TP9 (STBY/RES) Test point Standby/reset input test point TP10 (FLAG) Test point FLAG output test point TP11 (BUSY/SYNC) Test point BUSY/SYNC output test point Table 3. Function Master SPI connector pinout (J10) Pin number Type 1 Open drain output L6472 BUSY output 2 Open drain output L6472 FLAG output 3 Ground Ground 4 Supply EXT_VDD (can be used as external logic power supply) 5 Digital output 6 Digital input SPI serial clock signal (connected to L6472 CK input) 7 Digital input SPI master OUT slave IN signal (connected to L6472 SDI input) 8 Digital input SPI slave select signal (connected to L6472 CS input) 9 Digital input L6472 step-clock input 10 Digital input L6472 standby/reset input Description SPI master IN slave OUT signal (connected to L6472 SDO output through daisy chain termination jumper JP2) Doc ID 022980 Rev 1 3/11 Board description Table 4. 4/11 EVAL6472H Slave SPI connector pinout (J11) Pin number Type 1 Open drain output L6472 BUSY output 2 Open drain output L6472 FLAG output 3 Ground Ground 4 Supply EXT_VDD (can be used as external logic power supply) 5 Digital output 6 Digital input SPI serial clock signal (connected to L6472 CK input) 7 Digital input SPI master OUT slave IN signal (connected to L6472 SDO output) 8 Digital input SPI slave select signal (connected to L6472 CS input) 9 Digital input L6472 step-clock input 10 Digital input L6472 standby/reset input Description SPI master IN slave OUT signal (connected to pin 5 of J10) Doc ID 022980 Rev 1 1 2 VS VDD 2 VS Doc ID 022980 Rev 1 1 470 2 YELLOW DL2 1 BUSY BUSY J4 NM J7 SW NM 1 2 23 19 20 18 nCS CK SDI SDO C13 3.3nF/6V3 25 3 24 22 STCK 8 7 U1 VREG 5 4 VDD ADCIN SW OSCOUT C9A 100uF/63V R8 100 CS CK SDI SDO STCK STBY_RES FLAG BUSY_SYNC ADCIN SW OSCOUT OSCIN 2 4 6 8 10 L6472 3 C14 10nF/6V3 SW 1 VS OUT2B OUT1B OUT2A OUT1A 15 14 28 1 TP6 EXT_VDD CK nCS STBY_RESET FLAG C6 10nF/50V 220nF/16V D1 C1 SPI _ OUT J3 BAV99 2 1 3 5 7 9 29 FLAG R7 TP8 OSCIN + MISO SDO STCK BUSY 21 VDD C12 100pF/6V3 R6 39k D2 BZX585-B3V6 C11 100pF/6V3 R4 39k C9 100uF/63V + VS OPTION TP3 EXT_VDD STBY/ RES CK nCS STBY_RESET FLAG DGND FL AG VDD C8 100nF/50V 2 4 6 8 10 VREG VDD C10 100pF/6V3 R5 39k C7 100nF/50V VS SPI _ I N J2 6 17 EPAD TP7 STBY_RESET FLAG BUSY C15 100nF/50V 1 TP2 1 3 5 7 9 11 VBOOT RED DL1 C16 100nF/50V STCK MISO SDI STCK BUSY CP 470 2 1 Application reference VS 10 PGND PGND AGND R9 R3 8k2 R2 200K R1 31k6 GNDMORSV-508-2P VS 3 1 1 J1 2 1 TP1 VSB VSB VSA VSA 1 16 12 26 2 1 1 TP4 1 C2 100nF/6V3 VDD GND TP5 C4 100nF/6V3 VREG JP1 VDD VREG MISO EXT_VDD + + C3 10uF/6V3 C5 47uF/6V3 JP3 VDD SDO JP2 2 1 1 2 1A 2A J6 1B 2B MORSV-508-2P MORSV-508-2P J5 VREG Figure 2. 1 EVAL6472H Board description EVAL6472H schematic 27 13 9 AM10295V1 5/11 Board description Table 5. 6/11 EVAL6472H Bill of material Index Quantity Reference Value Package 1 1 C1 220 nF/16 V CAPC-0603 2 2 C2,C4 100 nF/6V3 CAPC-0603 3 1 C3 10 µF/6V3 CAPC-3216 4 1 C5 47 µF/6V3 CAPC-3216 5 1 C6 10 nF/50 V CAPC-0603 6 4 C7, C8, C15, C16 100 nF/50 V CAPC-0603 7 1 C9A 100 µF/6V3 (option) CAPE-R10HXX-P5 8 1 C9 100 µF/6V3 CAPES-R10HXX 9 3 C10, C11, C12 100 pF/6V3 CAPC-0603 10 1 C13 3.3 nF/6V3 CAPC-0603 11 1 C14 10 nF/6V3 CAPC-0603 12 1 DL1 LED diode (red) LEDC-0805 13 1 DL2 LED diode (amber) LEDC-0805 14 1 D1 BAV99 SOT23 15 1 D2 BZX585-B3V6 SOD323 16 1 JP1 Jumper - open JP2SO 17 2 JP2, JP3 Jumper - closed JP2SO 18 3 J1, J5, J6 Screw connector 2 poles MORSV-508-2P 19 2 J2,J3 Pol. IDC male header vertical 10 poles CON-FLAT-5X2-180M 20 2 J4, J7 NM STRIP254P-M-2 21 1 R1 31.6 kΩ RESC-0603 22 1 R2 200 kΩ TRIMM-100X50X110-64W 23 1 R3 8.2 kΩ RESC-0603 24 3 R4, R5, R6 39 kΩ RESC-0603 25 2 R7, R9 470 Ω RESC-0603 26 1 R8 100 Ω RESC-0603 27 7 TP1, TP2, TP3, TP4, TP5, TP7, TP8 TPTH-ring-1 mm red TH 28 1 TP6 TPTH-ring-1 mm black TH 29 1 U1 L6472 HTSSOP28 Doc ID 022980 Rev 1 EVAL6472H Board description Figure 3. EVAL6472H - silkscreen AM10290V2 Figure 4. EVAL6472H - layout (top layer) AM10290V1 Doc ID 022980 Rev 1 7/11 Board description Figure 5. EVAL6472H EVAL6472H - layout (inner layer2) AM10291V1 Figure 6. EVAL6472H - layout (inner layer3) AM10292V1 8/11 Doc ID 022980 Rev 1 EVAL6472H Board description Figure 7. EVAL6472H - layout (bottom layer3) AM10293V1 Thermal data Figure 8. Thermal impedance graph 25 20 Zth (°C/W) 1.1 15 10 5 0 1 100 10 1000 Time (sec) AM10294V1 Doc ID 022980 Rev 1 9/11 Revision history 2 EVAL6472H Revision history Table 6. 10/11 Document revision history Date Revision 21-Mar-2012 1 Changes Initial release. Doc ID 022980 Rev 1 EVAL6472H Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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