EVAL6598-100W

L6598 High voltage resonant controller Datasheet - production data  Sense op amp for closed loop control or protection features  High accuracy current controlled oscillator  Integrated bootstrap diode  Clamping on Vs  Available in DIP16 and SO16 packages 621 ',3 Description The L6598 device is manufactured with the BCD™ offline technology, able to ensure voltage ratings up to 600 V, making it perfectly suited for AC/DC adapters and wherever a resonant topology can be beneficial. The device is intended to drive two power MOSFETs, in the classical half bridge topology. A dedicated timing section allows the designer to set soft-start time, soft-start and minimum frequency. An error amplifier, together with the two enable inputs, are made available. In addition, the integrated bootstrap diode and the Zener clamping on low voltage supply, reduces to a minimum the external parts needed in the applications. Features  High voltage rail up to 600 V  dV/dt immunity ±50 V/ns in full temperature range  Driver current capability: 250 mA source 450 mA sink  Switching times 80/40 ns rise/fall with 1 nF load  CMOS shutdown input  Undervoltage lockout  Soft-start frequency shifting timing Figure 1. Block diagram 96 23287 23,1 23,1  23$03 +9     %227675$3 '5,9(5 89 '(7(&7,21  +9* '5,9(5  9%227  +9*  287 ,IPLQ 95() '($' 7,0( '5,9,1* /2*,& /(9(/ 6+,)7(5  ,IVWDUW 95()    &21752/ /2*,&  /9*  *1' 9WKH   5IVWDUW /2$' 9V  /9*'5,9(5 5IPLQ &%227 (1 9WKH  (1 ,VV  9&2 &I  &VV $0Y November 2013 This is information on a product in full production. DocID6554 Rev 8 1/23 www.st.com Contents L6598 Contents 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Block diagram description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 High/low side driving section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Timing and oscillator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 Op amp section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/23 DocID6554 Rev 8 L6598 1 Maximum ratings Maximum ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit 25 mA 14.6 V -1 to VBOOT -18 V -1 to VBOOT V 618 V ±50 V/ns ±50 V/ns Supply current at Vcl(1) IS VLVG Low side output VOUT High side reference VHVG High side output VBOOT Floating supply voltage dVBOOT/dt VBOOT pin slew rate (repetitive) dVOUT/dt OUT pin slew rate (repetitive) Vir Forced input voltage (pins Rfmin, Rfstart) -0.3 to 5 V Vic Forced input voltage (pins Css, Cf) -0.3 to 5 V VEN1, VEN2 Enable input voltage -0.3 to 5 V IEN1, IEN2 Enable input current ±3 mA -0.3 to 5 V Vopc Sense op amp common mode range Vopd Sense op amp differential mode range -5 to 5 V Vopo Sense op amp output voltage (forced) 4.6 V Tstg Storage temperature -40 to +150 °C Tj Junction temperature -40 to +150 °C Tamb Ambient temperature -40 to +125 °C 1. The device is provided of an internal clamping Zener between GND and the Vs pin, It must not be supplied by a low impedance voltage source. Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 (human body model). Table 2. Thermal data Symbol RthJA Parameter Thermal resistance junction to ambient SO16N DIP16 Unit 120 80 °C/W Table 3. Recommended operating conditions Symbol VS Vout Parameter Supply voltage Value Unit 10 to Vcl V (1) High side reference -1 to Vboot - Vcl V (1) Floating supply rail 500 V Maximum switching frequency 400 kHz Vboot fmax 1. If the condition Vboot - Vout < 18 is guaranteed, Vout can range from -3 to 580 V. DocID6554 Rev 8 3/23 23 Electrical characteristics 2 L6598 Electrical characteristics VS = 12 V; VBOOT - VOUT = 12 V; TA = 25 °C Table 4. Electrical characteristics Symbol Pin Parameter Test condition Min. Typ. Max. Unit Supply voltage Vsuvp VS turn on threshold 10 10.7 11.4 V Vsuvn VS turn off threshold 7.3 8 8.7 V Vsuvh Supply voltage under voltage hysteresis Vcl 12 2.7 Supply voltage clamping 14.6 Isu Start up current VS < Vsuvn Iq Quiescent current, fout = 60 kHz, no load VS > Vsuvp 15.6 2 V 16.6 V 250 µA 3 mA High voltage section Ibootleak 16 BOOT pin leakage current VBOOT = 580 V 5 µA Ioutleak 14 OUT pin leakage current VOUT = 562 V 5 µA RDSon 16 Bootstrap driver onresistance 300  100 150 High/low side drivers High side driver source current VHVG - VOUT = 0 170 250 mA Ihvgsi High side driver sink current VHVG - VBOOT = 0 300 450 mA Ilvgso Low side driver source current VLVG - GND = 0 170 250 mA Low side driver sink current VLVG - VS = 0 300 450 mA Ihvgso 15 11 Ilvgsi trise Low/high side output rise 15,11 time tfall Cload = 1 nF 80 120 ns Cload = 1 nF 40 80 ns 48 50 52 % Oscillator DC Output duty cycle fmin Minimum output oscillation frequency Cf = 470 pF; Rfmin = 50 k 58.2 60 61.8 kHz Soft-start output oscillation frequency Cf = 470 pF; Rfmin = 50 k; Rfstart = 47k 114 120 126 kHz fstart 4/23 14 DocID6554 Rev 8 L6598 Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Pin Vref 2, 4 td IVref Parameter Test condition Min. Typ. Max. Unit Voltage to current converters threshold 1.9 2 2.1 V 14 Deadtime between low and high side conduction 0.2 0.27 0.35 µs 2, 4 Reference current 120 A Timing section kss 1 Soft-start timing constant Css = 330 nF 0.115 0.15 0.185 s/µF 0.1 µA Sense op amp lIB Vio 6, 7 Rout Iout- 5 Iout+ Vic 6,7 GBW Gdc Input bias current Input offset voltage -10 10 mV Output resistance 200 300 ? Source output current Vout = 4.5 V 1 mA Sink output current Vout = 0.2 V 1 mA Op amp input common mode range -0.2 Sense op amp gain band width product(1) 0.5 1 MHz DC open loop gain 60 80 dB 3 V Comparators Vthe1 8 Enabling comparator threshold 0.56 0.6 0.64 V Vthe2 9 Enabling comparator threshold 1.05 1.2 1.35 V tpulse 8,9 Minimum pulse length 200 ns 1. Guaranteed by design. DocID6554 Rev 8 5/23 23 Pin connections 3 L6598 Pin connections Figure 2. Pin connections &VV   9%227 5IVWDUW   +9* &I   287 5IPLQ   1& 23287   96 23,1   /9* 23,1   *1' (1   (1 $0Y Table 5. Pin description Pin no. Name 1 CSS 2 Rfstart Soft-start frequency setting - low impedance voltage source -see also Cf 3 6/23 Function Cf Soft-start timing capacitor Oscillator frequency setting - see also Rfmin, Rfstart 4 Rfmin Minimum oscillation frequency setting - low impedance voltage source - see also Cf 5 OPout Sense op amp output - low impedance 6 OPon- Sense op amp inverting input -high impedance 7 OPon+ Sense op amp non inverting input - high impedance 8 EN1 Half bridge latched enable 9 EN2 Half bridge unlatched enable 10 GND Ground 11 LVG 12 Vs 13 N.C. Not connected 14 OUT High side driver reference 15 HVG High side driver output 16 Vboot Bootstrapped supply voltage Low side driver output Supply voltage with internal Zener clamp DocID6554 Rev 8 L6598 4 Timing diagrams Timing diagrams Figure 3. EN2 timing diagram 96 I287 IVWDUW IPLQ (1 9&VV 766 766 $0Y Figure 4. EN1 timing diagram +9* /9* (1 (1 $0Y DocID6554 Rev 8 7/23 23 Timing diagrams L6598 Figure 5. Oscillator/output timing diagram &I +9* /9* $0Y 8/23 DocID6554 Rev 8 L6598 Block diagram description 5 Block diagram description 5.1 High/low side driving section A high and low side driving section provide the proper driving to the external power MOS or IGBT. A high sink/source driving current (450/250 mA typ.) ensure fast switching times also when size for power MOS are used. The internal logic ensures a minimum deadtime to avoid cross conduction of the power devices. 5.2 Timing and oscillator section The device is provided of a soft-start function. It consists in a period of time, TSS, in which the switching frequency shifts from fstart to fmin. This feature is explained in the following description (refer to Figure 6 and Figure 7). Figure 6. Soft-start and frequency shifting block ,VV ,IVWDUW ,IPLQ JP ,RVF 26& &VV $0Y During the soft-start time the current ISS charges the capacitor CSS, generating a voltage ramp which is delivered to a transconductance amplifier, as shown in Figure 6. Thus this voltage signal is converted in a growing current which is subtracted to Ifstart. Therefore the current which drives the oscillator to set the frequency during the soft-start is equal to: Equation 1 g m I ss I osc = I fmin +  I fstart – g m V Css  t   = I fmin +  I fstart – -------------- C ss Equation 2 where V REF V REF I fmin = -------------- I fstart = ---------------- ,V REF = 2V R fmin R fstart DocID6554 Rev 8 9/23 23 Block diagram description L6598 At the startup (t = 0) the oscillator frequency is set by: Equation 3 1 1 I OSC  0  = I fmin + I fstart = V REF  -------------- + ---------------- R fmin R fstart At the end of the soft-start (t = TSS) the second term of eq.1 decreases to zero and the switching frequency is set only by Imin (i.e. Rfmin): Equation 4 V REF I OSC  T SS  = I fmin = -------------R fmin Since the second term of Equation 1 is equal to zero, we have: Equation 5 g m I ss C ss I fstart I fstart – --------------T SS = 0  T SS = -----------------------C ss g m I ss Note that there is not a fixed threshold of the voltage across CSS in which the soft-start finishes (i.e. the end of the frequency shifting), and TSS depends on CSS, Ifstart, gm, and ISS (Equation 5). Making TSS independent of Ifstart, the ISS current has been designed to be a fraction of Ifstart, so: Equation 6 I fstart C ss I fstart C ss I SS = --------------  T SS = --------------------------  T SS = -----------  T SS – k SS C SS K g m I fstart K gm K In this way the soft-start time depends only on the capacitor CSS. The typical value of the kSS constant (Soft-start timing constant) is 0.15 s/F. The current Iosc is fed to the oscillator as shown in Figure 7. It is twice mirrored (x4 and x8) generating the triangular wave on the oscillator capacitor Cf. Referring to the internal structure of the oscillator (Figure 7), a good relationship to compute an approximate value of the oscillator frequency in normal operation is: Equation 7 1.41 f min = -------------------R fmin C f 10/23 DocID6554 Rev 8 L6598 Block diagram description The degree of approximation depends on the frequency value, but it remains very good in the range from 30 kHz to 100 kHz (Figure 8 to Figure 12). Figure 7. Oscillator block ,RVF 9WK ;  6 &I 5 9WK  ; $0Y DocID6554 Rev 8 11/23 23 Block diagram description L6598 Figure 8. Typ. fmin vs. Rfmin at Cf = 470 pF Figure 9. Typ. (fstart-fmin) vs. Rfstar at Cf = 470 pF Figure 10. Typ. (fstart-fmin) vs. Rfstar at Cf = 470 pF Figure 11. fmin at different Rf vs Cf 12/23 DocID6554 Rev 8 L6598 Block diagram description Figure 12. Typ. (fstart-fmin) vs. Rfstar at Cf = 470 pF 5.3 Bootstrap section The supply of the high voltage section is obtained by means of a bootstrap circuitry. This solution normally requires a high voltage fast recovery diode for charging the bootstrap capacitor (Figure 13 - part a). In the device a patented integrated structure replaces this external diode. It is released by means of a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in Figure 13 - part b. Figure 13. Bootstrap driver To drive the synchronized DMOS it is necessary a voltage higher than the supply voltage Vs. This voltage is obtained by means of an internal charge pump (Figure 13 - part b). The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. The introduction of the diode prevents any current can flow from the Vboot pin to the VS one in case that the supply is quickly turned off when the internal capacitor of the pump is not fully discharged. The bootstrap driver introduces a voltage drop during the recharging of the capacitor Cboot (i.e. when the low side driver is on), which increases with the frequency and with the size of the external power MOS. It is the sum of the drop across the RDSON and of the diode DocID6554 Rev 8 13/23 23 Block diagram description L6598 threshold voltage. At low frequency this drop is very small and can be neglected. Anyway increasing the frequency it must be taken in to account. In fact the drop, reducing the amplitude of the driving signal, can significantly increase the RDSON of the external power MOS (and so the dissipation). To be considered that in resonant power supplies the current which flows in the power MOS decreases increasing the switching frequency and generally the increases of RDSON is not a problem because power dissipation is negligible. Equation 8 is useful to compute the drop on the bootstrap driver: Equation 8 Qg V drop = I ch arg e R dson + V diode  V drop = -------------------R dson + V diode T ch arg e where Qg is the gate charge of the external power MOS, Rdson is the on-resistance of the bootstrap DMOS, and Tcharge is the time in which the bootstrap driver remains on (about the semi-period of the switching frequency minus the deadtime). The typical resistance value of the bootstrap DMOS is 150 . For example using a power MOS with a total gate charge of 30 nC the drop on the bootstrap driver is about 3 V, at a switching frequency of 200 kHz. In fact: Equation 9 30nC V drop = ------------------150 + 0.6V  2.6V 2.23s To summaries, if a significant drop on the bootstrap driver (at high switching frequency when large power MOS are used) represents a problem, an external diode can be used, avoiding the drop on the RDSON of the DMOS. 5.4 Op amp section The integrated op amp is designed to offer low output impedance, wide band, high input impedance and wide common mode range. It can be readily used to implement protection features or a closed loop control. For this purpose the op amp output can be properly connected to Rfmin pin to adjust the oscillation frequency. 14/23 DocID6554 Rev 8 L6598 5.5 Block diagram description Comparators Two CMOS comparators are available to perform protection schemes. Short pulses ( 200 ns) on comparators input are recognized. The EN1 input (active high), has a threshold of 0.6 V (typical value) forces the device in a latched shut down state (e.g. LVG low, HVG low, oscillator stopped), as in the under voltage conditions. Normal operating conditions are resumed after a power-off power-on sequence. The EN2 input (active high), with a threshold of 1.2 V (typical value) restarts a soft-start sequence (see timing diagrams in Figure 3, Figure 4, and Figure 5). In addition the EN2 comparator, when activated, removes a latched shutdown caused by EN1. Figure 14. Switching time waveform definitions Figure 15. Deadtime and duty cycle waveform definition DocID6554 Rev 8 15/23 23 Block diagram description 16/23 L6598 Figure 16. Typ. fmin vs. temperature Figure 17. Startup current vs. temperature Figure 18. Typ. fstart vs. temperature Figure 19. Quiescent current vs. temperature DocID6554 Rev 8 L6598 Block diagram description Figure 20. Vs thresholds and clamp vs. temp. Figure 21. HVG source and sink current vs. temperature Figure 22. LVG source and sink current vs. temperature Figure 23. Soft-start timing constant vs. temperature DocID6554 Rev 8 17/23 23 Block diagram description L6598 Figure 24. Wide range AC/DC adapter application 18/23 DocID6554 Rev 8 L6598 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 25. Plastic DIP16 (0.25) package outline 3& Table 6. Plastic DIP16 (0.25) package mechanical data Dimensions Symbol mm Min. a1 0.51 B 0.77 Typ inch Max. Min. Typ. Max. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 DocID6554 Rev 8 0.050 19/23 23 Package information L6598 Figure 26. SO16 package outline ' Table 7. SO16 package mechanical data Dimensions Symbol mm Min. Typ A a inch Max. Typ. 1.75 1 0.1 0.25 a2 Max. 0.068 0.004 0.010 1.64 0.063 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.62 S 20/23 Min. 8° (max.) DocID6554 Rev 8 0.024 L6598 7 Ordering codes Ordering codes Table 8. Ordering information Order codes Package Packing L6598 DIP16 Tube L6598D L6598D013TR SO16N DocID6554 Rev 8 Tube Tape and reel 21/23 23 Revision history 8 L6598 Revision history Table 9. Document revision history Date Revision Changes 21-Jun-2004 5 Changed the impagination following the new release of “corporate technical publication design guide”. Done a few of corrections in the text. 09-Sep-2004 6 Added ordering number for the tape and reel version, updated Table 4 on page 4 02-Oct-2009 7 Updated Table 4 on page 4 8 Added cross-reference in Section 5. Updated Section 6: Package information (reformatted - added title of Figure 25 and Table 6, Figure 26 and Table 7 and reversed order of figures and tables, minor modifications). Updated Table 8 (replaced L6598D016TR device by L6598D013TR device). Minor corrections throughout document. 18-Nov-2013 22/23 DocID6554 Rev 8 L6598 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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