A5970AD
Up to 1 A step down-switching regulator for automotive applications
Datasheet - production data
Application
Dedicated to automotive applications
Description
SO-8
Features
Qualified following the AEC-Q100
requirements (see PPAP for more details)
1 A DC output current
Operating input voltage from 4 V to 36 V
3.3 V / (± 2%) reference voltage
Output voltage adjustable from 1.235 V to VIN
The A5970AD is a step-down monolithic power
switching regulator with a minimum switch current
limit of 1.35 A so it is able to deliver up to 1 A DC
current to the load depending on the application
conditions. The output voltage can be set from
1.235 V to VIN.
The device uses an internal P-channel DMOS
transistor (with a typical RDS(on) of 250 m) as
switching element to minimize the size of the
external components.
An internal oscillator fixes the switching frequency
at 500 kHz. Having a minimum input voltage of
4 V only it fits the automotive applications
requiring the device operation even in cold crank
conditions. Pulse by pulse current limit with the
internal frequency modulation offers an effective
constant current short-circuit protection.
Low dropout operation: 100% duty cycle
500 kHz Internally fixed frequency
Voltage feed-forward
Zero load current operation
Internal current limiting
Inhibit for zero current consumption
Synchronization
Protection against feedback disconnection
Thermal shutdown
Figure 1. Application schematic
A5970AD
March 2014
This is information on a product in full production.
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www.st.com
Contents
A5970AD
Contents
1
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Datasheet parameters over the temperature range . . . . . . . . . . . . . . . . 8
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
7
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5.1
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2
Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4
Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.5
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6
PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.7
Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2
Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.3
Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2
LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.3
PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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8
Contents
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1
Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.3
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.4
Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.5
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.6
Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.7
Negative buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.8
Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.9
Compensation network with MLCC at the output . . . . . . . . . . . . . . . . . . . 34
8.10
External SOFT_START network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Pin settings
A5970AD
1
Pin settings
1.1
Pin connection
Figure 2. Pin connection (top view)
1.2
Pin description
Table 1. Pin description
4/42
No.
Pin
Description
1
OUT
2
SYNCH
3
INH
4
COMP
5
FB
6
VREF
3.3 V VREF. No cap is requested for stability.
7
GND
Ground.
8
VCC
Unregulated DC input voltage.
Regulator output.
Master/slave synchronization.
A logical signal (active high) disables the device. If INH not used the pin
must be grounded. When it is open an internal pull-up disables the
device.
E/A output for frequency compensation.
Feedback input. Connecting directly to this pin results in an output
voltage of 1.23 V. An external resistive divider is required for higher
output voltages.
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A5970AD
Electrical data
2
Electrical data
2.1
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
Value
Unit
40
V
V
V
V8
Input voltage
V1
OUT pin DC voltage
OUT pin peak voltage at t = 0.1 s
-1 to 40
-5 to 40
I1
Maximum output current
Int. limit.
V4, V5
Analog pins
4
V
-0.3 to VCC
V
-0.3 to 4
V
0.6
W
Operating junction temperature range
-40 to 150
°C
Storage temperature range
-55 to 150
°C
Value
Unit
120(1)
°C/W
V3
INH
V2
SYNCH
PTOT
TJ
TSTG
2.2
Parameter
Power dissipation at TA 70 °C
Thermal data
Table 3. Thermal data
Symbol
RthJA
Parameter
Maximum thermal resistance junction ambient
1. Package mounted on evaluation board.
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Electrical characteristics
3
A5970AD
Electrical characteristics
TJ = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified.
Table 4. Electrical characteristics
Symbol
VCC
RDS(on)
IL
fSW
Parameter
Test condition
Operating input voltage range
Min.
4
MOSFET on resistance
Maximum limiting current(1)
Typ.
0.250
VCC = 5 V
1.35
1.8
VCC = 5 V, TJ = 25 °C
1.5
1.8
430
500
Switching frequency
Duty cycle
0
Max.
Unit
36
V
0.5
A
570
kHz
100
%
1.272
V
Dynamic characteristics (see test circuit)
V5
Voltage feedback
4.4 V < VCC < 36 V
h
Efficiency
V0 = 5 V, VCC = 12 V
1.198
1.235
90
%
DC characteristics
Iqop
Iq
Iqst-by
Total operating quiescent current
5
Quiescent current
Duty cycle = 0; VFB = 1.5 V
Total standby quiescent current
Vinh > 2.2 V
50
7
mA
2.7
mA
100
A
0.8
V
Inhibit
INH threshold voltage
Device ON
Device OFF
2.2
V
3.5
V
Error amplifier
VOH
High level output voltage
VFB = 1 V
VOL
Low level output voltage
VFB = 1.5 V
Source output current
VCOMP = 1.9 V; VFB = 1 V
Io sink
Sink output current
VCOMP = 1.9 V; VFB = 1.5 V
Ib
Source bias current
Io source
gm
0.4
190
300
A
1
1.5
mA
2.5
DC open loop gain
RL =
Transconductance
ICOMP = -0.1 mA to 0.1 mA;
VCOMP = 1.9 V
V
50
4
A
57
dB
2.3
mS
Synch function
6/42
High input voltage
VCC = 4.4 to 36 V
Low input voltage
VCC = 4.4 to 36 V
Slave synch current(2)
Vsynch = 0.74 V
Vsynch = 2.33 V
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2.5
0.11
0.21
VREF
V
0.74
V
0.25
0.45
mA
A5970AD
Electrical characteristics
Table 4. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Master output amplitude
Isource = 3 mA
2.75
3
V
Output pulse width
no load, Vsynch = 1.65 V
0.20
0.35
s
Reference voltage
IREF = 0 to 5 mA
VCC = 4.4 V to 36 V
3.2
3.3
3.399
V
Line regulation
IREF = 0 mA
VCC = 4.4 V to 36 V
5
10
mV
Load regulation
IREF = 0 mA
8
15
mV
18
35
mA
Reference section
Short-circuit current
5
1. With TJ = 85 °C, Ilim_min = 1.5 A, assured by design, characterization and statistical correlation.
2. Guaranteed by design.
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Datasheet parameters over the temperature range
4
A5970AD
Datasheet parameters over the temperature range
The 100% of the population in the production flow is tested at three different ambient
temperatures (-40 C, +25 C, +125 C) to guarantee the datasheet parameters inside the
junction temperature range (-40 C, +125 C).
The device operation is so guaranteed when the junction temperature is inside the (-40 C,
+150 C) temperature range. The designer can estimate the silicon temperature increase
respect to the ambient temperature evaluating the internal power losses generated during
the device operation (please refer to the Section 2.2).
However the embedded thermal protection disables the switching activity to protect the
device in case the junction temperature reaches the TSHTDWN (+150 C ± 10 C)
temperature.
All the datasheet parameters can be guaranteed to a maximum junction temperature of
+125 C to avoid triggering the thermal shutdown protection during the testing phase
because of self-heating.
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5
Functional description
Functional description
The main internal blocks are shown in the device block diagram in Figure 3. They are:
A voltage regulator supplying the internal circuitry. From this regulator, a 3.3 V
reference voltage is externally available.
A voltage monitor circuit which checks the input and the internal voltages.
A fully integrated sawtooth oscillator with a frequency of 500 kHz 15%, including also
the voltage feed forward function and an input/output synchronization pin.
Two embedded current limitation circuits which control the current that flows through
the power switch. The pulse-by-pulse current limit forces the power switch OFF cycle
by cycle if the current reaches an internal threshold, while the frequency shifter reduces
the switching frequency in order to significantly reduce the duty cycle.
A transconductance error amplifier.
A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to
drive the internal power.
A high side driver for the internal P-MOS switch.
An inhibit block for standby operation.
A circuit to implement the thermal protection function.
Figure 3. Block diagram
5.1
Power supply and voltage reference
The internal regulator circuit (shown in Figure 4) consists of a start-up circuit, an internal
voltage pre-regulator, the bandgap voltage reference and the bias block that provides
current to all the blocks. The starter supplies the start-up currents to the entire device when
the input voltage goes high and the device is enabled (inhibit pin connected to ground). The
pre-regulator block supplies the bandgap cell with a pre-regulated voltage VREG that has
a very low supply voltage noise sensitivity.
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Functional description
5.2
A5970AD
Voltages monitor
An internal block continuously senses the Vcc, Vref and Vbg. If the voltages go higher than
their thresholds, the regulator begins operating. There is also a hysteresis on the VCC
(UVLO).
Figure 4. Internal circuit
5.3
Oscillator and synchronization
Figure 5 shows the block diagram of the oscillator circuit.
The clock generator provides the switching frequency of the device, which is internally fixed
at 500 kHz. The frequency shifter block acts to reduce the switching frequency in case of
strong overcurrent or short-circuit. The clock signal is then used in the internal logic circuitry
and is the input of the ramp generator and synchronizer blocks.
The ramp generator circuit provides the sawtooth signal, used for PWM control and the
internal voltage feed-forward, while the synchronizer circuit generates the synchronization
signal. The device also has a synchronization pin which can work both as master and slave.
Beating frequency noise is an issue when more than one voltage rail is on the same board.
A simple way to avoid this issue is to operate all the regulators at the same switching
frequency.
The synchronization feature of a set of the A5970AD is simply get connecting together their
SYNCH pin. The device with highest switching frequency will be the MASTER and it
provides the synchronization signal to the others. Therefore the SYNCH is a I/O pin to
deliver or recognize a frequency signal. The synchronization circuitry is powered by the
internal reference (VREF) so a small filtering capacitor (100 nF) connected between VREF
pin and the signal ground of the master device is suggested for its proper operation.
However when a set of synchronized devices populates a board it is not possible to know in
advance the one working as master, so the filtering capacitor have to be designed for whole
set of devices.
When one or more devices are synchronized to an external signal, its amplitude have to be
in comply with specifications given in the Table 4 on page 6. The frequency of the
synchronization signal must be, at a minimum, higher than the maximum guaranteed natural
switching frequency of the device (575 kHz, see Table 4) while the duty cycle of the
synchronization signal can vary from approximately 10% to 90%. The small capacitor under
VREF pin is required for this operation.
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A5970AD
Functional description
Figure 5. Oscillator circuit block diagram
Figure 6. Synchronization example
SYNCH
OUT
A5970AD
A5973D
FB
OUT
SYNCH
A5970AD
A5973D
FB
COMP
COMP
SS/INH
SS/INH
GND
OUT
SYNCH
A5970AD
A5973D
GND
OUT
SYNCH
A5970AD
A5973D
FB
FB
COMP
SS/INH
5.4
COMP
SS/INH
GND
GND
Current protection
The A5970AD device features two types of current limit protection: pulse-by-pulse and
frequency foldback.
The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in
Figure 7. The output power PDMOS transistor is split into two parallel PDMOS transistors.
The smallest one includes a resistor in series, RSENSE. The current is sensed through
RSENSE and if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is
switched off until the next falling edge of the internal clock pulse. Due to this reduction of the
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Functional description
A5970AD
ON time, the output voltage decreases. Since the minimum switch ON time necessary to
sense the current in order to avoid a false overcurrent signal is too short to obtain
a sufficiently low duty cycle at 500 kHz (see Section 8.4 on page 26), the output current in
strong overcurrent or short-circuit conditions could be not properly limited. For this reason
the switching frequency is also reduced, thus keeping the inductor current under its
maximum threshold. The frequency shifter (Figure 5) functions based on the feedback
voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching
frequency decreases also.
Figure 7. Current limitation circuitry
5.5
Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage
reference (1.235 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage. The output (COMP) is connected to the external
compensation network. The uncompensated error amplifier has the following
characteristics:
Table 5. Uncompensated error amplifier characteristics
Description
Values
Transconductance
2300 µS
Low frequency gain
65 dB
Minimum sink/source voltage
1500 µA/300 µA
Output voltage swing
0.4 V/3.65 V
Input bias current
2.5 µA
The error amplifier output is compared to the oscillator sawtooth to perform PWM control.
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5.6
Functional description
PWM comparator and power stage
This block compares the oscillator sawtooth and the error amplifier output signals to
generate the PWM signal for the driving stage.
The power stage is a highly critical block, as it functions to guarantee a correct turn ON and
turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise
time of the current at turn ON, is a very critical parameter. At a first approach, it appears that
the faster the rise time, the lower the turn ON losses.
However, there is a limit introduced by the recovery time of the recirculation diode.
In fact, when the current of the power element is equal to the inductor current, the diode
turns OFF and the drain of the power is able to go high. But during its recovery time, the
diode can be considered a high value capacitor and this produces a very high peak current,
responsible for numerous problems:
Spikes on the device supply voltage that cause oscillations (and thus noise) due to the
board parasites.
Turn ON overcurrent leads to a decrease in the efficiency and system reliability.
Major EMI problems.
Shorter freewheeling diode life.
The fall time of the current during turn OFF is also critical, as it produces voltage spikes (due
to the parasites elements of the board) that increase the voltage drop across the PDMOS.
In order to minimize these problems, a new driving circuit topology has been used and the
block diagram is shown in Figure 8. The basic idea is to change the current levels used to
turn the power switch ON and OFF, based on the PDMOS and the gate clamp status.
This circuitry allows the power switch to be turned OFF and ON quickly and addresses the
freewheeling diode recovery time problem. The gate clamp is necessary to ensure that VGS
of the internal switch does not go higher than VGSmax. The ON/OFF Control block protects
against any cross conduction between the supply line and ground.
Figure 8. Driving circuitry
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Functional description
5.7
A5970AD
Inhibit function
The inhibit feature is used to put the device in standby mode. With the INH pin higher than
2.2 V the device is disabled and the power consumption is reduced to less than 100 µA.
With the INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an
internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also VCC compatible.
5.8
Thermal shutdown
The shutdown block generates a signal that turns OFF the power stage if the temperature of
the chip goes higher than a fixed internal threshold (150 ± 10 °C). The sensing element of
the chip is very close to the PDMOS area, ensuring fast and accurate temperature
detection. A hysteresis of approximately 20 °C keeps the device from turning ON and OFF
continuously.
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Additional features and protection
6
Additional features and protection
6.1
Feedback disconnection
If the feedback is disconnected, the duty cycle increases towards the maximum allowed
value, bringing the output voltage close to the input supply. This condition could destroy the
load.
To avoid this hazardous condition, the device is turned OFF if the feedback pin is left
floating.
6.2
Output overvoltage protection
Overvoltage protection, or OVP, is achieved by using an internal comparator connected to
the feedback, which turns OFF the power stage when the OVP threshold is reached. This
threshold is typically 30% higher than the feedback voltage.
When a voltage divider is required to adjust the output voltage (Figure 15 on page 27), the
OVP intervention will be set at:
Equation 1
R1 + R2
V OVP = 1.3 -------------------- V FB
R2
Where R1 is the resistor connected between the output voltage and the feedback pin, and
R2 is between the feedback pin and ground.
6.3
Zero load
Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so
the device works properly even with no load at the output. In this case it works in burst
mode, with a random burst repetition rate.
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Closing the loop
7
A5970AD
Closing the loop
Figure 9. Block diagram of the loop
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7.1
Closing the loop
Error amplifier and compensation network
The output L-C filter of a step-down converter contributes with 180 degrees phase shift in
the control loop. For this reason a compensation network between the COMP pin and
GROUND is added. The simplest compensation network together with the equivalent circuit
of the error amplifier are shown in Figure 10. RC and CC introduce a pole and a zero in the
open loop gain. CP does not significantly affect system stability but it is useful to reduce the
noise of the COMP pin.
The transfer function of the error amplifier and its compensation network is:
Equation 2
A V0 1 + s R c C c
A 0 s = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
s R0 C0 + Cp Rc Cc + s R0 Cc + R0 C0 + Cp + Rc Cc + 1
Where Avo = Gm · Ro
Figure 10. Error amplifier equivalent circuit and compensation network
The poles of this transfer function are (if Cc >> C0+CP):
Equation 3
1
F P1 = ------------------------------------2 R0 Cc
Equation 4
1
F P2 = -------------------------------------------------------2 Rc C0 + Cp
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Closing the loop
A5970AD
whereas the zero is defined as:
Equation 5
1
F Z1 = ------------------------------------2 Rc Cc
FP1 is the low frequency which sets the bandwidth, while the zero FZ1 is usually put near to
the frequency of the double pole of the L-C filter (see below). FP2 is usually at a very high
frequency.
7.2
LC filter
The transfer function of the L-C filter is given by:
Equation 6
R LOAD 1 + ESR C OUT s
A LC s = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
s L C OUT ESR + R LOAD + s ESR C OUT R LOAD + L + R LOAD
where RLOAD is defined as the ratio between VOUT and IOUT.
If RLOAD >> ESR, the previous expression of ALC can be simplified and becomes:
Equation 7
1 + ESR C OUT s
A LC s = --------------------------------------------------------------------------------------------2
L C OUT s + ESR C OUT s + 1
The zero of this transfer function is given by:
Equation 8
1
F O = ---------------------------------------------------2 ESR C OUT
F0 is the zero introduced by the ESR of the output capacitor and it is very important to
increase the phase margin of the loop.
The poles of the transfer function can be calculated through the following expression:
Equation 9
2
– ESR C OUT ESR C OUT – 4 L C OUT
F PLC1 2 = -----------------------------------------------------------------------------------------------------------------------------------------2 L C OUT
In the denominator of ALC the typical second order system equation can be recognized:
Equation 10
2
s + 2 n s +
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n
A5970AD
Closing the loop
If the damping coefficient is very close to zero, the roots of the equation become a double
root whose value is n.
Similarly for ALC the poles can usually be defined as a double pole whose value is:
Equation 11
1
F PLC = ---------------------------------------------2 L C OUT
7.3
PWM comparator
The PWM gain is given by the following formula:
Equation 12
V cc
G PWM s = ------------------------------------------------------------ V OSCMAX – V OSCMIN
where VOSCMAX is the maximum value of a sawtooth waveform and VOSCMIN is the
minimum value. A voltage feed forward is implemented to ensure a constant GPWM. This is
obtained by generating a sawtooth waveform directly proportional to the input voltage VCC.
Equation 13
V OSCMAX – V OSCMIN = K V CC
Where K is equal to 0.038. Therefore the PWM gain is also equal to:
Equation 14
1
G PWM s = ---- = const
K
This means that even if the input voltage changes, the error amplifier does not change its
value to keep the loop in regulation, thus ensuring a better line regulation and line transient
response.
In summary, the open loop gain can be expressed as:
Equation 15
R2
G s = G PWM s -------------------- A O s A LC s
R1 + R2
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Closing the loop
A5970AD
Example 1
Considering RC = 1.8 k, CC = 68nF and CP = 330 pF, the poles and zeroes of A0 are:
FP1 = 2.9 Hz
FP2 = 265 kHz
FZ1 = 1.3 kHz
If L = 15 µH, COUT = 330 µF and ESR = 55 m, the poles and zeroes of ALC become:
FPLC = 2.5 kHz
FZESR = 8.7 kHz
Finally R1 = 5.6 k and R2 = 3.3 k.
The gain and phase bode diagrams are plotted respectively in Figure 11 and Figure 12.
Figure 11. Module plot
Figure 12. Phase plot
The cut-off frequency and the phase margin are:
Equation 16
F C = 24KHz
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Application information
8
Application information
8.1
Component selection
Input capacitor
The input capacitor must be able to support the maximum input operating voltage and the
maximum RMS input current.
Since step-down converters draw current from the input in pulses, the input current is
squared and the height of each pulse is equal to the output current. The input capacitor has
to absorb all this switching current, which can be up to the load current divided by two (worst
case, with duty cycle of 50%). For this reason, the quality of these capacitors has to be very
high to minimize the power dissipation generated by the internal ESR, thereby improving
system reliability and efficiency. The critical parameter is usually the RMS current rating,
which must be higher than the RMS input current. The maximum RMS input current (flowing
through the input capacitor) is:
Equation 17
2
2
2D
D
I RMS = I O D – ---------------- + ------2
Where is the expected system efficiency, D is the duty cycle and IO is the output DC
current. This function reaches its maximum value at D = 0.5 and the equivalent RMS current
is equal to IO divided by 2 (considering = 1). The maximum and minimum duty cycles are:
Equation 18
V OUT + V F
D MAX = ------------------------------------V INMIN – V SW
and
Equation 19
V OUT + V F
D MIN = -------------------------------------V INMAX – V SW
Where VF is the freewheeling diode forward voltage and VSW the voltage drop across the
internal PDMOS. Considering the range DMIN to DMAX, it is possible to determine the max.
IRMS going through the input capacitor.
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Capacitors that can be considered are:
Electrolytic capacitors:
These are widely used due to their low price and their availability in a wide range of
RMS current ratings.
The only drawback is that, considering ripple current rating requirements, they are
physically larger than other capacitors.
Ceramic capacitors:
If available for the required value and voltage rating, these capacitors usually have
a higher RMS current rating for a given physical dimension (due to very low ESR).
The drawback is the considerably high cost.
Tantalum capacitors:
Very good, small tantalum capacitors with very low ESR are becoming more available.
However, they can occasionally burn if subjected to very high current during charge.
Therefore, it is better to avoid this type of capacitor for the input filter of the device.
They can, however, be subjected to high surge current when connected to the power
supply.
Table 6. List of ceramic capacitors for the A5970AD
Manufacturer
Series
Capacitor value (µF)
Rated voltage (V)
TAIYO YUDEN
UMK325BJ106MM-T
10
50
MURATA
GRM42-2 X7R 475K 50
4.7
50
High dv/dt voltage spikes on the input side can be critical for DC/DC converters. A good
power layout and input voltage filtering help to minimize this issue. In addition to the above
considerations, a 1 µF/50 V ceramic capacitor as close as possible to the VCC and GND
pins is always suggested to adequately filter VCC spikes.
Output capacitor
The output capacitor is very important to meet the output voltage ripple requirement.
Using a small inductor value is useful to reduce the size of the choke but it increases the
current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required.
Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain,
which helps to increase the phase margin of the system. If the zero goes to a very high
frequency, its effect is negligible. For this reason, ceramic capacitors and very low ESR
capacitors in general should be avoided.
Tantalum and electrolytic capacitors are usually a good choice for this purpose. A list of
some tantalum capacitor manufacturers is provided in Table 7.: Output capacitor selection.
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Application information
Table 7. Output capacitor selection
Manufacturer
Series
Cap value (µF)
Rated voltage (V)
ESR (m)
Sanyo POSCAP(1)
TAE
100 to 470
4 to 16
25 to 35
THB/C/E
100 to 470
4 to 16
25 to 55
AVX
TPS
100 to 470
4 to 35
50 to 200
KEMET
T494/5
100 to 470
4 to 20
30 to 200
Sprague
595D
220 to 390
4 to 20
160 to 650
1. POSCAP capacitors have some characteristics which are very similar to tantalum.
Inductor
The inductor value is very important as it fixes the ripple current flowing through the output
capacitor. The ripple current is usually fixed at 20 - 40% of Iomax, which is 0.2 - 0.4 A with
IOmax = 1 A. The approximate inductor value is obtained using the following formula:
Equation 20
V IN – V OUT
L = ---------------------------------- T ON
I
where TON is the ON time of the internal switch, given by D · T. For example, with
VOUT = 3.3 V, VIN = 12 V and IO = 0.3 A, the inductor value is about 15 µH. The peak
current through the inductor is given by:
Equation 21
I
I PK = I O + ----2
and it can be observed that if the inductor value decreases, the peak current (which must be
lower than the current limit of the device) increases. So, when the peak current is fixed,
a higher inductor value allows a higher value for the output current. In Table 8 some inductor
manufacturers are listed.
Table 8. Inductor selection
Manufacturer
Series
Inductor value (µH)
Saturation current (A)
Coilcraft
DO3316T
15 to 33
2.0 to 3.0
Coiltronics
UP1B
22 to 33
2.0 to 2.4
BI
HM76-3
15 to 33
2.5 to 3.3
Epcos
B82476
15 to 33
2 to 3
Wurth Elektronik
74456115
15 to 33
2.5 to 3
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8.2
A5970AD
Layout considerations
The layout of switching DC-DC converters is very important to minimize noise and
interference. Power-generating portions of the layout are the main cause of noise and so
high switching current loop areas should be kept as small as possible and lead lengths as
short as possible.
High impedance paths (in particular the feedback connections) are susceptible to
interference, so they should be as far as possible from the high current paths. An layout
example is provided in Figure 13.
The input and output loops are minimized to avoid radiation and high frequency resonance
problems. The feedback pin connections to the external divider are very close to the device
to avoid pick-up noise.
Figure 13. Layout example
A5970AD
8.3
Thermal considerations
The dissipated power of the device is tied to three different sources:
Conduction losses due to the not insignificant RDSON, which are equal to:
Equation 22
2
P ON = R DSON I OUT D
Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between VOUT and VIN, but in practice it is substantially higher than this value to
compensate for the losses in the overall application. For this reason, the switching losses
related to the RDSON increases compared to an ideal case.
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Application information
Switching losses due to turning ON and OFF. These are derived using the following
equation:
Equation 23
T ON + T OFF
P SW = V IN I OUT ------------------------------------ F SW = V IN I OUT T SW F SW
2
Where TRISE and TFALL represent the switching times of the power element that cause the
switching losses when driving an inductive load (see Figure 14). TSW is the equivalent
switching time.
Figure 14. Switching losses
Quiescent current losses.
Equation 24
P Q = V IN I Q
Where IQ is the quiescent current.
Example 2:
VIN = 12 V
VOUT = 3.3 V
IOUT = 0.8 A
RDS(on) has a typical value of 0.25 at 25 °C and increases up to a maximum value of 0.5. at
150 °C. We can consider a value of 0.4 .
TSW is approximately 70 ns.
IQ has a typical value of 2.7 mA at VIN = 12 V.
The overall losses are:
Equation 25
2
P TOT = R DSON I OUT D + V IN I OUT T SW F SW + V IN I Q =
2
= 0.4 0.8 0.3 + 12 0.8 70 10
–9
3
500 10 + 12 2.7 10
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The junction temperature of device will be:
Equation 26
T J = T A + Rth J – A P TOT
Where TA is the ambient temperature and RthJ-A is the thermal resistance junction to
ambient. Considering that the device is mounted on board with a good ground plane, that it
has a thermal resistance junction to ambient (RthJ-A) of about 120°C/W, and an ambient
temperature of about 50 °C:
Equation 27
T J = 50 + 0.55 120 116C
8.4
Short-circuit protection
In overcurrent protection mode, when the peak current reaches the current limit, the device
reduces the TON down to its minimum value (approximately 250 nsec) and the switching
frequency to approximately one third of its nominal value even when synchronized to an
external signal (see Section 5.4: Current protection on page 11). In these conditions, the
duty cycle is strongly reduced and, in most applications, this is enough to limit the current to
ILIM. In any event, in case of heavy short-circuit at the output (VO = 0 V) and depending on
the application conditions (Vcc value and parasitic effect of external components) the current
peak could reach values higher than ILIM. This can be understood considering the inductor
current ripple during the ON and OFF phases:
ON phase
Equation 28
V IN – V out – DCR L + R DSON I
I L TON = ------------------------------------------------------------------------------------ T ON
L
OFF phase
Equation 29
– V D + V out + DCR L I
I L TOFF = --------------------------------------------------------------- T OFF
L
where VD is the voltage drop across the diode, DCRL is the series resistance of the inductor.
In short-circuit conditions VOUT is negligible so during TOFF the voltage across the inductor
is very small as equal to the voltage drop across parasitic components (typically the DCR of
the inductor and the VFW of the free wheeling diode) while during TON the voltage applied
the inductor is instead maximized as approximately equal to VIN.
So the Equation 28 and the Equation 29 in overcurrent conditions can be simplified to:
Equation 30
V IN – DCR L + R DSON I
V IN
I L TON = ---------------------------------------------------------------- T ON MIN --------- 250ns
L
L
considering TON that has been already reduced to its minimum.
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Equation 31
– V D + V out + DCR L I
– V D + V out + DCR L I
I L TOFF = --------------------------------------------------------------- 3 TSW --------------------------------------------------------------- 6s
L
L
considering that fSW has been already reduced to one third of the nominal.
In case a short-circuit at the output is applied and VIN = 12 V the inductor current is
controlled in most of the applications (see Figure 15). When the application must sustain the
short-circuit condition for an extended period, the external components (mainly the inductor
and diode) must be selected based on this value.
In case the VIN is very high, it could occur that the ripple current during TOFF (Equation 31)
does not compensate the current increase during TON (Equation 30). Figure 17 shows an
example of a power up phase with VIN = VIN MAX = 36 V whereIL TON > IL TOFF so the
current escalates and the balance between Equation 30 and Equation 31 occurs at a current
slightly higher than the current limit. This must be taken into account in particular to avoid
the risk of an abrupt inductor saturation.
Figure 15. Short-circuit current VIN = 12 V
Figure 16. Short-circuit current VIN = 24 V
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Figure 17. Short-circuit current VIN = 36 V
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8.5
Application information
Application circuit
Figure 18 shows the evaluation board application circuit, where the input supply voltage,
VCC, can range from 4 V to 36 V and the output voltage is adjustable from 1.235 V to 6.3 V
due to the voltage rating of the output capacitor.
Figure 18. Evaluation board application circuit
A5970AD
4.7K
Table 9. Component list
Reference
Part number
Description
Manufacturer
C1
GRM42-2 X7R 475K 50
4.7 µF, 50 V
Murata
C2
POSCAP 6TAE330ML
330 µF, 6.3 V
Sanyo
C3
C1206C221J5GAC
220 pF, 5%, 50 V
KEMET
C4
C1206C223K5RAC
22 nF, 10%, 50 V
KEMET
R1
5.6 k, 1%, 0.1 W 0603
Neohm
R2
3.3 k, 1%, 0.1 W 0603
Neohm
R3
4.7 k, 1%, 0.1 W 0603
Neohm
D1
STPS3L40U
2 A, 40 V
STMicroelectronics
L1
DO3316T-153MLD
15 µH, 3.1 A
Coilcraft
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Figure 19. PCB layout (component side)
Figure 20. PCB layout (bottom side)
SL
Figure 21. PCB layout (front side)
LC
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8.6
Application information
Positive buck-boost regulator
The device can be used to implement a step-up/down converter with a positive output
voltage.
The output voltage is given by:
Equation 32
D
V OUT = V IN ------------1–D
where the ideal duty cycle D for the buck boost converter is:
Equation 33
V OUT
D = -----------------------------V IN + V OUT
However, due to power losses in the passive elements, the real duty cycle is always higher
than this. The real value (that can be measured in the application) should be used in the
following formulas.
The peak current flowing in the embedded switch is:
Equation 34
I LOAD I RIPPLE
I LOAD V IN D
I SW = --------------- + -------------------- = --------------- + ----------- --------1–D
2
1 – D 2 L f SW
while its average current is equal to:
Equation 35
I LOAD
I SW = --------------1–D
This is due to the fact that the current flowing through the internal power switch is delivered
to the output only during the OFF phase.
The switch peak current must be lower than the minimum current limit of the overcurrent
protection (see Table 4 on page 6 for details) while the average current must be lower than
the rated DC current of the device.
As a consequence, the maximum output current is:
Equation 36
I OUT MAX I SW MAX 1 – D
where ISW MAX represents the rated current of the device.
The current capability is reduced by the term (1 - D) and so, for example, with a duty cycle of
0.5, and considering an average current through the switch of 1 A, the maximum output
current deliverable to the load is 0.5 A.
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Figure 22 shows the schematic circuit of this topology for a 12 V output voltage and
5 V input.
Figure 22. Positive buck-boost regulator
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Application information
Negative buck-boost regulator
In Figure 23, the schematic circuit for a standard buck-boost topology is shown. The output
voltage is:
Equation 37
D
V OUT = – V IN ------------1–D
where the ideal duty cycle D for the buck boost converter is:
Equation 38
– V OUT
D = -----------------------------V IN – V OUT
The considerations given in Section 8.6 for the real duty cycle are still valid here.
Also the Equation 34 till Equation 36 can be used to calculate the maximum output current.
So, as an example, considering the conversion VIN = 12 V to VOUT = -5 V, ILOAD = 0.3 A:
Equation 39
5
D = ---------------- = 0.706
5 + 12
Equation 40
I LOAD
0.5
I SW = --------------- = ------------------------ = 1A
1–D
1 – 0.706
An important thing to take into account is that the ground pin of the device is connected to
the negative output voltage. Therefore, the device is subjected to a voltage equal to
VIN - VO, which must be lower than 36 V (the maximum operating input voltage).
Figure 23. Negative buck-boost regulator
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8.8
A5970AD
Synchronization example
See Section 5.3: Oscillator and synchronization on page 10 for details.
Figure 24. Synchronization example
A5970AD
8.9
A5970AD
Compensation network with MLCC at the output
MLCCs (multiple layer ceramic capacitor) with values in the range of 10 µF - 22 µF and
rated voltages in the range of 10 V - 25 V are available today at relatively low cost from
many manufacturers.
These capacitors have very low ESR values (a few m) and thus are occasionally used for
the output filter in order to reduce the voltage ripple and the overall size of the application.
However, a very low ESR value affects the compensation of the loop (see Section 7 on page
16) and in order to keep the system stable, a more complicated compensation network may
be required. However, due to the architecture of the internal error amplifier the bandwidth
with this compensation is limited.
That is why output capacitors with a not negligible ESR are suggested. The selection of the
output capacitor have to guarantee that the zero introduced by this component is inside the
designed system bandwidth and close to the frequency of the double pole introduced by the
LC filter. A general rule for the selection of this compound for the system stability is provided
in Equation 41.
Equation 41
1
f Z ESR = ------------------------------------------------ bandwidth
2 ESR C OUT
f LC f Z ESR 10 f LC
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Application information
Figure 25 shows an example of a compensation network stabilizing the system with ceramic
capacitors at the output (the optimum component value depends on the application).
Figure 25. MLCC compensation network example
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8.10
A5970AD
External SOFT_START network
At start-up the device can quickly increase the current up to the current limit in order to
charge the output capacitor. If soft ramp-up of the output voltage is required, an external
soft-start network can be implemented as shown in Figure 26. The capacitor C is charged
up to an external reference through R and the BJT clamps the COMP pin.
This clamps the duty cycle, limiting the slew rate of the output voltage.
Figure 26. Soft-start network example
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Typical characteristics
Typical characteristics
Figure 27. Load regulation
Vo (V)
3.312
Figure 28. Line regulation
Vo (V)
3.312
Vcc = 12V
Vo = 3.3V
3.308
3.304
3.304
Tj = 25°C
3.3
3.296
3.292
3.292
3.288
3.288
3.28
3.276
3.276
0.5
Tj = 125°C
3.284
Tj = 125°C
3.28
0
Tj = 25°C
3.3
3.296
3.284
Vcc = 12V
Vo = 3.3V
3.308
1
1.5
0
Io (A)
Figure 29. Output voltage vs. junction
temperature
Vo (V)
1.25
10
20
Vcc (V)
30
40
Figure 30. Shutdown current vs. junction
temperature
Ishd (A)
70
1.24
60
Vcc = 12V
1.23
50
1.22
Vcc = 12V
1.21
40
Vcc=12V
1.2
-50
30
0
50
Tj (°C)
100
150
-50
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50
Tj (°C)
100
150
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Typical characteristics
A5970AD
Figure 31. Junction temperature vs. output
current - VIN = 12 V
Figure 32. Junction temperature vs. output
current - VIN = 5 V
Figure 33. Efficiency vs output current VIN = 12 V
Figure 34. Efficiency vs output current VIN = 5 V
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10
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 35. SO-8 package outline
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Package information
A5970AD
Table 10. SO-8 package mechanical data
Dimensions
Symbol
mm
Min.
Typ.
inch
Max.
Min.
Typ.
Max.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D (1)
4.80
5.00
0.189
0.197
E
3.80
4.00
0.15
0.157
e
1.27
0.050
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
ddd
0° (min.), 8° (max.)
0.10
0.004
1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm (0.006 inch) in total (both sides).
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11
Ordering information
Ordering information
Table 11. Ordering information
Order code
Package
A5970AD
Tube
SO8
A5970ADTR
12
Packaging
Tape and reel
Revision history
Table 12. Document revision history
Date
Revision
02-May-2008
1
Initial release
27-Aug-2008
2
Updated: coverpage and Table 4 on page 5
23-Apr-2009
3
Updated first feature in coverpage
04-Nov-2009
4
Updated coverpage, Table 4 on page 6 and added Figure 27,
Figure 28, Figure 29 and Figure 30 on page 37.
5
Updated Section 8.1: Component selection on page 21 (updated
units in “Capacitor value” - header of Table 6, added text below
Table 6).
Updated titles from Figure 31 to Figure 34 (added values of “VIN”).
Updated Section 10: Package information on page 39 (reversed
order of Figure 35 and Table 10, updated titles, minor modifications).
Updated cross-references throughout document.
Minor modifications throughout document.
31-Mar-2014
Changes
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