L6668
SMART PRIMARY CONTROLLER
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General Features
Figure 1. Package
MULTIPOWER BCD TECHNOLOGY
LOAD-DEPENDENT CURRENT-MODE CONTROL: FIXED-FREQUENCY (HEAVY LOAD),
FREQUENCY FOLDBACK (LIGHT LOAD),
BURST-MODE (NO-LOAD)
ON-BOARD HIGH-VOLTAGE START-UP
IMPROVED STANDBY FUNCTION
LOW QUIESCENT CURRENT (< 2 mA)
SLOPE COMPENSATION
PULSE-BY-PULSE & HICCUP-MODE OCP
INTERFACE WITH PFC CONTROLLER
DISABLE FUNCTION (ON/OFF CONTROL)
LATCHED DISABLE FOR OVP/OTP FUNCTION
PROGRAMMABLE SOFT-START
2% PRECISION REFERENCE VOLTAGE EXTERNALLY AVAILABLE
±800 mA TOTEM POLE GATE DRIVER WITH
INTERNAL CLAMP AND UVLO PULL-DOWN
BLUE ANGEL, ENERGY STAR, EU CODE OF
CONDUCT COMPLIANT
SO-16 (Narrow)
Table 1. Order Codes
Part Number
Package
L6668
SO-16
L6668TR
SO-16 in Tape & Reel
SO16 PACKAGE ECOPACK®
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1.1 APPLICATIONS
HI-END AC-DC ADAPTERS/CHARGERS FOR
NOTEBOOKS.
LCD/CRT MONITORS, LCD/CRT TV
DIGITAL CONSUMER
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Figure 2. Block Diagram
S-COMP
V CC
HV
15
5
1
SLOPE
COMP.
VREG
25V
Vref
16
HV generator ON/OFF
and UVLO management
CLK
RCT
TIMING
8
VREF
Vcc_OK
DIS
R
+
7
S
Q
-
DIS
2.2V
N.C.
15V
4
OUT
6
S
BLANKING
Q
R
12
HICCUP
R
+
ISEN
+
PWM
-
S
Vcc_OK
DIS
OCP
Q
3
VREG
GND
-
-
HYST. CTRL
1.5V
+
0.4mA
PFC_STOP
13
+
14
DIS
OCP
STANDBY
0.8V
4R
SOFT-START
9
SKIPADJ
January 2006
ST-BY
11R
2.2/2.7V
11
SS
10
COMP
Rev. 4
1/23
L6668
2
Description
L6668 is a current-mode primary controller IC, designed to build single-ended converters.
The IC drives the system at fixed frequency at heavy load and an improved Standby function causes a
smooth frequency reduction as the load is progressively reduced. At very light load the device enters a
special operating mode (burst-mode with fixed, externally programmed peak current) that, in addition to
the on-board high-voltage start-up and the very low quiescent current, helps keep low the consumption
from the mains and be compliant with energy saving regulations. To allow meeting compliance with these
standards in power-factor-corrected systems too, an interface with the PFC controller is provided that enables to turn off the pre-regulator when the load level falls below a threshold.
The IC includes also a programmable soft-start, slope compensation for stable operation at duty cycles
greater then 50%, a disable function, a leading edge blanking on current sense to improve noise immunity,
latched disable for OVP or OTP shutdown and an effective two-level OCP able to protect the system even
in case the secondary diode fails short.
Table 2. Absolute Maximum Ratings
Symbol
Pin
Vcc
5
VHV
IHV
1
Value
Unit
IC Supply voltage (Icc = 20 mA)
Self-limited
V
1
High-voltage start-up generator voltage range
-0.3 to 700
V
1
High-voltage start-up generator current
Self-limited
A
Analog Inputs & Outputs, except pin 14
-0.3 to 8
V
---
Parameter
IPFC_STOP
14
Max. sink current (low state)
2
mA
VPFC_STOP
14
Max. voltage (open state)
16
V
0.75
W
Junction Temperature Operating range
-25 to 150
°C
Storage Temperature
-55 to 150
°C
Ptot
Tj
Tstg
Power Dissipation @Tamb = 50°C
Note: 1. ESD immunity for pin 1 is guaranteed up to 900V (Human Body Model).
Table 3. Thermal Data
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction to AmbientMax
Figure 3. Pin Connection (Top view)
2/23
HV
RCT
HVS
S-COMP
GND
PFC_STOP
OUT
STBY
Vcc
ISEN
N.C.
SS
DIS
COMP
VREF
SKIPADJ
Value
Unit
120
°C/W
L6668
Table 4. Pin Description
Pin
Number
Pin Name
Function
1
HV
High-voltage start-up. The pin is to be connected directly to the rectified mains voltage. A
0.8 mA internal current source charges the capacitor connected between pin Vcc and GND
to start up the IC. When the voltage on the Vcc pin reaches the start-up threshold the generator is shut down. Normally it is re-enabled when the voltage on the Vcc pin falls below
5V, except under latched shutdown conditions, when it is re-enabled as the Vcc voltage falls
0.5V below the start-up threshold.
2
HVS
High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and
comply with safety regulations (creepage distance) on the PCB.
3
GND
Chip ground. Current return for both the gate-drive current and the bias current of the IC. All
of the ground connections of the bias components should be tied to a track going to this pin
and kept separate from any pulsed current return.
4
OUT
Gate-drive output. The driver is capable of 0.8A min. source/sink peak current to drive
MOSFET’s. The voltage delivered to the gate is clamped at about 15V so as to prevent too
high values when the IC is supplied with a voltage close to or exceeding 20V.
5
Vcc
Supply Voltage of both the signal part of the IC and the gate driver. The internal high voltage generator charges an electrolytic capacitor connected between this pin and GND as
long as the voltage on the pin is below the start-up threshold of the IC, after that it is disabled. Sometimes a small bypass capacitor (0.1µF typ.) to GND might be useful to get a
clean bias voltage for the signal part of the IC.
6
N.C.
Connect the pin to GND.
7
DIS
Latched device shutdown. Internally the pin connects a comparator that, when the voltage
on the pin exceeds 2.2V, shuts the IC down and brings its consumption to a value barely
higher than before start-up. The information is latched and it is necessary to recycle the
input power to restart the IC: the latch is removed as the voltage on the Vcc pin goes below
the UVLO threshold. Connect the pin to GND if the function is not used.
8
VREF
Voltage reference. An internal generator furnishes an accurate voltage reference (5V±4%,
all inclusive) that can be used to supply up to 5 mA to an external circuit. A small film
capacitor (0.1µF typ.), connected between this pin and GND is recommended to ensure the
stability of the generator and to prevent noise from affecting the reference.
9
SKIPADJ
Burst-mode control threshold. A voltage is applied to this pin, derived from the reference
voltage VREF via a resistor divider. When the control voltage at pin COMP falls 50 mV
below the voltage on this pin the IC is shutdown and the consumption is reduced. The chip
is re-enabled as the voltage on pin COMP exceeds the voltage on the pin. The high-voltage
start-up generator is not invoked. The function is disabled during the soft-start ramp. The
pin must always be biased between 0.8 and 2.5V. A voltage between 0.8 and 1.4V disables
the function, if the pin is pulled below 0.8V the IC is shut down.
10
COMP
Control input for PWM regulation. The pin is to be driven by the phototransistor (emittergrounded) of an optocoupler to modulate the voltage by modulating the current sunk from
(sourced by) the pin (0.4 mA typ.). It is recommended to place a small filter capacitor
between the pin and GND, as close to the IC as possible to reduce switching noise pick up,
to set a pole in the output-to-control transfer function. A voltage 50 mV lower than that on
pin SKIPADJ shuts down the IC and reduces its current consumption.
11
SS
Soft start. An internal 20µA generator charges an external capacitor connected between
the pin and GND generating a voltage ramp across it. This ramp clamps the voltage at pin
COMP during start-up, thus the duty cycle of the power switch starts from zero. During the
ramp all functions monitoring the voltage at pin COMP are disabled. The SS capacitor is
quickly discharged as the chip goes into UVLO.
12
ISEN
Current sense (PWM comparator) input. The voltage on this pin is internally compared with
an internal reference derived from the voltage on pin COMP and when they are equal the
gate drive output (previously asserted high by the clock signal generated by the oscillator)
is driven low to turn off the power MOSFET. The pin is equipped with 200 ns. min. blanking
time for improved noise immunity. A second comparison level located at 1.5V shuts the
device down and brings its consumption almost to a “before start-up” level.
3/23
L6668
Table 4. Pin Description (continued)
Pin
Number
Pin Name
Function
13
STBY
Standby function. This pin is a high-impedance one as long as the voltage on pin COMP is
higher than 3V. When the voltage on pin COMP falls below 3V, the voltage on the pin tracks
that on pin COMP and is capable of sinking current. A resistor connected from the pin to the
oscillator allows programming frequency foldback at light load.
14
PFC_STOP
Open-drain ON/OFF control of PFC controller. This pin is intended for driving the base of a
PNP transistor in systems comprising a PFC pre-regulator, to stop the PFC controller at
light load by cutting its supply. The pin, normally low, opens if the voltage on COMP is lower
than 2.2V and goes back low when the voltage on pin COMP exceeds 2.7V. Whenever the
IC is shutdown, either latched (DIS >2.2V, ISEN >1.5V) or not (UVLO, SKIPADJ 2.2, or VISEN > 1.5
µA
2.5
mA
4
mA
180
VSKIPADJ 3V
1
mA
IHV, ON
ON-state current
VHV > VHvstart, Vcc > 3V
1.6
mA
VHV > VHvstart, Vcc = 0
0.8
IHV, OFF
Leakage current (OFF state)
VCCrestart
HV generator restart voltage
VHV = 400 V
(1)
4/23
After DIS tripping
40
µA
4.4
5
5.6
V
12
13
14
V
L6668
Table 5. Electrical Characteristcs (continued)
(Tj = 0 to 105°C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
4.925
5
5.075
V
REFERENCE VOLTAGE
VREF
Output voltage
(2)
VREF
Total variation
Vcc= 9.4 to 22 V,
IREF = 1 to 5 mA
4.8
5.13
V
IREF
Short circuit current
VREF = 0
10
30
mA
Sink capability in UVLO
Vcc = 6V; Isink = 0.5 mA
0.2
0.5
V
400
480
µA
Tj = 25 °C; IREF = 1 mA
PWM CONTROL
Maximum level
ICOMP =0
5.5
ICOMP
Max. source current
VCOMP = 1 V
320
RCOMP
Dynamic resistance
VCOMP = 2 to 4 V
Dmax
Maximum duty cycle
VCOMP = 5 V
Dmin
Minimum duty cycle
VCOMPH
V
kΩ
22
70
75
%
VCOMP = 1 V
0
%
-1
µA
ns
CURRENT SENSE COMPARATOR
IISEN
Input Bias Current
VISEN = 0
tLEB
Leading Edge Blanking
After gate drive low-to-high
transition
td(H-L)
VISENdis
225
290
100
ns
3.56
3.75
3.94
V/V
0.725
0.8
0.875
V
1.35
1.5
1.65
V
Delay to Output
Gain
VISENx
160
Maximum signal
VCOMP = 5 V
Hiccup-mode OCP level
(2)
STANDBY FUNCTION
Vdrop
Vth
VCOMP - VSTBY
ISTBY = 0.8 mA, VCOMP2.2V” in the table 4 pin 14.
L6668
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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