EVL6566A-75WES4

L6563S Enhanced transition-mode PFC controller Features ■ Tracking boost function ■ Fast “bidirectional” input voltage feedforward (1/V2 correction) ■ Interface for cascaded converter's PWM controller ■ Remote ON/OFF control ■ Accurate adjustable output overvoltage protection ■ Protection against feedback loop disconnection (latched shutdown) ■ Inductor saturation protection ■ Low (≤ 100 µA) start-up current ■ 6 mA max. operating bias current ■ 1% (@ TJ = 25 °C) internal reference voltage ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO SO14 Applications PFC pre-regulators for: ■ High-end AC-DC adapter/charger ■ Desktop PC, server, Web server ■ IEC61000-3-2 or JEITA-MITI compliant SMPS, in excess of 400 W ■ SO14 package Figure 1. Block diagram 3:0B6723 581   9 9 9 9  212))&RQWURO =&' 9 9  =HUR&XUUHQW 'HWHFWRU    'LVDEOH 9 9  3)&B2. 9FF    293 9ROWDJH UHIHUHQFHV 92/7$*( 5(*8/$725 «  89/2 ,QWHUQDO6XSSO\%XV  89/2 /B293 6  4 *'   9 5 75$&.,1* %2267  '5,9(5 &/$03 67$57(5  &855(17 0,5525 7%2 &203 ,19   %8))(5  9 ',6$%/( IURP 9)) 'LVDEOH 4 /(%  6 /B293 5 89/2 9ELDV (UURU$PSOLILHU  /B293    ,GHDOUHFWLILHU *1' 4 293 212))&RQWURO   9 08/7 6WDUWHU 2)) 9  08/7,3/,(5    0$,16'523 '(7(&725  9 3:0B /$7&+ &6 'LVDEOH   9)) !-V December 2010 Doc ID 16116 Rev 4 1/43 www.st.com 43 Contents L6563S Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 Tracking boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.6 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.7 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 31 7 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2/43 Doc ID 16116 Rev 4 L6563S List of table List of table Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Summary of L6563S idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO14 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Doc ID 16116 Rev 4 3/43 List of figure L6563S List of figure Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 4/43 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IC consumption vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IC consumption vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Vcc Zener voltage vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Start-up and UVLO vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Feedback reference vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 E/A output clamp levels vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 UVLO saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 OVP levels vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inductor saturation threshold vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Vcs clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ZCD sink/source capability vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ZCD clamp level vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TBO clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VVFF - VTBO dropout vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 IINV - ITBO current mismatch vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 IINV - ITBO mismatch vs ITBO current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 R discharge vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Line drop detection threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VMULTpk - VVFF dropout vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PFC_OK threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PFC_OK FFD threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PWM_LATCH high saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RUN threshold vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PWM_STOP low saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Multiplier characteristics @ VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multiplier characteristics @ VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multiplier gain vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Gate drive clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Gate drive output saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Delay to output vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Start-up timer period vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 23 Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic . . 25 RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 26 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 THD optimization: standard TM PFC controller (left side) and L6563S (right side) . . . . . . 28 Tracking boost block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Tracking output voltage vs Input voltage characteristic with TBO . . . . . . . . . . . . . . . . . . . 30 Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 31 Interface circuits that let dc-dc converter's controller IC drive L6563S in burst mode . . . . 32 Interface circuits that let the L6563S switch on or off a PWM controller. . . . . . . . . . . . . . . 32 Interface circuits for power up sequencing when dc-dc has the SS function . . . . . . . . . . . 33 Interface circuits for actual power-up sequencing (master PFC) . . . . . . . . . . . . . . . . . . . . 33 Brownout protection (master PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Demonstration board EVL6563S-100W, wide-range mains: electrical schematic . . . . . . . 35 Doc ID 16116 Rev 4 L6563S Figure 49. Figure 50. Figure 51. load Figure 52. W load Figure 53. Figure 54. Figure 55. matic Figure 56. List of figure L6563S 100 W TM PFC demonstration board: compliance to EN61000-3-2 standard . . . 36 L6563S 100 W TM PFC demonstration board: compliance to JEITA-MITI standard . . . . . 36 L6563S 100 W TM PFC demonstration board: input current waveform @230-50 Hz - 100 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 L6563S 100W TM PFC demonstration board: input current waveform @100 V-50 Hz - 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 EVL6563S-250W TM PFC demonstration board: electrical schematic . . . . . . . . . . . . . . . 37 EVL6563S-400W FOT PFC demonstration board: electrical schematic . . . . . . . . . . . . . . 37 EVL6563S-ZRC200W 200W PFC pre-regulator with ripple-free input current: electrical sche. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Doc ID 16116 Rev 4 5/43 Description 1 L6563S Description The L6563S is a current-mode PFC controller operating in transition mode (TM). Coming with the same pin-out as its predecessor L6563, it offers improved performance and additional functions. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @ TJ = 25 °C) internal voltage reference. Loop’s stability is optimized by the voltage feedforward function (1/V2 correction), which in this IC uses a proprietary technique that considerably improves line transient response as well in case of mains both drops and surges (“bidirectional”). Additionally, the IC provides the option for tracking boost operation, i.e. the output voltage is changed tracking the mains voltage. The device includes disable functions suitable for remote ON/OFF control both in systems where the PFC pre-regulator works as a master and in those where it works as a slave. In addition to an overvoltage protection able to keep the output voltage under control during transient conditions, the IC is provided also with a protection against feedback loop failures or erroneous settings. Other on-board protection functions allow that brownout conditions and boost inductor saturation can be safely handled. An interface with the PWM controller of the DC-DC converter supplied by the PFC preregulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor’s core saturation, etc.) and to disable the PFC stage in case of light load for the DC-DC converter, so as to make it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOSFET or IGBT drive. This, combined with the other features and the possibility to operate with ST’s proprietary Fixed-Off-Time control, makes the device an excellent solution for SMPS up to 400 W that need to be compliant with EN61000-3-2 and JEITA-MITI standards. 6/43 Doc ID 16116 Rev 4 L6563S Maximum ratings 2 Maximum ratings 2.1 Absolute maximum ratings Table 1. Symbol Pin Vcc 14 --- 1, 3, 7 --- 2.2 Absolute maximum ratings Parameter Value Unit IC supply voltage (Icc = 20 mA) self-limited V Max. pin voltage (Ipin =1 mA) Self-limited V -0.3 to 8 V -0.3 to Vcc V 3 mA -10 (source) 10 (sink) mA +/- 1250 V +/- 2000 V Value Unit 2, 4 to 6, 8, 10 Analog inputs and outputs VPWM_STOP 9 Analog output IPWM_STOP 9 Max. sink current IZCD 11 Zero current detector max. current VFF pin 5 Other pins 1 to 4 6 to 14 Maximum withstanding voltage range test condition: CDF-AEC-Q100-002 “human body model” Acceptance criteria: “normal performance” Thermal data Table 2. Thermal data Symbol Parameter RthJA Max. thermal resistance, junction-to-ambient 120 °C/W Ptot Power dissipation @TA = 50 °C 0.75 W Junction temperature operating range -40 to 150 °C Storage temperature -55 to 150 °C TJ Tstg Doc ID 16116 Rev 4 7/43 Pin connection 3 L6563S Pin connection Figure 2. Pin connection ,19   9FF &203   *' 08/7   *1' &6   =&' 9))   581 7%2   3:0B6723 3)&B2.   3:0B/$7&+ !-V Table 3. n° Pin description Name Function INV Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. The pin normally features high impedance but, if the tracking boost function is used, an internal current generator programmed by TBO (pin 6) is activated. It sinks current from the pin to change the output voltage so that it tracks the mains voltage. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below 2.4 V the gate driver output will be inhibited (burst-mode operation). 3 MULT Mains input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily stops the converter and limits the stress of the power components. VFF Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a dc level equal to the peak voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage. Never connect the pin directly to GND but with a resistor ranging from 100 kΩ (minimum) to 2 MΩ (maximum). TBO Tracking boost function. This pin provides a buffered VFF voltage. A resistor connected between this pin and GND defines a current that is sunk from pin INV (#1). In this way, the output voltage is changed proportionally to the mains voltage (tracking boost). If this function is not used leave this pin open. 1 4 5 6 8/43 Doc ID 16116 Rev 4 L6563S Pin connection Table 3. n° 7 Pin description (continued) Name Function PFC_OK PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66V, a feedback failure is assumed. In this case the device is latched off and the pin PWM_LATCH (#8) is asserted high. Normal operation can be resumed only by cycling Vcc bringing its value lower than 6V before to move up the Turn on threshold. If the voltage on this pin is brought below 0.23 V the IC is shut down. To restart the IC the voltage on the pin must go above 0.27 V. This can be used as a remote on/off control input. Output pin for fault signaling. During normal operation this pin features high impedance. If a feedback failure is detected (PFC_OK > 2.5 V and INV< 1.66V) the pin is asserted high. 8 PWM_LATCH Normally, this pin is used to stop the operation of the dc-dc converter supplied by the PFC preregulator by invoking a latched disable of its PWM controller. If not used, the pin will be left floating. 9 Output pin for fault signaling. During normal operation this pin features high impedance. If the IC is disabled by a voltage below 0.8 V on pin RUN (#10) the voltage on the pin is pulled to ground. Normally, this pin is used to temporarily stop the operation of the dc-dc converter PWM_STOP supplied by the PFC pre-regulator by disabling its PWM controller. A typical usage of this function is brownout protection in systems where the PFC pre-regulator is the master stage. If not used, the pin will be left floating. 10 RUN Remote ON/OFF control. A voltage below 0.8V shuts down (not latched) the IC and brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC restarts as the voltage at the pin goes above 0.88 V. Connect this pin to pin VFF (#5) either directly or through a resistor divider to use this function as brownout (AC mains undervoltage) protection. 11 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. 12 GND Ground. Current return for both the signal part of the IC and the gate driver. 13 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages. 14 Vcc Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. Doc ID 16116 Rev 4 9/43 Pin connection L6563S Figure 3. Typical system block diagram 0% 2%'5,!4/2 $# $##/.6%24%2 6OUTDC 6INAC 07-ISTURNEDOFFINCASEOF0&#gS ANOMALOUSOPERATIONFORSAFETY ,( ,3 07-OR 2ESONANT #/.42/,,%2 0&#CANBETURNEDOFFATLIGHT LOADTOEASECOMPLIANCEWITH ENERGYSAVINGREGULATIONS !-V 10/43 Doc ID 16116 Rev 4 L6563S 4 Electrical characteristics Electrical characteristics TJ = -25 to 125 °C, VCC = 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply voltage Vcc Operating range After turn-on VccOn Turn-on threshold (1) 11 VccOff Turn-off threshold (1) Vcc for resuming from latch OVP latched Vccrestart Hys Hysteresis VZ Zener voltage 10.3 22.5 V 12 13 V 8.7 9.5 10.3 V 5 6 7 V 2.7 V 25 28 V 2.3 Icc = 20 mA 22.5 Supply current Istart-up Iq ICC Iqdis Iq Start-up current Before turn-on, Vcc = 10 V 90 150 µA Quiescent current After turn-on, VMULT = 1 V 4 5 mA Operating supply current @ 70 kHz 5 6.0 mA VPFC_OK > VPFC_OK_S AND VINV < VPFC_OK – VFFD 180 280 µA VPFC_OK < VPFC_OK_D OR VRUN < VDIS 1.5 2.2 mA VPFC_OK > VPFC_OK_S OR VCOMP < 2.3 V 2.2 3 mA VMULT = 0 to 3 V -0.2 -1 µA Idle state quiescent current Quiescent current Multiplier input IMULT Input bias current VMULT Linear operation range 0 to 3 V VCLAMP Internal clamp level IMULT = 1 mA ΔVcs ΔVMULT Output max. slope VMULT =0 to 0.4 V, VVFF = 0.8 V VCOMP = Upper clamp Gain (2) VMULT = 1 V, VCOMP = 4 V 0.375 0.45 0.525 1/V TJ = 25 °C 2.475 2.5 2.525 2.455 2.545 KM 9 9.5 V 2.2 2.34 V/V Error amplifier VINV IINV Voltage feedback input threshold 10.3 V < Vcc < 22.5 V (3) Line regulation Vcc = 10.3 V to 22.5 V Input bias current TBO open, VINV = 0 to 4 V VINVCLAMP Internal clamp level IINV = 1 mA Doc ID 16116 Rev 4 V 8 2 5 mV -0.2 -1 µA 9 V 11/43 Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Parameter Gv Voltage gain GB Gain-bandwidth product ICOMP VCOMP L6563S Test condition Open loop Min. Typ. Max. Unit 60 80 dB 1 MHz Source current VCOMP = 4 V, VINV = 2.4 V 2 4 mA Sink current VCOMP = 4 V, VINV = 2.6 V 2.5 4.5 mA Upper clamp voltage ISOURCE = 0.5 mA 5.7 6.2 6.7 Burst-mode voltage (3) 2.3 2.4 2.5 2.1 2.25 2.4 Lower clamp voltage ISINK = 0.5 mA (3) V Current sense comparator ICS Input bias current tLEB Leading edge blanking 100 Delay to output td(H-L) VCSclamp Vcsofst Current sense reference clamp Current sense offset VCS = 0 1 µA 150 250 ns 100 200 300 ns 1.0 1.08 1.16 V VMULT = 0, VVFF = 3 V 40 70 VMULT = 3 V, VVFF = 3 V 20 VCOMP = Upper clamp, VMULT =1 V VVFF = 1 V mV Boost inductor saturation detector VCS_th IINV Threshold on current sense (3) E/A input pull-up current After VCS > VCS_th, before restarting 1.6 1.7 1.8 V 5 10 13 µA -0.1 -1 µA PFC_OK functions IPFC_OK Input bias current VPFC_OK = 0 to 2.6 V VPFC_OK_C Clamp voltage IPFC_OK = 1 mA VPFC_OK_S OVP threshold (1) voltage rising VPFC_OK_R Restart threshold after OVP (1) VPFC_OK_D Disable threshold (1) VPFC_OK_D Disable threshold (1) VPFC_OK_E Enable threshold VPFC_OK_E Enable threshold VFFD Feedback failure detection threshold (VINV falling) 9 9.5 V 2.435 2.5 2.565 V voltage falling 2.34 2.4 2.46 V voltage falling 0.12 0.35 V voltage falling TJ = 25 °C 0.17 0.23 0.29 V (1) voltage rising 0.15 0.38 V (1) voltage rising Tj = 25 °C 0.21 0.27 0.32 V VPFC_OK > VPFC_OK_S 1.61 1.66 1.71 mV Zero current detector VZCDH Upper clamp voltage IZCD = 2.5 mA 5.0 5.7 VZCDL Lower clamp voltage IZCD = - 2.5 mA -0.3 0 0.3 V VZCDA Arming voltage (positive-going edge) 1.1 1.4 1.9 V 12/43 Doc ID 16116 Rev 4 V L6563S Electrical characteristics Electrical characteristics (continued) Table 4. Symbol Parameter VZCDT Triggering voltage (negative-going edge) IZCDb Input bias current Test condition Min. Typ. Max. Unit 0.5 0.7 VZCD = 1 to 4.5 V 0.9 V 1 µA IZCDsrc Source current capability -2.5 -4 mA IZCDsnk Sink current capability 2.5 5 mA Tracking boost function ΔV ITBO Dropout voltage VVFF-VTBO Linear operation -20 20 mV 0 0.2 mA IINV-ITBO current mismatch ITBO = 25 µA to 0.2mA -5.5 +1.0 % IINV-ITBO current mismatch ITBO = 25 µA to 0.2mA TJ = 25 °C -4.0 +0 % (3) V VFF 2.9 3.1 V VTBO = 1 V VFF = VMULT = 0 V 2 μA VTBOclamp Clamp voltage ITBO_Pull ITBO = 0.2 mA Pull-up current =4V 3 PWM_STOP Ileak High level leakage current VPWM_STOP = Vcc 1 µA VL Low level IPWM_STOP = 0.5 mA 1 V Input bias current VRUN = 0 to 3 V -1 µA Disable threshold (3) voltage falling 0.745 0.8 0.855 V Enable threshold (3) voltage rising 0.845 0.88 0.915 V RUN function IRUN VDIS VEN Start-up timer tSTART_DEL Start-up delay tSTART First cycle after wake-up 25 50 75 75 150 300 150 300 600 Timer period µs µs Restart after VCS > VCS_th Voltage feedforward VVFF Linear operation range ΔV Dropout VMULTpk-VVFF 0.8 3 Vcc < VccOn 800 Vcc > or = to VccOn 20 V mV ΔVVFF Line drop detection threshold Below peak value 40 70 100 mV ΔVVFF Line drop detection threshold Below peak value TJ = 25 °C 50 70 90 mV 10 12.5 Internal discharge resistor TJ = 25 °C 7.5 RDISCH 5 Doc ID 16116 Rev 4 kΩ 20 13/43 Electrical characteristics Table 4. Electrical characteristics (continued) Symbol VVFF L6563S Parameter Test condition Linear operation range Min. Typ. Max. Unit 0.8 3 V -1 µA PWM_LATCH Ileak Low level leakage current VPWM_LATCH = 0 VH High level IPWM_LATCH = -0.5 mA 4.5 V VH High level IPWM_LATCH = -0.25 mA Vcc = VccOff 2.5 V VH High level IPWM_LATCH = -0.25 mA Vcc = VccOff TJ = 25 °C 2.8 V VOL Output low voltage Isink = 100 mA VOH Output high voltage Isource = 5 mA Isrcpk Peak source current -0.6 A Isnkpk Peak sink current 0.8 A Gate driver 9.8 1.2 10.3 V V tf Voltage fall time 30 60 ns tr Voltage rise time 45 110 ns 12 15 V 1.1 V VOclamp Output clamp voltage Isource = 5 mA; Vcc = 20 V UVLO saturation Vcc= 0 to VCCon, Isink = 2 mA 1. Parameters tracking each other 2. The multiplier output is given by: Vcs = VCS_Ofst + K M ⋅ ( VMULT ⋅ VCOMP − 2.5 2 V VFF ) 3. Parameters tracking each other 14/43 0.6 Doc ID 16116 Rev 4 10 L6563S Typical electrical performance 5 Typical electrical performance Figure 4. IC consumption vs VCC   Figure 5.   100 IC consumption vs TJ 10 Operating 10 Quiescent Disabled or during OV P 1 Co=1nF f =70kHz Tj = 25°C I cc [m A] VCC=12V Co = 1nF f =70kHz I c current (m A) 1 0.1 Latched off 0.1 Before Start up 0.01 VccOFF VccON 0.01 0. 001 0 5 10 15 20 25 -50 30 -25 0 25 50 Figure 6.   75 100 125 150 175 Tj (C) Vcc [V ] Vcc Zener voltage vs TJ Figure 7. Start-up and UVLO vs TJ   28 13 V CC-ON 12 27 11 26 VCC-OFF V V 10 25 9 24 8 23 7 6 22 -50 -25 0 25 50 75 100 125 150 175 -50 Tj (C) -25 0 25 50 75 100 125 150 175 Tj (C) Doc ID 16116 Rev 4 15/43 Typical electrical performance Figure 8.   L6563S Feedback reference vs TJ Figure 9. E/A output clamp levels vs TJ   2. 6 7 Uper Clam p 6 VCC = 12V 2.55 5 V COM P (V ) pi n INV (V ) V CC = 12V 2. 5 4 3 Lower Clamp 2 2.45 1 0 2. 4 -50 -25 0 25 50 75 Tj (C) 100 125 150 -25 0 25 50 75 100 150 175 Figure 11. OVP levels vs TJ   1 2. 5 0.9 2. 48 VCC = 0V 0.8 OV P T h 2. 46 P FC_OK l evels (V ) 0.7 0.6 V 125 Tj (C) Figure 10. UVLO saturation vs TJ   -50 175 0.5 0.4 2. 44 2. 42 2. 4 0.3 Resta rt Th 0.2 2. 38 0.1 2. 36 0 -50 -50 -25 0 25 50 75 100 125 150 175 Tj (C) 16/43 Doc ID 16116 Rev 4 -25 0 25 50 75 Tj (C) 100 125 150 175 L6563S Typical electrical performance Figure 12. Inductor saturation threshold vs TJ Figure 13. Vcs clamp vs TJ     1.9 1. 4 1.8 1.7 1. 3 VCSx (V ) CS pi n (V ) 1.6 1.5 VCC = 12V VCOMP =Upper clamp 1. 2 1.4 1.3 1. 1 1.2 1.1 1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 Figure 14. ZCD sink/source capability vs TJ   100 125 150 175 Figure 15. ZCD clamp level vs TJ   8 7 Si nk curren t 6 Upper Clamp 6 4 5 2 V ZCD pin (V ) IZCDsrc (mA) 75 Tj (C) Tj (C) V CC = 12V 0 -2 4 VCC = 12V Izcd =± 2.5mV 3 2 Source current -4 1 -6 0 -8 -50 Lower Cl am p -1 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) Doc ID 16116 Rev 4 17/43 Typical electrical performance L6563S Figure 16. TBO clamp vs TJ Figure 17. VVFF - VTBO dropout vs TJ   5 3.5 4 3 3.25 2 mV 1 V 3 0 -1 -2 2.75 -3 -4 -5 2.5 -50 -25 0 25 50 Tj (C) 75 100 125 150 Figure 18. IINV - ITBO current mismatch vs TJ   -50 175 -25 0 25 50 75 100 125 150 175 T j (C) Figure 19. IINV - ITBO mismatch vs ITBO current   0 -1.6 VCC = 12V -1.8 -1 100*{I(I NV )-I(TBO)}/I (TBO) [ % ] 100*{I(INV)-I(TBO)}/I(TBO) [ % ] -0.5 I TBO = 200uA -1.5 -2 ITBO = 25uA -2.5 -3 -2 -2.2 -2.4 VCC = 12V Tj = 25°C -2.6 -2.8 -3.5 -4 -3 -50 -25 0 25 50 75 100 125 150 175 0 Tj (C) 18/43 Doc ID 16116 Rev 4 100 200 300 I(TBO) 400 500 600 L6563S Typical electrical performance Figure 20. R discharge vs TJ   Figure 21. Line drop detection threshold vs TJ   20 90 18 80 16 70 14 60 50 mV kOhm 12 10 40 8 30 6 20 4 10 2 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 Figure 22. VMULTpk - VVFF dropout vs TJ 100 125 150 175 150 175 Figure 23. PFC_OK threshold vs TJ 2 0.4 1. 5 0.35 1 0.3 0. 5 0.25 Th (V ) ⎯ (m V)   75 Tj (C) Tj (C) 0 ON 0.2 -0. 5 0.15 -1 0.1 -1. 5 0.05 -2 OFF 0 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 -50 Doc ID 16116 Rev 4 -25 0 25 50 Tj (C) 75 100 125 19/43 Typical electrical performance L6563S Figure 24. PFC_OK FFD threshold vs TJ   Figure 25. PWM_LATCH high saturation vs TJ   2 10 VCC = 12V 1.9 9 1.7 7 1.6 6 1.5 5 1.4 -50 Isource =500uA 8 V VFFD Th (V ) 1.8 -25 0 25 50 75 100 125 150 Isource =250uA 4 17 5 -50 -25 0 25 Tj(C) Figure 26. RUN threshold vs TJ 50 75 T j (C) 100 125 150 175 Figure 27. PWM_STOP low saturation vs TJ   0. 25 1 ON 0.2 VCC = 12V Isink = 0. 5m A 0.8 OFF V V 0. 15 VCC = 12V 0.1 0.6 0. 05 0.4 0 -50 -25 0 25 50 75 100 125 150 175 -50 20/43 -25 0 25 50 75 Tj (C) T j (C) Doc ID 16116 Rev 4 100 125 150 175 L6563S Typical electrical performance Figure 28. Multiplier characteristics @ VFF = 1 V   Figure 29. Multiplier characteristics @ VFF = 3 V   1. 2 700 VCOMP 1. 1 V COM P Upper voltage cl amp 1 600 Upper vo ltage 5 .5 5 .0V 0. 9 4.5 V 500 4. 0V 400 0. 8 V CS (V ) V CS (m V) 5. 5V 0. 7 0. 6 0. 5 5. 0V 4. 5V 300 3.5 V 4. 0V 0. 4 200 0. 3 3. 5V 0. 2 3.0 100 3. 0V 0. 1 2. 6V 2.6 V 0 0 0 0. 1 0.2 0. 3 0. 4 0.5 0.6 0.7 0. 8 0.9 1 1.1 0 0. 5 1 1. 5 2 V MULT (V ) VM UL T (V ) Figure 30. Multiplier gain vs TJ 2. 5 3 3. 5 Figure 31. Gate drive clamp vs TJ     0. 5 12. 9 V CC = 20V 12.85 0. 4 Gai n (1/V ) 12. 8 V VCC = 12V VCOMP = 4V VMULT = VFF= 1V 12.75 0. 3 12. 7 0. 2 -50 -25 0 25 50 75 100 125 150 175 12.65 -50 Tj (C) Doc ID 16116 Rev 4 -25 0 25 50 75 Tj (C) 100 125 150 175 21/43 Typical electrical performance L6563S Figure 32. Gate drive output saturation vs TJ   Figure 33. Delay to output vs TJ 12 300 High level 10 250 TD(H-L) (n s) V 8 6 200 VCC = 12V 150 4 100 Low level 2 50 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tj (C) Figure 34. Start-up timer period vs TJ   450 After OCP 400 350 Ti m e (us) 300 250 Timer 200 150 100 First Cicle 50 0 -50 -25 0 25 50 75 100 125 150 175 Tj (C) 22/43 Doc ID 16116 Rev 4 -25 0 25 50 75 Tj (C) 100 125 150 175 L6563S Application information 6 Application information 6.1 Overvoltage protection Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 35). This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected. Example: VO = 400 V, VOX = 434 V. Select: R3 = 8.8 MΩ; then: R4 = 8.8 MΩ ·2.5/(434-2.5) = 51 kΩ. When this function is triggered, the gate drive activity is immediately stopped until the voltage on the pin PFC_OK drops below 2.4 V. Notice that R1, R2, R3 and R4 can be selected without any constraints. The unique criterion is that both dividers have to sink a current from the output bus which needs to be significantly higher than the bias current of both INV and PFC_OK pins. Figure 35. Output voltage setting, OVP and FFP functions: internal block diagram 6OUT 2A 2 2B   $ISABLE 6 6 0&#?/+ 2A 6 6 /60 ,?/60  2 6 2B  &REQUENCY #/-0 COMPENSATION   ).6 2 6  %RROR!MPLIFIER 2 !-V Doc ID 16116 Rev 4 23/43 Application information 6.2 L6563S Feedback failure protection (FFP) The OVP function above described handles “normal” over voltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. In case the overvoltage is generated by a feedback disconnection, for instance when the upper resistor of the output divider (R1) fails open, an additional comparator detects the voltage at pin INV. If the voltage is lower than 1.66 V and the OVP is active, the FFP is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 180 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. At the same time the pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver 2.8 V minimum with 0.25 mA load, intended for tripping a latched shutdown function of the PWM controller IC in the cascaded dc-dc converter, so that the entire unit is latched off. To restart the system it is necessary to recycle the input power, so that the Vcc voltage of both the L6563S goes below 6V and that one of the PWM controller goes below its UVLO threshold. The pin PFC_OK doubles its function as a not-latched IC disable: a voltage below 0.23V will shut down the IC, reducing its consumption below 2 mA. In this case both PWM_STOP and PWM_LATCH keep their high impedance status. To restart the IC simply let the voltage at the pin go above 0.27 V. Note that these functions offer a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down the IC and stopping the pre-regulator. 6.3 Voltage feedforward The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage Feedforward can compensate for the gain variation with the line voltage and allow minimizing all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 36). 24/43 Doc ID 16116 Rev 4 L6563S Application information Figure 36. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic  5HFWLILHGPDLQV FXUUHQW UHIHUHQFH 9FV[ ($RXWSXW 9 &203  9FV[  /+ /6 08/7,3/,(5  9 &203 9 LGHDOGLRGH 9   $FWXDO ,GHDO    9 08/7  0$,16'523 '(7(&725   9)) & ))  5 ))      9)) 908/7 !-V In this way a change of the line voltage will cause an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF); if it is too large there will be a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade-off was required. The L6563S realizes a NEW voltage feed forward that, with a technique that makes use of just two external parts, strongly minimizes this time constant trade-off issue whichever voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor RFF, both connected from the pin VFF (#5) to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (#3). In this way, in case of sudden line voltage rise, CFF will be rapidly charged through the low impedance of the internal diode; in case of line voltage drop, an internal “mains drop” detector enables a low impedance switch which suddenly discharges CFF avoiding long settling time before reaching the new voltage level. The discharge of CFF is stopped as its voltage equals the voltage on pin MULT or if the voltage on pin RUN (in case it is connected to VFF) falls below 0.88 V, to prevent the “Brownout protection” function from being improperly activated (see “Section 6.7 on page 31). As a result of the VFF pin functionality, an acceptably low steady-state ripple and low current distortion can be achieved with a limited undershoot or overshoot on the pre-regulator's output. Doc ID 16116 Rev 4 25/43 Application information L6563S The twice-mains-frequency (2•fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by: ΔVFF = 2 VMULTpk 1 + 4fLRFF CFF where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2•fL component, will be: 100 2π fLRFF CFF D3 % = Figure 37 shows a diagram that helps choose the time constant RFF·CFF based on the amount of maximum desired 3rd harmonic distortion. Note that there is a minimum value for the time constant RFF • CFF below which improper activation of the VFF fast discharge may occur. In fact, the twice-mains-frequency ripple across CFF under steady state conditions must be lower than the minimum line drop detection threshold (VVFF_min = 40 mV). Therefore: 2 RFF ⋅ CFF > VMULTpk _ max ΔVVFF _ min −1 4 fL _ min Always connect RFF and CFF to the pin, the IC will not work properly if the pin is either left floating or connected directly to ground. Figure 37. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current   10 1 f L= 50 Hz R FF · C FF [s] 0.1 0.01 0.1 f L= 60 Hz 1 D3 % 26/43 Doc ID 16116 Rev 4 10 L6563S 6.4 Application information THD optimizer circuit The L6563S is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (total harmonic distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this issue the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure 38 shows the internal block diagram of the THD optimizer circuit. Figure 38. THD optimizer circuit W W 9 9)) W  &203 08/7,3/,(5  08/7 W WR3:0 FRPSDUDWRU  2))6(7 *(1(5$725 W #9DF #9DF!9DF W !-V Doc ID 16116 Rev 4 27/43 Application information L6563S Figure 39. THD optimization: standard TM PFC controller (left side) and L6563S (right side)   Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current Imains Input current Vdrain MOSFET's drain voltage Vdrain MOSFET's drain voltage Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is modulated by the voltage on the VFF pin (see “Voltage Feedforward” section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in Figure 39, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness of the optimizer circuit. 6.5 Tracking boost function In some applications it may be advantageous to regulate the output voltage of the PFC preregulator so that it tracks the RMS input voltage rather than at a fixed value like in conventional boost pre-regulators. This is commonly referred to as “tracking boost” or “follower boost” approach. With the L6563S this can be realized by connecting a resistor (RT) between the TBO pin and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. The resistor defines a current, equal to 28/43 Doc ID 16116 Rev 4 L6563S Application information V(TBO)/RT, that is internally 1:1 mirrored and sunk from pin INV (#1) input of the L6563S's error amplifier. In this way, when the mains voltage increases the voltage at TBO pin will increase as well and so will do the current flowing through the resistor connected between TBO and GND. Then a larger current will be sunk by INV pin and the output voltage of the PFC pre-regulator will be forced to get higher. Obviously, the output voltage will move in the opposite direction if the input voltage decreases. To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the TBO pin is clamped at 3V. By properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. If this function is not used, leave the pin open: the device will regulate a fixed output voltage. Starting from the following data: ● Vin1 = minimum specified input RMS voltage; ● Vin2 = maximum specified input RMS voltage; ● Vo1 = regulated output voltage @ Vin = Vin1; ● Vo2 = regulated output voltage @ Vin = Vin2; ● Vox = absolute maximum limit for the regulated output voltage; to set the output voltage at the desired values use the following design procedure: 1. Determine the input RMS voltage Vinclamp that produces Vo = Vox: Vin clamp = Vox − Vo 2 Vox − Vo1 ⋅ Vin1 ⋅ Vin 2 − Vo 2 − Vo1 Vo 2 − Vo1 and choose a value Vinx such that Vin2 ≤ Vinx < Vinclamp. This will result in a limitation of the output voltage range below Vox (it will equal Vox if one chooses Vinx = Vinclamp) 2. Determine the divider ratio of the MULT pin (#3) bias: k= 3 2 ⋅ Vin x and check that at minimum mains voltage Vin1 the peak voltage on pin 3 is greater than 0.65 V. 3. Determine R1, the upper resistor of the output divider, for instance 3 MΩ. 4. Calculate the lower resistor R2 of the output divider and the adjustment resistor RT: Vin 2 − Vin1 ⎧ ⎪⎪R2 = 2.5 ⋅ R1⋅ (Vo − 2.5 ) ⋅ Vin − (Vo − 2.5 ) ⋅ Vin 1 2 2 1 ⎨ Vin 2 − Vin1 ⎪R T = 2 ⋅ k ⋅ R1⋅ ⎪⎩ Vo 2 − Vo1 5. Check that the maximum current sourced by the TBO pin (#6) does not exceed the maximum specified (0.2 mA): ITBO max = 3 ≤ 0.2 ⋅ 10 − 3 RT Figure 40 shows the internal block diagram of the tracking boost function. Doc ID 16116 Rev 4 29/43 Application information L6563S Figure 40. Tracking boost block 42!#+).' "//34  #522%.4 -)22/2 4"/ )4"/ #/-0   "5&&%2  FROM 6&& 6 24 ).6 )4"/  TO-ULTIPLIER  6 %RROR!MPLIFIER 6/54 2 2 !-V Figure 41. Tracking output voltage vs Input voltage characteristic with TBO   9R  9R [  9R  9LQ    9R     9LQ   9LQ  9LQ   9LQ [ !-V 6.6 Inductor saturation detection Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current upslope becomes so large (50-100 times steeper, see Figure 42) that during the current sense propagation delay the current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. However, in some applications such as ac-dc adapters, where the PFC pre-regulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may 30/43 Doc ID 16116 Rev 4 L6563S Application information occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e. when the output voltage is significantly below the rectified peak voltage. As a result, in the boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization. To cope with a saturated inductor, the L6563S is provided with a second comparator on the current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 1.1 V, exceeds 1.7 V. After that, the IC will be attempted to restart by the internal starter circuitry; the starter repetition time is twice the nominal value to guarantee lower stress for the inductor and boost diode. Hence, the system safety will be considerably increased. Figure 42. Effect of boost inductor saturation on the MOSFET current and detection method 6.7 Power management/housekeeping functions A special feature of this IC is that it facilitates the implementation of the “housekeeping” circuitry needed to co-ordinate the operation of the PFC stage to that of the cascaded DCDC converter. The functions realized by the housekeeping circuitry ensure that transient conditions like power-up or power down sequencing or failures of either power stage be properly handled. This device provides some pins to do that. One communication line between the IC and the PWM controller of the cascaded dc-dc converter is the pin PWM_LATCH (Figure 44b), which is normally open (high impedance) when the PFC works properly, and goes high if it loses control of the output voltage (because of a feedback loop disconnection) with the aim of latching off the PWM controller of the cascaded dc-dc converter as well (see “Feedback failure protection” section for more details). A second communication line can be established via the disable function included in the PFC_OK pin (see “Feedback failure protection” section for more details). Typically this line is used to allow the PWM controller of the cascaded dc-dc converter to drive in burst mode operation the L6563S in case of light load and to minimize the no-load input consumption. Interface circuits like those are shown in Figure 43. Doc ID 16116 Rev 4 31/43 Application information L6563S Figure 43. Interface circuits that let dc-dc converter's controller IC drive L6563S in burst mode  3)&B2.  /$ /+ /6  3)&B6723 581 3)&B2. /    /+ /6  3)&B6723 581   !-V The third communication line is the pin PWM_STOP (#9), which works in conjunction with the pin RUN (#10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the cascaded dc-dc converter. The pin is an open collector, normally open, that goes low if the device is disabled by a voltage lower than 0.8 V on the RUN pin. The pin goes again open if the voltage on pin RUN exceeds 0.88V. It is important to point out that this function works correctly in systems where the PFC stage is the master and the cascaded dc-dc converter is the slave or, in other words, where the PFC stage starts first, powers both controllers and enables/disables the operation of the dc-dc stage. The pin RUN can be used to start and stop the main converter. In the simplest case, to enable/disable the PWM controller the pin PWM_STOP can be connected to the output of the error amplifier (Figure 44a). Figure 44. Interface circuits that let the L6563S switch on or off a PWM controller  21 581     /+ /6 3:0B6723 /+ /6  3:0B/$7&+ 2)) 8&[; 8&[; /$; /; /$;     RU ; 3:05(6 FRQWUROOHU /$;  /;  /$;  DQRWODWFKHG ; 3:05(6 FRQWUROOHU EODWFKHG !-V If the chip is provided with a soft-start pin, it is possible to delay the start-up of the dc-dc stage with respect to that of the PFC stage, which is often desired, as described in Figure 45. An underlying assumption in order for that to work properly is that the UVLO thresholds of the PWM controller are certainly higher than those of the L6563S. 32/43 Doc ID 16116 Rev 4 L6563S Application information Figure 45. Interface circuits for power up sequencing when dc-dc has the SS function  21 581   /+ /6   3:0B6723 2)) /$;  /;  /$;  ; 66 3:05(6 FRQWUROOHU &66 !-V If this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents the dc-dc stage from starting up correctly) or, simply, the PWM controller is devoid of soft start, the arrangement of Figure 46 lets the dc-dc converter start-up when the voltage generated by the PFC stage reaches a preset value. The technique relies on the UVLO thresholds of the PWM controller. Figure 46. Interface circuits for actual power-up sequencing (master PFC) +9EXV  6XSSO\UDLO %& /$ ; 8&[; 8&[; / ; /; N7 9FF   21 581 2)) 3:0B6723   %&& 9=      ;   3:0 FRQWUROOHU /+ /6 3)&B2.  9FFB2II 9=9FFPD[ !-V Another possible use of the RUN and PWM_STOP pins (again, in systems where the PFC stage is the master) is the brownout protection, thanks to the hysteresis provided. The brownout protection is basically a not-latched device shutdown function that is activated when a condition of mains undervoltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shutdown the unit in case of brownout. IC shutdown upon brownout can be easily realized as shown in Figure 47. The scheme on the left is of general use, that one on the right can be used if the bias levels of the multiplier and the RFF·CFF time constant are compatible with the specified brownout level and with the specified holdup time respectively. In this latest case, an additional resistor voltage divider and one capacitor are not needed. Doc ID 16116 Rev 4 33/43 Application information L6563S In table 1 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. Figure 47. Brownout protection (master PFC) Table 5. Summary of L6563S idle states Typical IC PWM_LATCH PWM_STOP Condition Caused or revealed bey IC behavior Restart condition consumption Status Status UVLO Vcc < VccOff Disabled Vcc > VccOn 90 µA Off High Feedback disconnected PFC_OK > VPFC_OK_S AND INV < 1.66V Latched Vcc < Vccrestart then Vcc > VccOn 180 µA High High Standby PFC_OK < VPFC_OK_D PFC_OK > VPFC_OK_E 1.5 mA Off High AC brownout RUN < VDIS RUN > VEN 1.5 mA Off Low OVP PFC_OK > VPFC_OK_S PFC_OK < VPFC_OK_R 2.2 mA Off High Low consumption COMP < 2.4V Burst mode COMP > 2.4V 2.2 mA Off High Saturated boost inductor Vcs > VCS_th Doubled Tstart Auto restart 2.2 mA Off High 34/43 Stop switching Doc ID 16116 Rev 4 L6563S Application examples and ideas 7 Application examples and ideas Figure 48. Demonstration board EVL6563S-100W, wide-range mains: electrical schematic ' 1 a  / 65: 34;;;9 ' *%8- / +) < 57   ) )8 6($ - 0.'6   & 1  B a 9DF  & 1 9 & 1 5 17& 56   ' 677+/  & 1 5 5  & X) 9 ' // - 0.'6  5 0 5 0 ' %=;& 5 0 5 . 5 0 5 . 5 0 5 0 5 . 5 . 5 0 5 . 5 0 5 . 5 . & 1 5 0 8    & 1 & 1 /6 & 1 5 .    & X)  5 . ,1 9 &203 08/7 9&& *' *1' &6 =& ' 9)) 58 1 7%2 3:06723 3)& 2. 3:0/$7&+ & X)9  4 67)101   +6 +($76,1 . 5 5 5 .  5 5   5 5 & 1 5 5  -3 %$5(& 233(5:,5 (-8 03(5 & S & 1 5 5 5 . 5 0 5 . 5 . Doc ID 16116 Rev 4 - &21  9&&  *1'  3:0B6723  3:0B/$7&+  212)) 35/43 Application examples and ideas L6563S Figure 49. L6563S 100 W TM PFC demonstration board: compliance to EN61000-3-2 standard   Meas ured value Figure 50. L6563S 100 W TM PFC demonstration board: compliance to JEITA-MITI standard EN61000-3- 2 class- D lim its Measur ed value JEITA-MITI Class-Dlim its 10 Harmonic Current [A] Harmonic Current [A] 1 0.1 0.01 0.001 1 0.1 0.01 0.001 0.0001 0.0001 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Harmonic Order [n] Harmonic Order [n] Figure 51. L6563S 100 W TM PFC Figure 52. L6563S 100W TM PFC demonstration board: input current demonstration board: input current waveform @230-50 Hz - 100 W load waveform @100 V-50 Hz - 100 W load 36/43 Doc ID 16116 Rev 4 L6563S Application examples and ideas Figure 53. EVL6563S-250W TM PFC demonstration board: electrical schematic D2 1N5406 D1 D10XB60H L1 2 ~ 1 J1 2 1 90-264Vac 3 1 5 7 8 C6 10N J2 D3 STTH5L06 C5 100uF - 450V D4 LL4148 R2 47R D5 BZX55-C18 R5 150K +400Vout R3 1M0 JPX2 +400Vdc +400Vdc NC RTN RTN 1 2 3 4 5 JPX6 RX3 47R LH30-792Y3R0-01 C2 1uF-X2 Z1 R4 2M2 C4 1.5uF-520V _ ~ 3 4 C1 470N-X2 R1 NTC 1R0-S237 L2 180uH + F1 FUSE 4A R6 1M0 JPX7 R7 1M0 PCB REV. 1 R10 27K R9 62K R11 150K R13 100K 1 VCC INV R16 6R8 R14 100K 470N 2 C8 14 RX4 2 C11 2N2 R15 51K C14 220pF C12 1uF GD 13 MULT GND 12 CS ZCD 11 COMP R17 R18 3R9 6R8 0R0 3 4 5 VFF RUN 6 TBO PWM-STOP 9 7 PFC-OK PWM-LATCH 8 Q1 STF12NM50N D6 LL4148 JPX1 D7 LL4148 Q2 JPX5 1 1 R19 3R9 3 U1 L6563S C10 680N 2 C7 68N RX1 0R0 STF12NM50N R12 2M2 3 R8 2M2 R21 3M3 HS1 HEAT-SINK 10 JPX8 R20 220R C13 2N2 R23 0R22 R25 3M3 R24 0R22 JPX3 JPX4 R26 2M2 C15 2N2 R27 56K JP2 WIRE JUMPER R33 51K R29 10R R28 1M0 C9 68uF-35V R30 1K0 R31 1K0 R32 100R 1 VCC 2 GND 3 PWM_STOP 4 PWM_LATCH 5 ON/OFF J3 CON5 JPX10 Figure 54. EVL6563S-400W FOT PFC demonstration board: electrical schematic JP101 JUMPER 1 1 L2 RES L1 L3 DM-51uH-6A D2 D15XB60 CM-1.5mH-5A F1 J1 D1 2 ~ 5-6 R1 C1 C2 C3 1M5 470nF-X2 470nF-X2 680nF-X2 1 2 C8 RES R2 J2 8 C4 C5 470nF-630V 470nF-630V STTH8R06 11 NTC 2R5-S237 C6 470nF-630V - ~ 90 - 265Vac D3 + 8A/250V 2 +400Vdc 1N5406 L4 PQ40-500uH 1-2 C7 330uF-450V 1 2 3 4 5 +400Vdc +400Vdc NC RTN RTN +400Vout C9 RES JP102 JUMPER R3 150K +400Vdc R5 47R R10 R9 680k 680k R4 150K R102 C10 18N R6 0R0 D4 LL4148 2M2 R11 R7 680k 2M2 R8 R12 C13 100nF 2M2 R24 36K C12 470nF/50V 68uF/50V D5 BZX85-C15 15k 82K R14 56k C14 1uF C11 R13 U1 L6563S 1 INV VCC 14 2 COMP GD 13 3 MULT GND 12 4 CS ZCD 11 5 VFF RUN 10 6 TBO 7 PFC-OK PWM-STOP 9 PWM-LATCH 8 C17 10nF LL4148 D6 C15 100pF D7 LL4148 R36 3R9 R28 RES R29 RES C101 4N7 R15 3K3 J3 C16 220pF 1 2 3 RES R17 6R8 R16 15K Q1 STP12NM50FP R35 3R9 D8 LL4148 R31 1k5 R30 RES Q2 STP12NM50FP R18 6R8 R26 R19 56k C18 R27 C19 1uF 1M0 2nF2 1K0 C20 330pF R32 R33 620k 620k R20 0R39-1W R21 0R39-1W R22 0R39-1W R23 0R39-1W Q3 BC857C R34 C21 10k 10nF R101 0R0 Doc ID 16116 Rev 4 37/43 MKDS 1,5/3-5.08 CN1 Doc ID 16116 Rev 4 10n C4 HT 6.3A 250V F1 16k R5 1M0 R4 1M0 R23 56k 1uF 100k C11 330pF 47n 470n R11 C9 C10 C8 2n2 1M0 CY2 2n2 R9 RX2 1M8 CY1 R3 330nF CX1 RX1 1M8 7 6 5 4 3 2 1 15mH L1 PFC-OK TBO VFF CS MULT COMP INV U1 CX2 330nF L6563S RUN ZCD GND GD VCC PWM-LATCH PWM-STOP HS1 ~ BD1 8 9 10 11 12 13 14 D15XB60 ~ 38/43 1 2 3 220R R12 100n 47uF-25V 2n2 C13 56k R10 D4 LL4148 10R C6 R13 120k R24 120k R7 120k R6 C1 1uF5-630V C2 220nF-630V C5 _ + 90-264Vac C7 3n3 LL4148 D3 33R 10k R14 R2 0R22 R1 HS2 STF12NM50N Q1 2R5 10A C3 150uF-450V RT1 D2 STTH5L06 0R27 20V ZD1 10 3 12 260uH ZRC-IND L2 R8 14 1 8 D1 1N5406 22n C12 15k R18 390k R17 1M0 R16 1M0 R15 R19 36k R22 1M8 R21 2M2 R20 2M2 CN2 MKDS 1,5/2-5.08 1 2 Application examples and ideas L6563S Figure 55. EVL6563S-ZRC200W 200W PFC pre-regulator with ripple-free input current: electrical schematic L6563S 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 6. SO14 mechanical data mm. Dim. Min Typ Max A 1.350 1.750 A1 0.100 0.250 A2 1.100 1.650 B 0.330 0.510 C 0.190 0.250 D 8.550 8.750 E 3.800 4.000 e 1.270 H 5.800 6.200 h 0.250 0.500 L 0.400 1.270 k 0d 8d ddd 0.100 Doc ID 16116 Rev 4 39/43 Package mechanical data L6563S Figure 56. Package dimensions 40/43 Doc ID 16116 Rev 4 L6563S 9 Ordering codes Ordering codes Table 7. Ordering information Order codes Package L6563S Packing Tube SO14 L6563STR Tape and reel Doc ID 16116 Rev 4 41/43 Revision history 10 L6563S Revision history Table 8. 42/43 Document revision history Date Revision Changes 12-Aug-2009 1 Initial release. 03-Sep-2009 2 Updated mechanical data. 29-Jan-2010 3 Updated Table 4 on page 11. 21-Dec-2010 4 Updated Figure 1 on page 1, Figure 24 on page 20, Table 3 on page 8, Table 4 on page 11, Table 5 on page 34 and Section 6.2 on page 24. Doc ID 16116 Rev 4 L6563S Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 16116 Rev 4 43/43