L6591
PWM controller for ZVS half bridge
Datasheet − production data
Features
■
Complementary PWM control for soft-switched
half bridge with programmable deadtime
■
Up to 500 kHz operating frequency
■
Onboard high-voltage startup
■
Advanced light load management
■
Adaptive UVLO
■
Pulse-by-pulse OCP
■
OLP (latched or autorestart)
■
Transformer saturation detection
■
Interface with PFC controller
Applications
■
Latched disable input
■
High power AC-DC adapter/charger
■
Input for power-on sequencing or brownout
protection
■
Desktop PC, entry-level server
■
Telecom SMPS
SO16 narrow
■
Programmable soft-start
Figure 1.
Block diagram
HV
4% precision external reference
■
600 V-rail compatible high-side gate driver with
integrated bootstrap diode and high dV/dt
immunity
■
SO16N package
V CC
9
16
5
SO 16
■
CLK
OSC
TIMING
25 V
Vre f
HV ge nerator ON/O FFa nd
a daptive UV LOmanag ement
VREG
6
VREF
Vcc_OK
2
Low
UVLO
R
DIS
+
S
Sync hronou s
bo otstra p diode
Q
-
4.5V
DIS
15
BOOT
-
HICCUP
S
BLANKI NG
Q
P WM _CT L
+
ISEN
R
3
+
PWM
-
Vc c_O K
DIS
S HUT DO WN
R
PFC_STOP
Q
S
8
OCP2
LI NE_ OK
OCP2
DI S
VREG
BURST- M ODE CTRL
Ilimre f
0 .8 V max.
1.25V
-
1
LINE
LI NE_OK
1 5µA
HVG
13
FGND
V CC
10
LV G
1.7 5V
-
+
14
L EVEL
SHIFTER
0.3 2mA
+
+
OCP
-
Dead time adjustment
& logic
1.5V
L ow
UV LO
11
GND
3R
SOFT-START
+
R
2.0 V
4
7
SS
August 2012
This is information on a product in full production.
COMP
Doc ID 14821 Rev 6
1/41
www.st.com
41
Contents
L6591
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
2.1
Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
High-voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2
Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3
PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4
PWM comparator, PWM latch and hiccup mode OCP . . . . . . . . . . . . . . . 26
6.5
Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6
Oscillator and deadtime programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7
Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.8
Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.9
Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 32
7
Summary of L6591 power management functions . . . . . . . . . . . . . . . 34
8
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2/41
Doc ID 14821 Rev 6
L6591
1
Description
Description
The L6591 is a double-ended PWM controller specific to the soft-switched half bridge
topology. It provides complementary PWM control, where the high-side switch is driven ON
for a duty cycle D and the low-side switch for a duty cycle 1-D, with D < 50%. An externally
programmable deadtime inserted between the turn-off of one switch and the turn-on of the
other one guarantees soft-switching and enables high-frequency operation.
To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage
floating structure able to withstand more than 600 V with a synchronous-driven high-voltage
DMOS that replaces the external fast-recovery bootstrap diode.
The IC enables the user to set the operating frequency of the converter by means of an
externally programmable oscillator: the maximum duty cycle is digitally clipped at 50% by a
T-flip-flop, so that the operating frequency is half that of the oscillator.
At very light load the IC enters a controlled burst mode operation that, along with the built-in
non-dissipative high-voltage startup circuit and the low quiescent current, helps keep the
consumption from the mains low and is compliant with energy saving recommendations.
To allow compliance with these standards also in two-stage power-factor-corrected systems,
an interface with the PFC controller is provided that enables the pre-regulator to be switched
off between one burst and the following one.
An innovative adaptive UVLO helps minimize the issues related to fluctuations of the selfsupply voltage with the output load, due to the transformer's parasitic.
IC protection functions include: not-latched input undervoltage (brownout), a first-level OCP
with delayed shutdown able to protect the system during overload and short-circuit
conditions (either auto-restart or latch mode can be selected) and a second-level OCP that
latches off the IC when the transformer saturates or one of the secondary diodes fails short.
Finally, a latched disable function allows easy implementation of OTP or OVP.
Programmable soft-start and digital leading-edge blanking on the current sense input pin
complete the equipment of the IC.
Figure 2.
Typical system block diagram
PF C P RE-REGULATO R
ZVS HAL F-BRIDG E
Voutd c
Vinac
PW M is turned off in case of PFC's
anomalous operation, for safety
L6561/2
or
L6563
L6591
PFC can be turn ed off at light
load to ease compliance with
energy saving r egulatio ns.
AM13253v1
Doc ID 14821 Rev 6
3/41
Pin settings
L6591
2
Pin settings
2.1
Connection
Figure 3.
Pin connection (top view)
LINE
1
16
HVSTART
DIS
2
15
BOOT
ISEN
3
14
HVG
SS
4
13
FGND
OSC
5
12
N.C.
VREF
6
11
GND
COMP
7
10
LVG
PFC_STOP
8
9
Vcc
AM13254v1
2.2
Functions
Table 1.
Pin N.
1
2
4/41
Pin functions
Name
Function
LINE
Line sensing input. The pin is to be connected to the high-voltage input bus
with a resistor divider. A voltage below 1.25 V shuts down the IC, lowers its
consumption and discharges the soft-start capacitor. IC operation is reenabled as the voltage exceeds 1.25 V. The comparator is provided with
current hysteresis: an internal 15 µA current generator is ON as long as the
voltage applied at the pin is below 1.25 V, and is OFF if this value is
exceeded. Bypass the pin with a capacitor to GND (#11) to reduce noise
pick-up. The pin is intended for either power-on sequencing in systems with
PFC, or brownout protection. Tie to Vcc (#9) with a 220 to 330 kΩ resistor if
the function is not used.
DIS
Latched device shutdown. Internally, the pin connects a comparator that,
when the voltage on the pin exceeds 4.5 V, shuts the IC down and brings its
consumption to a value barely higher than before startup. The information is
latched and it is necessary to recycle the input power to restart the IC: the
latch is removed as the voltage on the Vcc pin (#9) goes below the UVLO
threshold. Connect the pin to GND (#11) if the function is not used.
Doc ID 14821 Rev 6
L6591
Pin settings
Table 1.
Pin N.
3
4
5
6
7
8
Pin functions (continued)
Name
Function
ISEN
Current sense (PWM comparator) input. The voltage on this pin is internally
compared with an internal reference derived from the voltage on the COMP
pin and, when they are equal, the high-side gate drive output (previously
asserted high by the clock signal generated by the oscillator) is driven low to
turn off the upper Power MOSFET; the lower MOSFET is turned on after a
delay programmed by the timing capacitor at the OSC pin (#5). The pin is
equipped with 200 ns blanking time for improved noise immunity. A second
comparator, referenced at 0.8 V, turns off the upper MOSFET if the voltage
at the pin exceeds the threshold, overriding the PWM comparator (pulse-bypulse OCP). A third comparison level located at 1.5 V shuts the device
down and brings its consumption almost to a “before startup” level (hiccup
mode OCP) to prevent uncontrolled current rise. A logic circuit improves
sensitivity to temporary disturbances.
SS
Soft-start. An internal 20 µA generator charges an external capacitor
connected between the pin and GND (#11) generating a voltage ramp.
During the ramp, the internal reference for pulse-by-pulse OCP (see pin #3,
ISEN) rises linearly starting from zero to its final value, therefore causing
the duty cycle of the upper MOSFET to rise starting from zero as well, and
all the functions monitoring the COMP pin (#7) are disabled. The same
capacitor is used to delay IC shutdown (latch-off or auto-restart mode
selectable) after detecting an overcurrent condition. The SS capacitor is
quickly discharged as the chip goes into UVLO.
OSC
Oscillator pin. A resistor to VREF (#6) and a capacitor from the pin to GND
(#11) define the oscillator frequency. The maximum duty cycle is limited
below 50% by an internal T-flip-flop. As a result, the switching frequency is
half that of the oscillator. The capacitor value defines the deadtime
separating the conduction state of either MOSFET. This capacitor should
not be lower than 220 pF.
VREF
Voltage reference. An internal generator furnishes an accurate voltage
reference (5 V±4%, all inclusive) that can be used to supply up to 5 mA to
an external circuit. A small film capacitor (0.1 µF typ.), connected between
this pin and GND (#11) is recommended to ensure the stability of the
generator and to prevent noise from affecting the reference.
COMP
Control input for PWM regulation. The pin is to be driven by the
phototransistor (emitter-grounded) of an octocoupler to modulate the
voltage by modulating the current sunk from (sourced by) the pin (0.4 mA
typ.). It is recommended to place a small filter capacitor between the pin
and GND (#11), as close to the IC as possible, to reduce switching noise
pick-up, and to set a pole in the output-to-control transfer function. A voltage
lower than 1.75 V shuts down the IC and reduces its current consumption.
The chip restarts as the voltage exceeds 1.8 V. This function realizes burst
mode operation at light load.
Open-drain ON/OFF control of PFC controller. This pin is intended for
temporarily stopping the PFC controller at light load in systems comprising
a PFC pre-regulator, during burst mode operation (see pin COMP, #7). The
pin, normally open, goes low if the voltage on COMP is lower than 1.75 V
PFC_STOP
and opens when the voltage on the COMP pin exceeds 1.8 V. Whenever the
IC is shut down (SS > 5 V, DIS > 4.5, ISEN > 1.5 V) the pin is low as well,
provided the supply voltage of the IC is above the restart threshold
(typ. 5 V). It is open during UVLO. Leave the pin open if not used.
Doc ID 14821 Rev 6
5/41
Pin settings
L6591
Table 1.
Pin N.
Name
Function
9
Vcc
Supply voltage of both the signal part of the IC and the low-side gate driver.
The internal high-voltage generator charges an electrolytic capacitor
connected between this pin and GND (#11) as long as the voltage on the
pin is below the startup threshold of the IC, after that, it is disabled and the
chip turns on. Sometimes a small bypass capacitor (0.1 µF typ.) to GND
may be useful to get a clean bias voltage for the signal part of the IC. The
minimum operating voltage (UVLO) is adapted to the loading conditions of
the converter to ease burst mode operation, during which the available
supply voltage for the IC drops.
10
LVG
Low-side gate-drive output. The driver is capable of 0.3 A min. source and
0.8 A min. sink peak current to drive the gate of the lower MOSFET of the
half bridge leg. The pin is actively pulled to GND (#11) during UVLO.
11
GND
Chip ground. Current return for both the low-side gate-drive current and the
bias current of the IC. All of the ground connections of the bias components
should be tied to a track going to this pin and kept separate from any pulsed
current return.
12
N.C.
High-voltage spacer. The pin is not connected internally to isolate the group
of high-voltage pins and comply with safety regulations (creepage distance)
on the PCB.
13
FGND
High-side gate-drive floating ground. Current return for the high-side gatedrive current. Layout carefully the connection of this pin to avoid too large
spikes below ground.
HVG
High-side floating gate-drive output. The driver is capable of 0.3 A min.
source and 0.8 A min. sink peak current to drive the gate of the upper
MOSFET of the half bridge leg. A pull-down resistor between this pin and
pin 13 (FGND) makes sure that the gate is never floating during UVLO.
BOOT
High-side gate-drive floating supply voltage. The bootstrap capacitor
connected between this pin and pin 13 (FGND) is fed by an internal
synchronous bootstrap diode driven in-phase with the low-side gate-drive.
This patented structure can replace the normally used external diode.
HVSTART
High-voltage startup. The pin is to be connected directly to the rectified
mains voltage. A 0.8 mA internal current source charges the capacitor
connected between pin Vcc (#9) and GND (#11) until the voltage on the Vcc
pin reaches the startup threshold. Normally it is re-enabled when the
voltage on the Vcc pin falls below 5 V, except under latched shutdown
conditions, in which case it is re-enabled as the Vcc voltage falls 1 V below
the startup threshold to keep the latch active.
14
15
16
6/41
Pin functions (continued)
Doc ID 14821 Rev 6
L6591
Electrical data
3
Electrical data
3.1
Maximum ratings
Table 2.
Absolute maximum ratings
Symbol
Pin
VHVSTART
16
IHVS
Value
Unit
Voltage range (referred to ground)
-0.3 to 700
V
16
Input current
Self-limited
A
VBOOT
15
Floating supply voltage
-1 to 618
V
VFGND
13
Floating ground voltage
-3 to VBOOT -18
V
dVFGND/dt
13
Floating ground slew rate
50
V/ns
VCC
9
IC supply voltage (Icc = 20 mA)
Self-limited
V
IHVG, ILVG
10, 14
Gate drive peak current
Self-limited
A
IPFC_STOP
8
Max. sink current (VPFC_STOP = 25 V)
Self-limited
A
VLINEmax
1
Maximum pin voltage (Ipin ≤1 mA)
Self-limited
V
-
2 to 7
-0.3 to 7
V
ISEN
3
-3 to 7
V
0.75
W
Junction temperature operating range
-40 to 150
°C
Storage temperature
-55 to 150
°C
PTOT
Analog inputs and outputs
Current sense input
Power dissipation @ TA = 50 °C
TJ
TSTG
3.2
Parameter
Thermal data
Table 3.
Symbol
RthJA
Thermal data
Parameter
Thermal resistance junction-to-ambient (1)
Value
Unit
120
°C/W
1. Value depending on PCB copper area and thickness.
Doc ID 14821 Rev 6
7/41
Electrical characteristics
4
L6591
Electrical characteristics
TJ = 0 to 105 °C, Vcc = 15 V, VBOOT = 12 V, CHVG = CLVG = 1 nF; RT = 22 kΩ, CT = 330 pF;
unless otherwise specified.
Table 4.
Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
IC supply voltage
Vcc
VccOn
VccOff
Operating range after
turn-on
VCOMP > VCOMPL
11.3
22
VCOMP = VCOMPL
9.2
22
Turn-on threshold
(1)
13
14
15
VCOMPL
9.7
10.5
11.3
= VCOMPL
8.2
8.7
9.2
(1) V
COMP >
Turn-off threshold
(1) V
COMP
V
V
V
Hys
Hysteresis
VCOMP > VCOMPL
3.0
3.5
VZ
Vcc clamp voltage
Icc = 15 mA
22
25
28
V
V
Supply current
Startup current
Before turn-on,
Vcc = 12.5 V
190
250
µA
Iq
Quiescent current
After turn-on
2.8
3.5
mA
Icc
Operating supply current
5.3
8
mA
VDIS > 4.5 V,
VISEN > 1.5 V
0.35
mA
VCOMP = 1.64 V
2.2
mA
VLINE < 1.25 V
0.35
mA
17
V
800
µA
10
µA
Istartup
Iqdis
Shutdown quiescent
current
High-side floating gate-drive supply
VBOOT
Operating supply voltage
Referred to FGND pin
IqBOOT
Quiescent current
VFGND = 0
High-voltage leakage
VFGND = VBOOT =
VHVG = 600 V
Synchronous bootstrap
diode on-resistance
VLVG = HIGH
ILK
RDS(on)
500
Ω
125
High-voltage startup generator
VHV
VHVstart
Icharge
8/41
Breakdown voltage
IHV < 100 µA
700
Start voltage
IVcc < 100 µA
60
75
90
V
Vcc charge current
VHV > VHvstart,
Vcc > 3 V
0.55
0.75
1
mA
Doc ID 14821 Rev 6
V
L6591
Electrical characteristics
Table 4.
Electrical characteristics (continued)
Symbol
IHV, ON
IHV, OFF
Parameter
Test condition
ON-state current
Min.
Typ.
VHV > VHvstart,
Vcc > 3 V
1.6
VHV > VHvstart, Vcc = 0
0.8
(1)
(1)
After DIS tripping
Unit
mA
Leakage current (OFF-state) VHV = 400 V
VCCrestart HV generator restart voltage
Max.
40
µA
4.4
5
5.6
V
12.2
13.2
14.2
V
5
5.1
V
Reference voltage
(1)
VREF
Output voltage
TJ = 25 °C;
IREF = 1 mA
4.9
VREF
Total variation
Vcc= 9.2 to 22 V,
IREF = 1 to 5 mA
4.8
5.2
V
IREF
Short-circuit current
VREF = 0
10
30
mA
Sink capability in UVLO
Vcc = 6 V;
Isink = 0.5 mA
0.5
V
-1
µA
0.2
Current sense comparator
IISEN
Input bias current
VISEN = 0
tLEB
Leading edge blanking
After VHVG low-to-high
transition
td(H-L)
Delay to output
Gain
VISENx
200
VISENdis Hiccup mode OCP level
170
ns
3.8
4
4.2
V/V
0.76
0.8
0.84
V
(1)
1.4
1.5
1.65
V
ICOMP = 0
5.5
210
(1) V
COMP
Maximum signal
ns
=5V
PWM control and burst mode control
VCOMPH Maximum level
ICOMP
Source current
VCOMP = 2 V
RCOMP
Dynamic resistance
VCOMP = 2 to 4 V
VCOMPBon Burst mode on threshold
(1)
VCOMP falling
V
300
400
25
1.68
Hys
Burst mode hysteresis
VCOMP rising
Dmax
Maximum duty cycle
VCOMP = 5 V
46
(1)
1.9
1.75
µA
kΩ
1.82
70
V
mV
50
%
2
2.1
V
Adaptive UVLO
VCOMPL
UVLO shift threshold
Line sensing
Vth
Threshold voltage
Voltage rising or falling
1.22
1.25
1.28
V
IHys
Current hysteresis
Vcc > 5 V
13.2
14.7
16.2
µA
Clamp level
ILINE = 1 mA
2.8
3
Vclamp
Doc ID 14821 Rev 6
V
9/41
Electrical characteristics
Table 4.
L6591
Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
-1
µA
DIS function
IOTP
Input bias current
Vth
Disable threshold
VDIS = 0 to Vth
4.275
4.5
4.725
V
TJ = 25 °C
170
180
190
kHz
Vcc = 9.2 to 22 V
168
180
192
kHz
Oscillator peak voltage
(1)
2.85
3
3.15
V
Oscillator valley voltage
(1)
0.75
0.9
1.05
V
Oscillator and deadtime programming
fosc
Vpk
Vvy
Oscillation frequency
Deadtime
(VHVG high-to-low to VLVG
low-to-high transition)
Tdead
0.42
CT = 1 nF
1.0
µs
Deadtime (VLVG high-to-low
to VHVG low-to-high
transition)
0.42
CT = 1 nF
1.0
Soft-start
ISSC
ISsdis
Charge current
Discharge current
VSsclamp High saturation voltage
TJ = 25 °C, VSS < 1.5 V,
VCOMP = 4 V
14
18
22
TJ = 25 °C, VSS > 1.5 V,
VCOMP = VCOMPH
3.4
4.7
5.6
VSS > 1.5 V
3.4
4.7
5.6
µA
VCOMP = 4 V
VSSDIS
Disable level
(2)
VSSLAT
Latch-off level
VCOMP = VCOMPH
VCOMP = VCOMPH
2
4.85
5
µA
V
5.15
6.4
V
V
PFC_STOP function
Ileak
VL
High level leakage current
VPFC_STOP = Vcc,
VCOMP = 2 V
1
µA
Low saturation level
IPFC_STOP = 2 mA
VCOMP = 1.5 V
0.1
V
1.0
V
Low-side gate driver (voltages referred to GND)
VLVGL
Output low-voltage
VLVGH
Output high-voltage
Isourcepk Peak source current
Isinkpk
10/41
Peak sink current
Isink = 200 mA
Isource = 5 mA
(2)
(2)
Doc ID 14821 Rev 6
12.8
13.3
V
-0.3
A
0.8
A
L6591
Electrical characteristics
Table 4.
Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tf
Fall time
40
ns
tr
Rise time
80
ns
Vcc = 0 to VccOn,
Isink = 1 mA
UVLO saturation
1.1
V
1.5
V
High-side gate driver (voltages referred to FGND)
VHVGL
Output low-voltage
Isink = 200 mA
VHVGH
Output high-voltage
Isource = 5 mA
Isourcepk Peak source current (2)
Isinkpk
Peak sink current
(2)
11
11.9
V
-0.3
A
0.8
A
tf
Fall time
40
ns
tr
Rise time
80
ns
Pull-down resistor
25
kΩ
1. Parameters tracking each other.
2. Parameters guaranteed by design.
Doc ID 14821 Rev 6
11/41
Typical characteristics
L6591
5
Typical characteristics
Figure 4.
High-voltage generator ON-state
sink current vs. Tj
Figure 5.
ϭ͘Ϯ
High-voltage generator output
(Vcc charge current) vs. Tj
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ϴϱй
Ϭ
ϴϬй
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
ͲϱϬ
Ϭ
dũΣ
ϱϬ
ϭϬϬ
".W
Figure 6.
ϭϱϬ
dũΣ
High-voltage generator start
voltage vs. Tj
".W
Figure 7.
High-voltage generator Vcc restart
voltage vs. Tj
ϭϰ
ϭϭϬй
ϭϮ
ϭϬϱй
ϭϬ
s ƌĞƐƚĂƌƚ s
s,sƐƚĂƌƚй
ĂĨƚĞƌ/^ƚƌŝƉƉŝŶŐ
ϭϬϬй
ϴ
ŶŽƌŵĂůŽƉĞƌĂƚŝŽŶ
ϲ
ϰ
ϵϱй
Ϯ
Ϭ
ϵϬй
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
ͲϱϬ
dũΣ
ϱϬ
ϭϬϬ
ϭϱϬ
dũΣ
".W
12/41
Ϭ
Doc ID 14821 Rev 6
".W
L6591
Typical characteristics
Figure 8.
IC consumption during normal
operation vs. Tj
Figure 9.
IC consumption under protection
and before turn-on vs. Tj
Ϭ͘ϯϱ
ϲ
Ϭ͘ϯ
ϱ
KƉĞƌĂƚŝŶŐ
Ϭ͘Ϯϱ
YƵŝĞƐĐĞŶƚ
ϰ
/ĐĐŵ
/ĐĐŵ
ƵƌƐƚŵŽĚĞ
ϯ
Ϭ͘Ϯ
Ϭ͘ϭϱ
>/E фϭ͘ϰϰs
Ϯ
/^хϰ͘ϱs
Ϭ͘ϭ
/^ Eхϭ͘ϱs
ϭ
ĞĨŽƌĞƚƵƌŶŽŶ;sĐĐсϭϮ͘ϱsͿ
Ϭ͘Ϭϱ
Ϭ
Ϭ
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ͲϱϬ
ϭϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
dũΣ
dũΣ
".W
Figure 10. Startup & UVLO vs. Tj
".W
Figure 11. Vcc Zener voltage vs. Tj
ϭϲ
ϯϬ
ϭϰ
Ϯϱ
ϭϮ
sKDW хsKDW>
ϮϬ
ϴ
ss
ss
ϭϬ
sKDW сsKDW>
ϭϱ
/ĐĐсϭϱŵ
sĐĐͺŽŶ
ϲ
sĐĐͺŽĨĨ
ϰ
ϭϬ
sĐĐͺŽĨĨͺůŽǁ
ϱ
Ϯ
Ϭ
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
Ϭ
ͲϱϬ
dũΣ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
dũΣ
".W
Doc ID 14821 Rev 6
".W
13/41
Typical characteristics
L6591
Figure 12. COMP voltage upper clamp level vs. Figure 13. COMP source current vs. Tj
Tj
ϭϮϬй
ϳ
ϭϬϬй
ϲ͘ϱ
/KDWй
sKDWs
ϴϬй
ϲ
ϲϬй
sKDW сϮs
/KDW сϬ
ϰϬй
ϱ͘ϱ
ϮϬй
sĂůƵĞƐŶŽƌŵĂůŝnjĞĚƚŽ/KDW ΛϮϱΣ
Ϭй
ϱ
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ͲϱϬ
ϭϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
dũΣ
dũΣ
".W
Figure 14. COMP dynamic resistance vs. Tj
".W
Figure 15. Oscillator frequency vs. Tj
Ϯϴ͘ϱ
ϭϬϭ͘Ϭй
Ϯϴ
s сϭϱs
Ϯϳ͘ϱ
ϭϬϬ͘ϱй
Ϯϲ͘ϱ
ĨK^й
ZKDWs's
Ϯ͘ϭ
Ϭ͘ϱ
s сϬs
/^/E< сϭŵ
Ϭ͘ϰ
Ϯ
ϭ͘ϵ
Ϭ͘ϯ
ϭ͘ϴ
Ϭ͘Ϯ
ϭ͘ϳ
Ϭ͘ϭ
ϭ͘ϲ
ϭ͘ϱ
Ϭ
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ͲϱϬ
ϭϱϬ
Ϭ
ϱϬ
ϭϬϬ
".W
Figure 26. UVLO saturation vs. Tj
".W
Figure 27. Soft-start clamp voltage vs. Tj
Ϭ͘ϵ
Ϯ͘ϱ
Ϭ͘ϴ
Ϯ͘ϰ
Ϯ͘ϯ
Ϭ͘ϳ
Ϯ͘Ϯ
Ϭ͘ϲ
sKDW сϰs
Ϯ͘ϭ
Ϭ͘ϱ
s^^s
s>s's
ϭϱϬ
dũΣ
dũΣ
s сϬs
/^/E< сϭŵ
Ϭ͘ϰ
Ϯ
ϭ͘ϵ
Ϭ͘ϯ
ϭ͘ϴ
Ϭ͘Ϯ
ϭ͘ϳ
Ϭ͘ϭ
ϭ͘ϲ
ϭ͘ϱ
Ϭ
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
dũΣ
dũΣ
".W
Doc ID 14821 Rev 6
".W
17/41
Typical characteristics
L6591
Figure 28. Low-side gate drive output low
saturation
Figure 29. Gate drive output low-voltage vs. Tj
Ϭ͘ϱ
ϭ͘ϴ
Ϭ͘ϰϱ
ϭ͘ϲ
Ϭ͘ϰ
ϭ͘ϰ
Ϭ͘ϯϱ
s>s'Θs,s's
ϭ͘Ϯ
Ϭ͘ϯ
s>s's
/сϮϬϬŵ
,ŝŐŚƐŝĚĞƌĞĨĞƌƌĞĚƚŽ&'E
Ϭ͘Ϯϱ
Ϭ͘Ϯ
ϭ
,ŝŐŚƐŝĚĞ
Ϭ͘ϴ
>ŽǁƐŝĚĞ
Ϭ͘ϲ
Ϭ͘ϭϱ
Ϭ͘ϰ
Ϭ͘ϭ
Ϭ͘Ϯ
Ϭ͘Ϭϱ
Ϭ
Ϭ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
ϮϬϬ
ͲϱϬ
ϮϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
dũΣ
/>s'ŵ
".W
Figure 30. Gate drive output high-voltage vs.
Tj
".W
Figure 31. High-side pull-down resistor vs. Tj
ϭ
ϭϰ
Ϭ͘ϵ
ϭϯ
>ŽǁƐŝĚĞ
Ϭ͘ϴ
Ϭ͘ϳ
Ϭ͘ϲ
s,s's
s>s'Θs,s's
ϭϮ
ϭϭ
Ϭ͘ϱ
Ϭ͘ϰ
ϭϬ
Ϭ͘ϯ
sĐĐсϭϱs͕sƚсϭϮs
/сͲϱŵ
,ŝŐŚƐŝĚĞƌĞĨĞƌƌĞĚƚŽ&'E
ϵ
,ŝŐŚƐŝĚĞƌĞĨĞƌƌĞĚƚŽ&'E
Ϭ͘Ϯ
Ϭ͘ϭ
Ϭ
ϴ
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
ϮϬϬ
Ϭ
".W
18/41
ϱϬ
ϭϬϬ
ϭϱϬ
ϮϬϬ
ϮϱϬ
/,s'ŵ
dũΣ
Doc ID 14821 Rev 6
".W
L6591
Typical characteristics
Figure 32. Burst mode thresholds vs. Tj
Figure 33. Burst mode hysteresis vs. Tj
ϵϬ
ϭ͘ϵ
ϭ͘ϴϱ
KĨĨƚŚƌĞƐŚŽůĚ;sKDW ƌĂŝƐŝŶŐͿ
ϴϱ
ϭ͘ϴ
ϴϬ
sKDW ƌĂŝƐŝŶŐ
ϭ͘ϳ
s KDW ŵs
sKDWs
ϭ͘ϳϱ
KŶƚŚƌĞƐŚŽůĚ;sKDW ĨĂůůŝŶŐͿ
ϭ͘ϲϱ
ϳϱ
ϳϬ
ϭ͘ϲ
ϲϱ
ϭ͘ϱϱ
ϲϬ
ϭ͘ϱ
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
ͲϱϬ
Ϭ
dũΣ
ϱϬ
ϭϬϬ
ϭϱϬ
dũΣ
".W
Figure 34. Line sensing threshold vs. Tj
".W
Figure 35. Line sensing current hysteresis vs.
Tj
ϭ͘ϱ
ϭϲ
ϭ͘ϰϱ
ϭϱ
ϭ͘ϰ
ϭϰ
ϭ͘ϯϱ
ϭϯ
/>/E ŵ
s>/E s
ϭ͘ϯ
ϭ͘Ϯϱ
ϭ͘Ϯ
sKDW хϱs
ϭϮ
ϭϭ
ϭ͘ϭϱ
ϭϬ
ϭ͘ϭ
ϵ
ϭ͘Ϭϱ
ϭ
ϴ
ͲϱϬ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
ͲϱϬ
dũΣ
Ϭ
ϱϬ
ϭϬϬ
ϭϱϬ
dũΣ
".W
Doc ID 14821 Rev 6
".W
19/41
Typical characteristics
L6591
Figure 36. Deadtime vs. Tj
Figure 37. Oscillator frequency vs. RT, CT
ϱϬϬ
ϭ͘Ϯ
ϰϱϬ
ϭ
dсϭϬϬƉ&
ϰϬϬ
ZdсϮϮ
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