FC106

® FC106 Fibre Channel Transceiver 1.0625 GBaud PRELIMINARY DATA FEATURES s Serial Link Transceiver q q serializer and deserializer implementing the Fibre Channel FC0 and FC1 layers Parallel Interface Receive Byte Clock REFCLK 10 bits s s s s Direct support for 1.0625 GBaud Fibre Channel (ANSI X3.230-1994) rates Fibre Channel 10-bit Interface (ANSI TR/X3.18-199X) Direct interfaces to optical tranceivers Plesiochronous mode operation q 8 bit / 10 bit DECODER (optional) 8 bit / 10 bit ENCODER (optional) transmitter and receiver clock frequencies may differ by up to 100 ppm DESER IALIZER CLOCK RECOVERY BYTE AND WORD ALIGNEMENT s s s s s s s s s s Integrated Fibre Channel 8b/10b encode/decode (optional use through JTAG) Byte and word synchronization of incoming serial stream Supports any DC-balanced encoding scheme Internal Loop-Back for Self-Test Random Pattern Auto-Test Optional integrated impedance adaptation to transmission line characteristics (50 or 75 ohms) TTL compatible parallel I/O’s JTAG Test Access Port 0.35 µ CMOS Technology for low cost and low power PQFP package available in two sizes: 14x14 mm (FC106/14) or 10x10 mm (FC106/10) SERIALI ZER AND CLOCK FREQUENCY MULTIPLICATION FC 106 1.0625 Gbaud Serial data over copper or optical cables APPLICATIONS s s s s Fibre Channel Arbitrated Loop Fibre Channel fabric Transmission schemes encoding bytes as 10-bit characters to form a DC-balanced stream High performance backplane interconnect 1/32 September 98 Revision 1.2 FC106 Table of Contents 1 2 3 General Description - - - - - - - - - - - - - - - - - - - - - - 4 Interface Diagram - - - - - - - - - - - - - - - - - - - - - - - 6 Functional Description - - - - - - - - - - - - - - - - - - - - 7 3.1 Block diagram - - - - - - - - - - - - - - - - - - - - - - - 8 3.2 Input latches - - - - - - - - - - - - - - - - - - - - - - - - 8 3.3 8bit/10bit Encoder/Decoder - - - - - - - - - - - - - - - - - 9 3.4 DLL clock generator - - - - - - - - - - - - - - - - - - - - 9 3.5 Serializer functional description and reference clock - - - - - 9 3.6 Serializer latches and XOR-tree - - - - - - - - - - - - - - 10 3.7 Serial input multiplexer - - - - - - - - - - - - - - - - - - 10 3.8 Deserializer functional description - - - - - - - - - - - - - 10 3.9 Bit alignment - - - - - - - - - - - - - - - - - - - - - - - 11 3.10 Byte and word alignment - - - - - - - - - - - - - - - - 12 3.11 Clock recovery - - - - - - - - - - - - - - - - - - - - - 12 3.12 Serial input-output buffer - - - - - - - - - - - - - - - - 13 3.13 I/O impedance control - - - - - - - - - - - - - - - - - - 14 3.14 Self-test - - - - - - - - - - - - - - - - - - - - - - - - - 15 4 5 Serial I/O Electrical Model - - - - - - - - - - - - - - - - - 16 Electrical Specifications - - - - - - - - - - - - - - - - - - 17 5.1 Absolute maximum ratings - - - - - - - - - - - - - - - - 17 5.2 Operating conditions - - - - - - - - - - - - - - - - - - - 17 5.3 DC characteristics - - - - - - - - - - - - - - - - - - - - 18 2/32 September 98 Revision 1.2 FC106 6 Timing Specifications - - - - - - - - - - - - - - - - - - - - 20 6.1 Transmit interface timing and latency - - - - - - - - - - - 20 6.2 Receive interface timing - - - - - - - - - - - - - - - - - 21 6.2.1 Receive clock timing and latency - - - - - - - - - - - 21 6.2.2 Receive interface timing - - - - - - - - - - - - - - - 23 6.3 Serial Input/output AC characteristics - - - - - - - - - - - 24 7 FC106 Pin Description - - - - - - - - - - - - - - - - - - - 25 7.1 Pin summary - - - - - - - - - - - - - - - - - - - - - - - 25 7.2 Pin functions - - - - - - - - - - - - - - - - - - - - - - - 26 8 Package Specifications - - - - - - - - - - - - - - - - - - - 29 8.1 FC106 64-pin PQFP pinout - - - - - - - - - - - - - - - - 29 8.2 FC106 64-pin Quad Flat-pack package dimensions - - - - 30 8.2.1 FC106/14: 14x14 mm package dimensions - - - - - - 30 8.2.2 FC106/10: 10x10 mm package dimensions - - - - - - 31 3/32 September 98 Revision 1.2 FC106 1 General Description The FC106 Fibre Channel transceiver chip implements the lower layer protocols of the ANSI X3.230-1994 Fibre Channel standard. The Fibre Channel standard specifies the mapping of various upper layer protocols (ULP) such as SCSI, IP and HiPPI to a common lower layer protocol, together with appropriate electrical and optical high performance specifications. Fibre Channel provides a channel over which concurrent communication of a variety of ULP’s may exist on a single interconnect between workstations, mainframes and supercomputers, and provides a connection to mass storage devices and other peripherals. The FC106 implements the Fibre Channel electrical transceiver physical layer specification for 1.0625 Gbit/s. At this frequency, the Fibre Channel delivers 100 MByte/s of data bandwidth over a twin coaxial or twin optical fibre cable. This bandwidth equals or exceeds most bus bandwidths. The FC106 chip performs the high speed serialization and deserialization function that makes bus-bandwidth, serial communication possible. This chip can drive electrical cables directly or it can interface with suitable optical modules. Figure 1.1 shows the different connections. Figure 1.1 FC106 chip connections 1.0625 Gb/s System 1 Serial Data over copper or optical cables System 2 REFCLK (1) REFCLK (2) Fibre Fibre I/O Bus Channel Controll er FC106 FC106 Channel Controller The parallel interface on the FC106 is compatible with the 10-Bit Interface Specification (ANSI TR/X3.18-1998) which defines a common, standard signaling interface between the Fibre Channel Physical and Protocol layers. In addition, the FC106 can be used for all other proprietary serial links transmitting data as 10-bit encoded characters. The FC106 incorporates an impedance adaptor circuit (set by the pins ZC+, ZC-) to ensure high quality adaptation to the transmission line characteristic impedance.This feature is optional and the user can keep external adaptation for compatibility reasons. 4/32 September 98 Revision 1.2 I/O Bus 10 bits 10 bits FC106 The FC106 integrates a loop-back path for system-level test purposes. It also includes a self-test capability in which random patterns are transmitted through the internal loop-back path and compared after reception. The FC106 is implemented in a standard digital 0.35 µ CMOS process. Its typical power consumption is 0.4 Watts (not including the power required to drive the TTL parallel output port, which is in the 0.1 Watt range for output capacitive loads of 10 pF per pin). 5/32 September 98 Revision 1.2 FC106 2 Interface Diagram Interface diagram TTTTT T C R MD D R A E K S S I OS T N Figure 2.1 Test 10 FC Protocol Device TX[0:9] COM_DET RBC[0:1] RX[0:9] 2 10 receiver REFCLK EWRAP EN_CDET [106.25 MHz] FC106 transmitter 6/32 September 98 Revision 1.2 FC106 3 Functional Description The FC106 provides all required signals in the 10-Bit Interface Specification for Fibre Channel. It also provides 10 pins for additional functions (these pins are marked in the following by *). The additional functions are: • impedance control (ZC+*, ZC-*) • production test through JTAG (TCK(*)-TRSTN(*)-TMS (*)-TDI(*)-TDO (*)- TEST ENABLE (*)) • self-test of the chip (AT*) • reset pin (RS) (but note that another reset is automatically generated in the chip during power on). In addition to implementing the Fibre Channel standard, the FC106 is adaptable through the JTAG path to the transmission of any sequence of 10-bit encoded characters at rates varying between 1 and 1.1 Gbaud. 7/32 September 98 Revision 1.2 FC106 3.1 TCK(*) TRSTN(*) TMS(*) Block diagram Block diagram JTAG CONTROL Figure 3.1 SERIALIZER ENC XOR Tree transmitter TDI(*) TDO(*) TEST ENABLE(*) TX- TX [0:9] TX+ 8b/10b encoder ZC+(*) DLL clock generator ZC setting RCB[0:1] Clock Recovery AT (*) RS (*) ZC-(*) REFCLK 8b/10b decoder Word Alignment Bit Alignment rece iver RX- SELF TEST ENC RX+ DESERIALIZER RX[0:9] EN_CDET COM_DET (*)Test signals not included in FCS 10-bit interface EWRAP 3.2 Input latches The transmitter accepts 10-bit wide TTL parallel data at inputs TX[0:9]. The user-provided reference clock signal REFCLK is also used as the transmit byte clock. The TX[0:9] and REFCLK signals must be properly aligned, as shown in Section 6.1: Transmit interface timing and latency on page 20. 8/32 September 98 Revision 1.2 FC106 3.3 8bit/10bit Encoder/Decoder In normal operation mode, the FC106 accepts 10-bit pre-encoded data, and provides to the application, 10-bit encoded data (as specified in the ANSI 10-bit Interface Specification). In addition, the FC106 contains an 8b/10b encoder/decoder, which can be inserted into the data flow. The selection of this mode is made through the JTAG path. In this mode, the FC106 accepts and delivers bytes on 9 bits (8 bits of data on TX/RX[0:7] and 1 bit on TX/ RX[8] which is used to differentiate control characters). The timings of the parallel I/O ports are identical in both modes: using the 8b/10b encoder/decoder increases the transmission latency by 2 byte clock periods (equivalent to a 4 meter increase of the cable length). 3.4 DLL clock generator The Delay Locked Loop (DLL) block generates the internal clocks. These are required by the transmitter section to perform its function, and by the receiver block to generate the reference clocks which are used to recover the serial data input frequency. These clocks are based on the user supplied reference byte clock REFCLK. This clock is multiplied by 10 to generate the required serial output data rate. No external components are required to operate the DLL Clock Generator. 3.5 Serializer functional description and reference clock The FC106 serializer performs the serialization of 10-bit pre-encoded parallel data at signaling rates up to 1.0625 Gb/s. System design is simplified by the integration into the chip of a block performing clock multiplication from the parallel data clock. It accepts 10-bit encoded parallel data words which are clocked into the device at 1/10 of the signaling rate. For Fibre Channel use, data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specification. The FC106 serializes the input data and transmits it at a signaling rate of 10 times the frequency of the REFCLK input. The device includes a Delay-Locked-Loop based clock multiplier that generates the 1.0625 Gbaud clocks. This DLL is fully monolithic and requires no external components. Its acquisition time, at power-up, is less than 16 microseconds. The FC106 loads parallel data on the rising edge of REFCLK. The delay through the FC106 from loading the code-group to the transmission of the first bit of the code-group on the TX+, TX- pair, is 17.4 ns with an extra 9.4 ns if the 8b10b encoding function is enabled. A loop-back-mode signal EWRAP is provided allowing internal dynamic self-test of the chip. When EWRAP is low, the output of the transmitter is sent to the TX+ and TX- output pins, and the input of the receiver is driven by the signals entered through the RX+ and RX- pins. 9/32 September 98 Revision 1.2 FC106 When EWRAP is high, the output of the transmitter is sent directly to the input of the receiver. 3.6 Serializer latches and XOR-tree The parallel data words TX[0:9] are individually sampled using the clocks provided by the DLL Clock Generator. The outputs of these serializer latches are merged through an Exclusive-OR tree, in order to generate the output data bit streams. 3.7 Serial input multiplexer The Input Multiplexer supports the internal loopback of the high speed serial signal for test purposes. In normal operation, EWRAP is set low. The serial output data stream is placed at TX+/TXoutputs, and the serial data accepted at RX+/RX- is transmitted to the deserializer block. When wrap-mode is activated by setting EWRAP high, the serial data generated by the serializer block is internally wrapped to the input of the deserializer block. 3.8 Deserializer functional description The FC106 deserializer operates at signaling rates up to 1.0625 Gb/s, as specified in the Fibre Channel standard. It extracts the clock and retimes the data from the serial bit stream. The serial bit stream should be encoded as 10-bit characters (for example the 8B/10B code for Fibre Channel) which provide a transition density greater than 10%. The retimed serial bit stream is converted into a 10-bit parallel output word. The FC106 has internal DLL based clock recovery circuit which requires no external components. When the DLL of the serializer clock multiplier is locked to the expected data rate (defined by REFCLK), the retiming acquisition time (to lock to the incoming serial data stream) is less than 3 microseconds. The FC106 provides byte and data word alignment using a comma symbol recognition mechanism. The 7-bit comma symbol is defined in Fibre Channel specification as a [0:6]= 0011111. This pattern is only contained within special characters known as K28.1, K28.5 and K28.7 defined specifically for synchronization by Fibre Channel. Serial data is received on the RX+ and RX- pins. The DLL clock recovery circuit will lock to the data stream if the clock to be recovered is within 0.01% of the expected data rate. For 10/32 September 98 Revision 1.2 FC106 example, if the REFCLK used is 106.25 MHz, then the incoming data serial signaling rate must be 1.0625 ± 0 .0001 Gb/s. The FC106 provides 2 TTL recovered clocks RBC[0] and RBC[1], which are both driven at a frequency of one twentieth of the serial signaling rate. These clocks are generated by the clock recovery DLL, which is phase locked to the serial data. RBC[1] is 180° out of phase with RBC[0]. If serial data is not present, or does not meet the required transition density or signaling rate, the RBC frequencies will be half of the expected recovered clock frequency (defined by REFCLK). This function replaces the optional LCK_REF signal that is specified in the Fibre Channel 10-bit interface. When no data is present, phase adjustments are required for switching between a locking to incoming data and locking to REFCLK. The specification on output clocks RBC[0:1] is maintained during these adjustments.The clock periods are not truncated. The serial data is retimed and deserialized. Parallel data is loaded into the output register, and therefore accessible on the output data port. For Fibre Channel use, bytes 1 and 3 of the receive data word will be accessible on the rising edge of RBC[0], and bytes 0 and 2 on the rising edge of RBC[1]. Word synchronization is enabled in the FC106 by connecting the EN_CDET pin to V dd. When EN_CDET is set high, the FC106 examines serial data for the presence of a positive disparity comma symbol (0011111). Improper alignment occurs when a comma symbol straddles a 10-bit boundary or is not aligned within the 10-bit transmission character. Proper alignment is reached by shifting the boundary of the parallel output. At power up the FC106 will not be in synchronization and data alignment is not established. The COM_DET output signal is then set low. When a comma symbol is detected, COM_DET is set high (if EN_CDET is already set high). COM_DET will go high only during a cycle in which RBC[1] is rising (see Section 6.2.2: Receive interface timing on page 23 for precise timing). Note that if EN_CDET is set low, but a comma is detected while the input stream is already word-aligned, COM_DET will be set high again. 3.9 Bit alignment The alignment block aligns the incoming data bit stream and the reference clocks generated by the DLL Clock Generator. It compensates for clock frequency dispersions between the crystals generating the respective reference clocks REFCLK of the transmitting and receiving chips. 11/32 September 98 Revision 1.2 FC106 3.10 Byte and word alignment The word alignment function is performed under control of the EN_CDET signal. When EN_CDET is high, the word alignment function is operational. If an improperly aligned comma is encountered, the internal data is shifted to realign the comma character at the deserializer output (RX[0:9]). In this process, up to three characters prior to the comma character may be corrupted. 3.11 Clock recovery The clock recovery block generates the two receiver byte clocks RBC[0:1] at half the frequency corresponding to the RX+/RX- byte data rate. These two byte clocks are 180 ° out of phase with each other. They are alternatively used to clock the 10-bit parallel output data. 12/32 September 98 Revision 1.2 FC106 3.12 Serial input-output buffer Figure 3.2 shows a simplified schematic of the serial I/O. Figure 3.2 Schematic diagram of serial I/O Vdd Vdd Dout- Dout+ V ss Vss Transmitting Chip TX+ Rs Rout TXRs See Section 3.13 for configuration control versus line impedance 0.01 µF(optional) Rc 0.01µF Receiving Chip 1.5 KΩ RX+ RX1.5 KΩ Rin 1.5 KΩ 1.5 KΩ TO DESERIALIZER 13/32 September 98 Revision 1.2 FC106 3.13 I/O impedance control The ZC block sets the internal RX+/RX- and the TX+/TX- matching impedance. Table 3.1 details the different settings. Table 3.1 ZC block settings ZC+ Case 1: 50Ω line Rout = 100Ω Rc = 100Ω R > 1.5KΩ ZC- ADD Rs ADD Rc +/-1% +/-1% 100 Ω Rs = 0Ω LINE = 50Ω External Rc OPEN OPEN 0 Ω or Vdd or Vdd transmitter Rs = 0Ω receiver Case 2: 50Ω line Rout = 100Ω Rin = 100Ω R > 1.5K Ω Rs = 0Ω LINE = 50Ω Vss No external Rc Use internal Rc receiver OPEN 0 Ω or Vdd NONE transmitter Rs = 0Ω Case 3: 75Ω line Rout = 100Ω Rc = 150Ω R > 1.5K Ω Rs = 25Ω LINE = 75Ω External Rc OPEN OPEN 25 Ω or Vdd or Vdd 150 Ω transmitter- Rs = 25Ω receiver Case 4: 75Ω line Rout = 150Ω Rc = 150Ω R > 1.5K Ω Rs = 0Ω LINE = 75Ω External Rc OPEN Vss or Vdd 0Ω 150 Ω transmitter Rs = 0Ω receiver Case 5: 75Ω line Rout = 150Ω Rin = 150Ω R > 1.5K Ω Rs = 0Ω LINE = 75Ω Vss No external Rc Use internal Rc receiver Vss 0Ω NONE transmitter Rs = 0Ω Case 3 and 4 are identical applications: Case 3 allows better on board compatibility with other FC parts that request 25 Ω series resistors. Exact value of Rout and Rin are detailed in Section 5.3: DC characteristics on page 18. 14/32 September 98 Revision 1.2 FC106 3.14 Self-test The self-test block generates its own internal clock (the frequency of which can be digitally tuned through the JTAG port), and pseudo-random patterns. This data is encoded, serialized, deserialized (through the loop-back test path, or through an external connection between TX+/TX- and RX+/RX-) and decoded. The recovered data is checked; the errors and the number of transmitted bytes are internally counted. The contents of these counters are accessible through the JTAG path. This block is activated by the AT signal. In normal operation, AT is tied to Vdd and the self-test block is disabled. During production tests, AT is forced to Vss, allowing full speed dynamic tests, even at wafer level. 15/32 September 98 Revision 1.2 FC106 4 Serial I/O Electrical Model Serial I/O electrical schematic diagram Vdd Vss Tr R1 1pF 1pF R1 Tr = Tf = 0.2nS Vdd Tf V ss This simplified model is given for typical board simulation, within 15% precision. The termination at the receiving end can be either internal or external, following Section 3.13. Figure 4.1 Simplified serial transmitter model Rout Zc = 40 Ω Td = 0.15nS Zc = 40Ω Td = 0.15nS Simplified QFP64 package model Your board and/or cable/connector model 0.01 µ F(optional) Rc 0.01 µF(optional) Zc = 60Ω Td = 0.15nS Zc = 60Ω Td = 0.15nS Simplified QFP64 package model 0.5pF Rin 0.5pF Simplified serial receiver model 1.5KΩ 1.5KΩ 1.5KΩ 1.5KΩ TO DESERIALIZER 50 Ω CONFIGURATI ON PARAMETER VALUES FOR TYPICAL SIMULATIO N R1 Rout Rc Rin 100Ω 200Ω 100Ω if external termination 100Ω if internal termination 75 Ω CONFIGURA TION 150Ω 300Ω 150 Ω if external termination 150Ω if internal termination 16/32 September 98 Revision 1.2 FC106 5 5.1 Symbol Vdd V V INL INH Electrical Specifications Absolute maximum ratings Absolute maximum ratings Parameter Supply Voltage Serial signal input low level Serial signal input high level Units V V V Min 0 -0.5 Vdd+0.5 Max 4 Table 5.1 ZC+, ZC- V Vdd+0.5 TTL input signals T° C MAX Maximum assembly temperature (for 10 seconds maximum) Storage temperature V °C °C -65 5.5 260 150 Note Stresses greater those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions ( VIN>Vdd or VIN