FERD30S50DJF-TR

FERD30S50 Field effect rectifier Datasheet  production data A Features A  CMOS proprietary process  Stable leakage current over reverse voltage K A  Low forward voltage drop A  High frequency operation Description K K ) s t( c u d o r P This single rectifier is based on a proprietary technology, enabling to achieve the best in class VF/IR trade-off for a given silicon surface. e t le o s b Packaged in PowerFLAT™ 5x6, this device is intended to be used in rectification and freewheeling operations in switch-mode power supplies. O ) A A s ( t c PowerFLAT 5x6 FERD30S50DJF u d o Table 1. Device summary Symbol e t e ol IF(AV) s b O Pr Value 30 A VRRM 50 V Tj (max) +150 °C VF(typ) 0.33 V TM: PowerFLAT is a trademark of STMicroelectronics November 2013 This is information on a product in full production. Doc ID024715 Rev 2 1/8 www.st.com Characteristics 1 FERD30S50 Characteristics Table 2. Absolute ratings (limiting values, at 25 °C, unless otherwise specified, anode terminals short-circuited) Symbol Parameter Value Unit VRRM Repetitive peak reverse voltage 50 V IF(RMS) Forward rms current 45 A A IF(AV) Average forward current,  = 0.5 Tc = 95 °C 30 IFSM Surge non repetitive forward current tp = 10 ms sinusoidal 180 Tstg Storage temperature range Tj (1) ct u d o Maximum operating junction temperature Table 3. Thermal resistance Symbol Rth(j-c) A -65 to + 175 1 dPtot < condition to avoid thermal runaway for a diode on its own heatsink Rth(j-a) dTj 1. ) s ( t e l o Parameter Junction to case r P e s b O 150 °C °C Value (max) Unit 2.6 °C/W Table 4. Static electrical characteristics (anode terminals short-circuited) Symbol IR (1) P e s b O t e l o Forward voltage drop Test conditions ct du Reverse leakage current ro VF(2) ) (s Parameter Tj = 125 °C Tj = 25 °C Tj = 125 °C Tj = 25 °C Tj = 125 °C Tj = 25 °C Tj = 125 °C Tj = 25 °C Tj = 125 °C Min. VR = 35 V VR = VRRM Max. Unit 0.8 mA 25 30 60 0.32 IF = 5 A 0.25 0.37 IF = 10 A IF = 15 A 1. Pulse test: tp = 5 ms,  < 2% 2. Pulse test: tp = 380 µs,  < 2% To evaluate the conduction losses use the following equation: P = 0.205 x IF(AV) + 0.017 IF2(RMS) 2/8 Typ. Doc ID024715 Rev 2 V 0.33 0.415 0.47 0.39 0.45 FERD30S50 Characteristics Figure 1. Average forward power dissipation versus average forward current 24 PF(AV)(W) 35 d = 0.5 d = 1 20 R th(j-a) = R th(j- c) 25 d = 0.1 20 d = 0.05 15 8 T 4 IF(AV)(A) 0 0 5 10 15 20 d=tp/T 25 30 T 10 5 tp 35 0 40 Figure 3. Relative variation of thermal impedance junction to case versus pulse duration 1.0 IF(AV)(A) 30 d = 0.2 16 12 Figure 2. Average forward current versus ambient temperature ( = 0.5) Z t h ( j- c) / R t h ( j- c ) d=tp/T tp 25 50 0 0.9 e t le IR(mA) o s b 0.8 1.E+01 0.6 O ) 0.5 0.4 0.3 Single pulse 0.1 0.0 1.E-04 1.E-03 du 1.E-02 1.E-01 t p (s) 1.E+00 o r P Figure 5. Junction capacitance versus reverse voltage applied (typical values) e t e l C(pF) 10000 125 150 c u d o r P Tj = 125 °C Tj = 25 °C 1.E-01 V R (V) 0 5 10 15 20 25 30 35 40 45 50 Figure 6. Forward voltage drop versus forward current (typical values) I (A) 100.0 F so Ob 100 1.E+00 s ( t c 0.2 75 Figure 4. Reverse leakage current versus reverse voltage applied (typical values) 1.E+02 0.7 ) s t( Tamb(°C) F = 1 MHz Vosc = 30 mVRMS Tj = 25 °C 10.0 Tj = 125 °C 1000 Tj = 25 °C 1.0 VR (V) 100 1 10 100 V F (V) 0.1 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 Doc ID024715 Rev 2 3/8 8 Characteristics FERD30S50 Figure 7. Thermal resistance junction to ambient versus copper surface under tab (typical values) R th( j - a)(°C/W) 150 Epoxy printed board Fr4, copper thickness = 35 µm 125 100 75 ) s t( 50 c u d 25 o r P SCu (cm²) 0 0 1 2 3 4 e t le 5 o s b O ) s ( t c u d o r P e t e l o s b O 4/8 Doc ID024715 Rev 2 6 7 8 9 10 FERD30S50 2 Package information Package information  Epoxy meets UL94, V0  Cooling method: by conduction (C) In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 8. PowerFLAT-8L dimensions (definitions) E2 K b e e t le A D A1 o s b ) s t( c u d D2 L o r P A2 O ) E s ( t c u d o Table 5. PowerFLAT-8L dimensions (values) e t e ol Ref. O bs Pr Dimensions Millimeters Min. Typ. Inches Max. Min. Typ. Max. A 0.80 1.00 0.031 0.039 A1 0.02 0.05 0.001 0.002 A2 b 0.25 0.30 D D2 0.010 0.50 0.012 5.20 4.11 0.020 0.205 4.31 0.162 0.170 e 1.27 0.050 E 6.15 0.242 E2 3.50 3.70 0.138 0.146 L 0.50 0.80 0.020 0.031 K 1.275 1.575 0.050 0.062 Doc ID024715 Rev 2 5/8 8 Package information FERD30S50 Figure 9. Footprint (dimensions in mm) 3.86 4.33 6.29 5.35 4.41 0.98 0.95 ) s t( 0.62 1.27 c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 6/8 Doc ID024715 Rev 2 o r P FERD30S50 3 Ordering information Ordering information Table 6. Ordering information 4 Order code Marking Package Weight FERD30S50DJF FD30S50 PowerFLAT 5x6 95 mg Base qty Delivery mode 3000 Tape and reel Revision history c u d Table 7. Document revision history Date Revision 28-Jun-2013 1 Initial release. 2 Updated Table 1 and Table 4. Inserted new Figure 1, Figure 2, Figure 4 and Figure 6. Product name changed from FERD30S50DJF to FERD30S50. 18-Nov-2013 Changes ) s t( e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O Doc ID024715 Rev 2 7/8 8 FERD30S50 ) s t( Please Read Carefully: c u d Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. o r P Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. e t le No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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