HCF40103BEY

HCF40103B 8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS ■ ■ ■ ■ ■ ■ ■ ■ SYNCHRONOUS OR ASYNCHRONOUS PRESET MEDIUM -SPEED OPERATION : fCL =3.6MHz (Typ.) at VDD = 10V CASCADABLE QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF40103B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40103B consists of an 8-stage synchronous down counter with a single output that is active when the internal count is zero. This device contains a single 8-bit binary counter. It has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO DETECT output are active-low logics. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/ ) (s t c u d o r P e t e l o s b O ) s ( ct DIP SOP PACKAGE TUBE t e l o DIP SOP u d o r P e ORDER CODES HCF40103BEY HCF40103BM1 T&R HCF40103M013TR CE) input is high. The CARRY-OUT/ZERO DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET ENABLE (SPE) input is low, data at the JAM input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input. When the ASYNCHRONOUS PRESET ENABLE (APE) input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 represent a single 8 bit binary word. When the CLEAR (CLR) input is low, the counter is asynchronously cleared to its maximum count (25510) regardless of the state of any other input. The precedent relationship between control input is indicated in the truth table. If all control s b O PIN CONNECTION September 2002 1/14 HCF40103B inputs are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. HCF40103B may be cascaded using the CI/CE input and the CO/ZD output, in either a synchronous or ripple mode. IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 CLOCK 2 CLEAR 3 4, 5, 6, 7, 10, 11, 12, 13 CI/CE J0 to J7 9 APE 14 CO/ZD SPE let 16 o s b FUNCTIONAL DIAGRAM ) s ( ct Jam Inputs Asynchronous Preset Enable Inputs(Active Low) Terminal Count Output (Active Low) Synchronous Preset Enable Input (Active Low) u d o r P e 15 8 NAME AND FUNCTION Clock Input (LOW to HIGH edge triggered) Asynchronous Master Reset Input (Active Low) Terminal Enable Input VSS Negative Supply Voltage VDD Positive Supply Voltage O ) s ( t c u d o r P e t e l o s b O TRUTH TABLES CONTROL INPUTS PRESET MODE CLR APE SPE CI/CE H H H H L H H H L X H H L X X H L X X X Synchronous Asynchronous X : Don’t Care Clock connected to Clock input Synchronous Operation : changes occur on negative to positive clock transitions. 2/14 ACTION Inhibit Counter Count Down Preset on Next Positive Clock Transition Preset Asynchronously Clear to Maximum Count HCF40103B LOGIC DIAGRAM ) s ( ct u d o r P e t e l o ) (s LOGIC DIAGRAM FOR FLIP-FLOPS, FF0-FF7 s b O t c u d o r P e t e l o s b O 3/14 HCF40103B TIMING CHART ) s ( ct u d o r P e t e l o t c u ABSOLUTE MAXIMUM RATINGS Symbol VDD od Pr Supply Voltage ) (s Parameter s b O Value Unit -0.5 to +22 V VI DC Input Voltage -0.5 to VDD + 0.5 V II DC Input Current ± 10 mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C e t e ol PD s b O Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD 4/14 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF40103B DC SPECIFICATIONS Test Condition Symbol IL Parameter Quiescent Current 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Output Voltage VOH Low Level Output Voltage VOL High Level Input Voltage VIH Low Level Input Voltage VIL Output Drive Current IOH Output Sink Current IOL Input Leakage Current Input Capacitance II CI VO (V) VI (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 r P e |IO| VDD (µA) (V)