HCF4015M013TR

HCF4015B DUAL 4-STAGE STATIC SHIFT REGISTER WITH SERIAL INPUT/PARALLEL OUTPUT ■ ■ ■ ■ ■ ■ ■ ■ ■ MEDIUM SPEED OPERATION 12 MHz (Typ.) CLOCK RATE AT VDD - VSS = 10V FULLY STATIC OPERATION 8 MASTER-SLAVE FLIP-FLOPS PLUS INPUT AND OUTPUT BUFFERING HIGH NOISE IMMUNITY QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF4015B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4015B consists of two identical, independent, 4 stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the ) s ( ct DIP SOP ORDER CODES PACKAGE TUBE DIP SOP HCF4015BEY HCF4015BM1 ) s t( T&R c u d HCF4015M013TR o r P four stages on both registers. All register stages are D-TYPE, MASTER-SLAVE flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive going clock transition. The resetting of all stages is accomplished by a high level on the reset line. It is possible to expand the register to 8 stages using one HCF4015B package and to expand to more than 8 stages by using addition HCF4015Bs. e t le o s b O - u d o r P e t e l o PIN CONNECTION s b O September 2002 1/10 HCF4015B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 8 CLOCK A CLOCK B RESET A RESET B DATA A DATA B QnA QnB VSS 16 VDD 1, 9 6, 14 7, 15 5, 4, 3, 10 13, 12, 11, 2 NAME AND FUNCTION Clock Input Reset Input Data Inputs Outputs A-Stage Outpus B-Stage Negative Supply Voltage Positive Supply Voltage FUNCTIONAL DIAGRAM c u d e t le ) s ( ct TRUTH TABLE CLOCK r P e t e l o bs O X X : Don’t Care 2/10 u d o ) s t( o r P o s b O - D R Q1 Qn L L L Qn - 1 H L H Qn - 1 X L Q1 Qn - (NO CHANGE) X H L 0 HCF4015B LOGIC DIAGRAM c u d ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter VI DC Input Voltage II DC Input Current Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Tstg Storage Temperature PD e t le Supply Voltage (s) b O - so o r P Value ) s t( Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW -55 to +125 °C -65 to +150 °C t c u Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. d o r P e RECOMMENDED OPERATING CONDITIONS Symbol t e l o VDD VI Top s b O Supply Voltage Input Voltage Operating Temperature Parameter Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C 3/10 HCF4015B DC SPECIFICATIONS Test Condition Symbol IL Parameter Quiescent Current 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Output Voltage VOH Low Level Output Voltage VOL High Level Input Voltage VIH Low Level Input Voltage VIL Output Drive Current IOH 0/5 0/5 0/10 0/15 0/5 0/10 0/15 Output Sink Current IOL Input Leakage Current Input Capacitance II CI VO (V) VI (V) 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 |IO| VDD (µA) (V)