HCF4017BEY

HCF4017B DECADE COUNTER WITH 10 DECODED OUTPUTS ■ ■ ■ ■ ■ ■ ■ ■ MEDIUM SPEED OPERATION : 10 MHz (Typ.) at VDD = 10V FULLY STATIC OPERATION STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION The HCF4017B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4017B is 5-stage Johnson counter having 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the clock input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. This counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advanced via the clock line is inhibited ) (s t c u d o r P e t e l o ) s ( ct DIP SOP PACKAGE TUBE t e l o DIP SOP u d o r P e ORDER CODES HCF4017BEY HCF4017BM1 T&R HCF4017M013TR s b O when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson decade-counter configuration permits high speed operation, 2-input decimal decode gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded outputs are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY - OUT signal completes one cycle every 10 clock input cycles and is used to ripple-clock the succeeding device in a multi-device counting chain. s b O PIN CONNECTION September 2001 1/11 HCF4017B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 14 SYMBOL NAME AND FUNCTION 0 to 9 Decoded Decimal Output 8 CLOCK CLOCK INHIBIT RESET CARRY OUT VSS 16 VDD 13 15 12 Clock Input Clock Inhibit Input Reset Input Carry Output Negative Supply Voltage TRUTH TABLE Positive Supply Voltage FUNCTIONAL DIAGRAM CLOCK CLOCK INHIBIT X X u d o r P e t e l o s b O This logic diagram has not be used to estimate propagation delays 2/11 Q0 X L L Qn L L Qn+1 L L Qn H L Qn H L Qn+1 t e l o LOGIC DIAGRAM H H L s ( t c DECODED OUTPUT r P e u d o RESET Qn X )- ) s ( ct s b O X : Don’t Care Qn : No Change HCF4017B TIMING CHART ) s ( ct u d o r P e t e l o ABSOLUTE MAXIMUM RATINGS Symbol )- VDD Parameter t(s Supply Voltage VI DC Input Voltage II DC Input Current PD c u d Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature ete Tstg o r P Storage Temperature s b O Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW -55 to +125 °C -65 to +150 °C l o s Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. b O RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C 3/11 HCF4017B DC SPECIFICATIONS Test Condition Symbol IL Parameter Quiescent Current 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Output Voltage VOH Low Level Output Voltage VOL High Level Input Voltage VIH Low Level Input Voltage VIL Output Drive Current IOH Output Sink Current IOL Input Leakage Current Input Capacitance II CI 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0/18 |IO| VDD (µA) (V)