HCF4099BEY

HCF4099B 8 BIT ADDRESSABLE LATCH ■ ■ ■ ■ ■ ■ ■ ■ SERIAL DATA INPUT - ACTIVE PARALLEL OUTPUT STORAGE REGISTER CAPABILITY MASTER CLEAR CAN FUNCTION AS DEMULTIPLEXER QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF4099B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4099B, an 8-bit addressable latch, is a serial-input, parallel output storage register that can perform a variety of functions. Data is input to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4099BEY HCF4099BM1 HCF4099M013TR WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer ; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level. PIN CONNECTION October 2002 1/14 HCF4099B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 5, 6, 7 9, 10, 11, 12, 13, 14, 15, 1 3 2 A0 to A2 Address Inputs Q0 to Q7 Latch Outputs Data Inputs Reset Input 8 DATA RESET WRITE DISABLE VSS 16 VDD 4 NAME AND FUNCTION Write Disable Input Negative Supply Voltage Positive Supply Voltage FUNCTIONAL DIAGRAM TRUTH TABLE SELECT INPUTS LATCH ADDRESSED C B A L L L L H H H H L L H H L L H H L H L H L H L H INPUTS WRITE DISABLE RESET OUTPUTS OF ADDRESSED LATCH L L H H L H L H D Qi0 D L Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 EACH OTHER OUTPUT FUNCTION Qi0 Qi0 L L ADDRESSABLE LATCH MEMORY DEMULTIPLEXER CLEAR ALL BITS TO "0" D: The level at the data input ; Qi0 The level before the indicated steady state input conditions were established, (i=0, 1,...7) 2/14 HCF4099B LOGIC DIAGRAM TIMING CHART 3/14 HCF4099B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD 4/14 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF4099B DC SPECIFICATIONS Test Conditions Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value IO VDD (µA) (V)