HDMI2C1-14HD
ESD protection and signal conditioning
for HDMI™ 2.0 source interface
Datasheet production data
High integration level for minimal PCB footprint
Efficient protection of sensitive HDMI™ ASICs
Very low power consumption in stand-by mode
Wake-up from stand-by through CEC bus
Allow to drive long cable and poor quality cable
Companion chip for STMicroelectronics’
STixxxx HDMI™ decoders
Complies with the following standards
HDMI™ 2.0 version
Features
IEC 61000-4-2 level 4
HDMI™ 2.0 (4K/2K 60fps) compliant from -40 to
85 °C
JESD22-A114D level 2
TMDS high bandwidth and very low clamping
voltage ESD protection
Applications
8 kV contact ESD protection on connector side
Supports direct connection to low-voltage
HDMI™ ASIC and/or CEC driver (down to
1.8 V)
DDC capacitive decoupling between ASIC and
HDMI™ connector and dynamic pull-up for long
cable driving
Back drive protection on 5 V, DDC bus and
CEC
CEC independent structure from main power
supply
HDMI™ Ethernet and audio return channel
(HEAC) compatible
HPD pull down and signal conditioning
Short-circuit protection on 5 V output
Proposed in QFN 36 leads 500 µm pitch
Consumer and computer electronics HDMI™
source device such as:
– Set-top boxes / ADSL boxes
– DVD and Blu-Ray disk systems
– Notebook / PC graphic cards
– Game console
– Home theater
Description
The HDMI2C1-14HD is a fully integrated ESD
protection and signal conditioning device for
control links and TMDS data video channels of
HDMI™ transmitters (source).
The HDMI2C1-14HD is a simple solution that
provides HDMI™ designers with an easy and fast
way to reach full compliance with the stringent
HDMI™ 2.0 (4K/2K 60fps) on a wide temperature
range.
Benefits
Easy hardware design and speed-up
certification of HDMI™ 2.0
Pin map sequence compliant with HDMI™
connector type A
May 2015
This is information on a product in full production.
TM: HDMI: the HDMI logo and High-Definition
Multimedia Interface are trademarks or registered
trademarks of HDMI Licensing LLC.
DocID023674 Rev 2
1/32
www.st.com
Contents
HDMI2C1-14HD
Contents
1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
CEC line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
DDC functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
HEAC link and HPD line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1
HPD line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2
HEAC functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
+5V protection and fault line functional block description . . . . . . . . . . . . .11
2.5
Back drive protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6
TMDS channels ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7
Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5
4.1
QFN package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Recommendation on PCB assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
Stencil opening design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2
Solder paste . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3
Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4
PCB design preference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5
Reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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DocID023674 Rev 2
HDMI2C1-14HD
Functional description
The HDMI2C1-14HD is a fully integrated ESD protection and signal conditioning device for
control links and TMDS data video channels of HDMI™ transmitters (source).
The control stage provides a bidirectional buffer, integrating signal conditioning and dynamic
pull-up on DDC bus for maximum system robustness and signal integrity. The HEAC (HDMI
Ethernet and audio return channels) function is supported, making the component fully
compliant with HDMI 2.0 version. A bidirectional CEC block is integrated, able to wake-up
the application from stand-by mode (all power supply off, except the CEC power supply). All
video format specified by HDMI™ 2.0 standard like 1080p60 3D, 4K/2K 60fps are
supported, giving maximal flexibility to designers. The +5 V supplied to the cable is
protected against accidental surge current and short circuit. All these features are provided
in a single 36 leads QFN package featuring natural PCB routing and saving space on the
board.
The HDMI2C1-14HD is a simple solution that provides HDMI™ designers with an easy and
fast way to reach full compliance with the stringent HDMI™ 2.0 on a wide temperature
range. STMicroelectronics proposes a dual version dedicated for the sink interfaces: the
HDMI2C2-14HD.
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Functional description
HDMI2C1-14HD
Figure 2. Block diagram
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DocID023674 Rev 2
HDMI2C1-14HD
Application information
2
Application information
2.1
CEC line description
The CEC bus is described in the HDMI™ standards as the consumer electronics control. It
provides control functions between all the various audiovisual equipments chained in the
user's environment.
The CEC block integrated in the HDMI2C1-14HD implements a level shifter, shifting the
cable CEC +3.3 V voltage (VDD_CEC) down to the ASIC power supply voltage (VDD_CEC_IC)
that can be as low as 1.8 V. The Figure 3 shows the functional diagram of the integrated
CEC block.
Figure 3. CEC link functional diagram
VDD_CEC_IC
VDD_CEC
decoupling
capacitance
Enable
IEC61000-4-2
RPU_CEC_IC
Ctrl
circuit
HBM
CEC_IC
Anti back drive
diode
decoupling
capacitance
CEC
driver
HDMI
connector
VDD_CEC
UVLO
1
3
RPU_CEC_BUS
VDD_CEC_IC
5
7
9
11
CEC
13
15
17
19
2
4
6
8
10
12
14
16
18
In case of no activity on the CEC bus, or if the CEC driver is off (VDD_CEC_IC = 0), the CEC
pin is put in high impedance mode (open circuit) protecting the circuitry and the application
against hazardous back drive.
The Figure 4 illustrates the normal operating mode of the CEC block when the IC from the
source and when the sink drives the communication.
Figure 4. Simplified view of the electrical parameters of the CEC block
CEC_IC
CEC_IC
VDD_CEC_IC
ASIC side
VDD_CEC_IC
VIH_CEC_IC
VIL_CEC_IC
t
t
CEC
CEC
VDD_CEC
VDD_CEC
Cable side
90%
VTup_CEC
VHYST_CEC
VTdown_CEC
10%
Block in high
impedance
tFALL_CEC
t
Block in high
impedance
Level shifting
Source IC drives
tRISE_CEC
DocID023674 Rev 2
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Block in high
impedance
Level shifting
Block in high
impedance
Sink drives through HDMI cable
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Application information
HDMI2C1-14HD
In case the application is set in stand-by mode, the +5 V main supply of the application is
generally powered off in order to reduce as much as possible the global power
consumption. The CEC driver can be the only device still working in low power mode,
allowing a wake up of the whole application through the CEC line. When the main power
supply +5 V is switched off, and if the CEC bus is still active (VDD_CEC power in on state),
the HDMI2C1-14HD keeps the CEC bus working properly while all other outputs of the
component are put in high impedance mode.
The CEC output (cable side) integrates a protection against ESD which is compliant with
IEC61000-4-2 standard, level 4 (8kV contact).
2.2
DDC functional block description
The DDC bus is described in the HDMI™ standards as the Display Data Channel. The
topology corresponds to an I2C bus that must be compliant with the I2C bus specification
version 5 (October 2012). The DDC bus is made of 2 lines: data line (SDA) and clock line
(SCL). It is used to create a point to point communication link from the source to the sink.
EEDID and HDCP protocols are flowing through this link, making this I2C communication
channel a key element in the HDMI™ application.
The DDC block integrated in the HDMI2C1-14HD allows a bidirectional communication
between the cable and the ASIC. It is fully compliant with the HDMI™ 2.0 standard and its
CTS, and with the I2C bus specification version 2.1. It is shifting the 5V voltage from the
cable (V5V_OUT) down to the ASIC voltage level (VDD_IC) that can be as low as 1.8 V. The
Figure 5 shows the functional diagram of the DDC block integrated in the HDMI2C1-14HD
device.
Figure 5. DDC bus functional diagram (SCL and SDA lines)
VDD_IC
+5V
decoupling
capacitance
VDD_5V
VDD_IC
5V_OUT
1
RPU_ASIC
3
UVLO
Enable
11
13
15
17
SCL_IC
SDA_IC
SCL
SDA
IEC61000-4-2
HBM
reshaping
circuit
Drive
19
DocID023674 Rev 2
8
10
12
14
16
18
HDMI
connector
The Figure 6 illustrates the electrical parameter of the DDC block specified in Table 8.
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6
9
RPU_BUS
VDD_5V
5
7
dynamic pull -up
HDMI
ASIC
2
4
5V_OUT
HDMI2C1-14HD
Application information
Figure 6. Simplified view of the electrical parameters of the DDC block
ASIC side
SDA_IC
VDD_IC
Vtup_IC
V Tdown_IC
t
SDA
Cable side
5V_OUT
70%
Vtup_BUS
V Tdown_BUS
V HYST_BUS
30%
t
T FALL_BUS
T RISE_BUS
Source IC drives
Sink drives through HDMI cable
The HDMI™ standard specifies that the max capacitance of the cable can reach up to 700
pF. Knowing that the max capacitance of the sink input can reach up to 50 pF, this means
that the I2C driver must be able to drive a load capacitance up to 750 pF. On the other hand,
the I2C standard specifies a maximum rise time of the signal must be lower than 1 µs in
order to keep the signal integrity. Taking into account the max cable capacitance of 750 pF,
it is not possible to guarantee a rise time lower than 1 µs in worst case. Therefore, a
dynamic pull-up has been integrated at the output of SDA and SCL lines and synchronized
with the I2C driver. This signal booster accelerates for a short period the charging time of
the equivalent cable capacitance, allowing to drive any HDMI™ cable. The Figure 7
illustrates the benefit of the dynamic pull-up integrated in the HDMI2C1-14HD device.
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Application information
HDMI2C1-14HD
Figure 7. Benefit of the dynamic pull-up on the DDC bus
I2C driver with dynamic pull-up
I2C driver without dynamic pull-up
5V_OUT
5V_OUT
dynamic pull -up
RPU_BUS
logical
circuitry
synchronized
with I2C bus
750pF
RPU_BUS
750pF
HDMI™ cable model
HDMI™ cable model
IC control
VDD_IC
IC control
VDD_IC
Signal on the cable
Signal on the cable
5V_OUT
5V_OUT
Rise time out of I2C specification
Risk of communication failure
Rise time compliante with I2C specification
Signal integrity OK even on 750 pF load capacitance
In order to activate the DDC block, the VDD_5V has to reach the specified VDD_5V_ON
threshold (see Table 4). In addition, the inputs and outputs of the bidirectional level shifters
(SCL, SDA, SCL_IC, SDA_IC) must be set to a high level after the power-on, and the HPD
line has to be activated one time.
The DDC outputs (SCL and SDA on cable side) integrate a protection against ESD which is
compliant with IEC61000-4-2 standard, level 4 (8 kV contact).
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HDMI2C1-14HD
2.3
Application information
HEAC link and HPD line description
The HDMI2C1-14HD proposes a unique solution in order to manage and protect both the
HEAC and the HPD links. The Figure 8 shows an overview of the function diagram of the
integrated block.
Figure 8. HEAC / HPD / Utility functional block diagram
decoupling
capacitance
VDD_IC
HDMI
connector
VDD_IC
HPD
or
IC
HPD / HEAC-
1
3
IEC61000-4-2
HPD_IC
HBM
HDMI
ASIC
7
11
13
15
Utility
IEC61000-4-2
matching
6
8
9
HEAC HEAC+
2
4
5
17
Utility / HEAC+
19
10
12
14
16
18
This block simplifies the design and the PCB layout of the HPD and HEAC functions. Simply
connect the 2 pins from the HDMI connector to one side of the device, and then use the 3
dedicated outputs on the other side of the device to manage separately the HPD and the
HEAC links.
Both HPD and Utility inputs (cable side) integrate a protection against ESD which is
compliant with IEC61000-4-2 standard, level 4 (8 kV contact).
2.3.1
HPD line description
The HPD line is described in the HDMI™ standards as the Hot Plug Detect function. This
line is used by the Source device in order to detect if a Sink device is connected through an
HDMI cable.
The integrated HPD block is pulling down the line via a current source. When the input
voltage is detected to be higher than a threshold level VTH_HPD, the signal is converted into
a high state level on the ASIC side, at the voltage level of the ASIC power supply VDD_IC.
Otherwise, HPD_IC pin remains in low state.
The electrical parameters relevant to the HPD block and specified by theTable 7 are
illustrated in the Figure 9.
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Application information
HDMI2C1-14HD
Figure 9. Simplified view of the electrical parameters of the HPD block
Signal on HPD link
5V
VIH_HPD
VIL_HPD
HPD_IC signal
2.3.2
HEAC functional block description
The HEAC link is described in the HDMI™ 1.4 and HDMI™ 2.0 standards as the HDMI™
Ethernet and audio return channel. It corresponds physically to one differential wired pair
made of the Utility line and the HPD line. Two signals are transmitted through this link.
The first signal corresponds to the HDMI™ Ethernet channel (HEC). The signal is
transmitted in differential mode (bidirectional) through the HEAC link. It is specified by the
100Base-TX IEEE 802.3 standard (fast Ethernet 100Mbps over twisted pair). Therefore, the
HEC integrates an Ethernet link into the video cable, enabling IP-based applications over
the HDMI™ cable.
The second signal corresponds to the Audio Return Channel (ARC). The signal is
transmitted either in common mode (unidirectional, from sink to source) through the HEAC
link. It is specified by the IEC 60958-1 standard. The ARC function integrates an upstream
audio capability, simplifying the cabling of the audiovisual equipment. It is no more
necessary to use a coaxial cable from TV to audio amplifier.
The HDMI2C1-14HD helps the designer to implement this high added value HEAC function
in the application, protecting the link against the ESD with no disturbance of the signal. It
provides 2 distinct outputs HEAC+ and HEAC- in order to ease as much as possible the
PCB layout.
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HDMI2C1-14HD
+5V protection and fault line functional block description
The +5 V power supply that the source device has to provide to the HDMI™ cable is
described by the HDMI™ 2.0 standard. It must be protected against accidental short circuit
that could occur on the cable side.
The HDMI2C1-14HD device embeds a low drop current limiter. If an over-current is
detected, the HDMI2C1-14HD limits the current through the +5 V power supply.If the current
is too high (short circuit), the device opens the +5 V.
Furthermore, the HDMI2C1-14HD device embeds also an over temperature protection
(OTP). If the internal temperature of the device reaches a too high value, the +5 V supply is
opened in order to protect the application.
In case either the current limiter or the OTP is triggered, the fault pin switches down to low
state level (open drain topology) in order to optionally inform the HDMI™ ASIC that an
abnormal situation has been detected (option).
An under voltage lockout (UVLO) is also integrated in the block. It checks the main +5 V
power supply state, and enables the 5V_OUT only if the main power supply has reached a
minimal value VDD_5V_ON.
The Figure 10 shows the functional diagram of the current limiter block.
Figure 10. +5 V functional diagram
HDMI
connector
5V
OTP
UVLO
3
decoupling
capacitance
HBM
VDD_IC
1
+5V_OUT
Low drop current limiter
Current
sensor
IEC61000-4-2
VDD_5V
decoupling
capacitance
7
Ctrl
RPU_FAULT
11
15
17
FAULT
6
8
9
13
HDMI
ASIC
2
4
5
19
10
12
14
16
18
or
IC
HBM
2.4
Application information
To summarize, the short circuit protection and the over temperature protection features are
providing a high robustness level of the application. On top of this, the fault line can be used
in order to improve the user experience.
The 5V_OUT pin integrates a protection against ESD which is compliant with IEC61000-4-2
standard, level 4 (8 kV contact). The decoupling capacitance is mandatory, according to the
power management state of the art.
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Application information
2.5
HDMI2C1-14HD
Back drive protection
Figure 11. Back drive current diagram
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Thanks to the innovative switch architecture, back drive current is blocked whatever back
drive current is coming from +5V_OUT and/or DDC lines (see figure 11).
In case of no activity on CEC bus, or if the CEC driver is off (VDD_CEC = 0), the output CEC
pin is put in high impedance mode (open circuit) protecting the circuitry and the application
against hazardous back drive.
2.6
TMDS channels ESD protection
The TMDS (Transient Minimized Differential Signaling) channels are described by the HDMI
2.0 standard. A total of 4 unidirectional differential pairs are used to transmit the video data
to the sink device. There are 3 channels dedicated to the video data, and 1 channel
dedicated to the clock.
The HDMI2C1-14HD provides a simple PCB layout solution, directly compliant with HDMI
connector type A. It protects the application against the ESD according the IEC61000-4-2
level 4 standard (+/-8 kV contact). The high bandwidth of this ESD protection allows to
transmit HD video data with no disturbance of the signal up to 5.94 Gbps per channel.
A capacitor can be optionally connected to the ESD_DISCH pin in order to enhance the
ESD protection performances.
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HDMI2C1-14HD
Application information
Figure 12. TMDS lines ESD protection functional diagram
5V_OUT
HDMI
connector
VDD_IC
HDMI
ASIC
DAT_D2+_IC
DAT_D2+
DAT_D2 -_IC
DAT_D2 -
DAT_D1+_IC
DAT_D1+
5
DAT_D1-_IC
DAT_D1-
7
DAT_D0+_IC
DAT_D0+
11
DAT_D0 -_IC
DAT_D0 -
13
DAT_CLK+_IC
DAT_CLK+
DAT_CLK- _IC
DAT_CLK
-
1
3
2
4
6
8
9
15
17
19
10
12
14
16
18
IEC61000-4-2
ESD_DSICH
Application block diagrams
The Figure 13 shows an application block diagram proposal, implementing all the possible
options. The TMDS channels are simply connected to the connector and to the source
HDMI ASIC. The diagram shows that the CEC driver can be totally independent from the
HDMI ASIC. By this way, even if the +5 V power supply and/or if the HDMI ASIC is sleeping
in stand-by mode, the CEC bus is still active in low power mode. The designer has then all
the tools to optimize the power consumption of the global application in stand-by mode, and
has the possibility to implement a smart wake-up through the CEC bus enhancing the final
user experience.
Figure 13. Application block diagram
VDD_IC
HDMI2C1 -14HD
4 TMDS channels
8 lines
TMDS
lines IN
ESD_DISCH
C6
+5V
TMDS data 2+
TMDS data- 2
TMDS data 1+
TMDS data
- 1
TMDS data 0+
TMDS data
- 0
TMDS Clock+
TMDS Clock
-
TMDS
lines OUT
+5V power
5V_OUT
VDD_5V
R7
C3
C4
C2
VDD_IC
over current
detect
R3 R2
FAULT
HPD
HPD_IC
VDD_IC
HPD
HPD / HEAC-
SDA
R4
R5
DDC data
SDA_IC
SDA
DDC clock
SCL_IC
SCL
HEAC-
HEAC-
VDD_CEC_IC
Utility / HEAC+
VDD_CEC
VDD_CEC_IC
R6
CEC
driver
SCL
Utility
HEAC+
HEAC+
HDMI connector
VDD_IC
HDMI ASIC
2.7
VDD_CEC
C5
D1
C1
CEC_IC
CEC
R1
CEC bus
GND
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Application information
HDMI2C1-14HD
Table 1. Block diagrams references
Ref.
Typical values
R1
27 k
Pull-up resistance on CEC bus, specified by the HDMI standard
R2, R3
1.8 k
Pull-up resistances on DDC bus, specified by the HDMI standard
R4, R5
10 k
Pull-up resistance on DDC bus, ASIC side, value selected to be
compliant with I2C levels
R6
Note:
Comment
270 kto Pull-up resistance on CEC line, ASIC side
R7
10 k
Pull-up resistance on FAULT line (option)
D1
BAT54
Small Schottky diode blocking back drive current flowing toward the
VDD_CEC supply
C1 to C5
100 nF
Decoupling capacitance on power supplies
C6
1 µF
ESD protection enhancement capacitance (option)
SCL_IC, SDA_IC, and CEC_IC have to be driven with an ASIC working with open drain
outputs.
Figure 14. PCB layout example
VDD_CEC_IC
R6
CEC
driver
VDD_CEC
VDD_IC
DDC data
4 TMDS channals, 8 lines
HDMI ASIC
C6
nc
C5
C1
C2
SCL_IC
VDD_CEC
SDA_IC
VDD_5V
HPD_IC
5V_OUT
HDMI connector type A
TMDS Data2+
ESD_DISCH
nc
TMDS Data2 Shield
DAT_D2+_IC
DAT_D2+
DAT_D2 -_IC
DAT_D2-
DAT_D1+_IC
DAT_D1+
TMDS Data2 TMDS Data1+
GND
TMDS Data1 Shield
DAT_D1 - _IC
DAT_D1-
DAT_D0+_IC
DAT_D0+
DAT_D0 -_IC
DAT_D0 -
DAT_CK+_IC
DAT_CK+
DAT_CK- _IC
DAT_CK -
TMDS Data1 TMDS Data0+
TMDS Data0 Shield
TMDS Data0 TMDS Clock+
TMDS Clock Shield
TMDS Clock -
CEC
SCL
Utility
SDA
D1 R1
HPD
HEAC-
HEAC+
VDD_CEC
HEAC+
HEAC -
C4
VDD_CEC_IC
R7
FAULT
R4
VDD_IC
R5
CEC_IC
fault detect
DDC clock
5V_OUT
VDD_5V
VDD_CEC_IC
C3
CEC
Utility / HEAC+
SCL
SDA
5V_OUT
R3
R2
DDC/CEC GND / HEAC shield
+5V power
HPD / HEAC -
The Figure 14 illustrates the fact that the HDMI2C1-14HD pin configuration eases and
optimizes the PCB layout of the HDMI interface. The proposed pin-out sequence is directly
compliant with HDMI connector type A.
14/32
DocID023674 Rev 2
HDMI2C1-14HD
Application information
Table 2. Pin description
Pin
Name
Description
Pin
Name
1
SDA_IC
DDC input ASIC side
19
DAT_CK-
TMDS output Clock CK-
2
HPD_IC
HPD output ASIC side
20
DAT_CK+
TMDS output Clock CK+
3
ESD_DISCH
ESD protection enhancement
capacitance
21
DAT_D0-
TMDS output Data D0-
4
DAT_D2+_IC
TMDS input Data D2+
22
DAT_D0+
TMDS output Data D0+
5
DAT_D2-_IC
TMDS input Data D2-
23
DAT_D1-
TMDS output Data D1-
6
DAT_D1+_IC
TMDS input Data D1+
24
DAT_D1+
TMDS output Data D1+
7
DAT_D1-_IC
TMDS input Data D1-
25
DAT_D2-
TMDS output Data D2-
8
DAT_D0+_IC
TMDS input Data D0+
26
DAT_D2+
TMDS output Data D2+
9
DAT_D0-_IC
TMDS input Data D0-
27
NC
10
DAT_CK+_IC TMDS input Clock CK+
28
5V_OUT
+5V power supply HDMI cable side
11
DAT_CK-_IC
TMDS input Clock CK-
29
VDD_5V
+5V main power supply
12
HEAC+
HEAC+ output ASIC side
30
VDD_CEC
13
HEAC-
HEAC- output ASIC side
31
VDD_CEC_IC
14
HPD
HPD/HEAC- input HDMI
cable side
32
NC
15
SDA
DDC output HDMI cable side
33
VDD_IC
HDMI ASIC power supply
16
SCL
DDC output HDMI cable side
34
FAULT
Fault line output ASIC side
17
Utility
Utility/HEAC+ input HDMI
cable side
35
CEC_IC
CEC input ASIC side
18
CEC
CEC output HDMI cable side
36
SCL_IC
DDC input ASIC side
Pad
GND
DocID023674 Rev 2
Description
not connected
CEC supply HDMI cable side
CEC driver power supply
not connected
Ground
15/32
32
Application information
HDMI2C1-14HD
9''B, &
6'$B, &
9''B9
9B287
'$7B'B, &
'$7B' B,&
'$7B&. B,&
DocID023674 Rev 2
&(&
'$7B&.B, &
8WLOLW \
'$7B' B,&
6&/
'$7B'B, &
6'$
'$7B' B,&
*1'
+3'
'$7B'B, &
+($ &
(6'B',6&+
+($ &
+3'B, &
16/32
9''B&(&
)$8/7
9''B&(&B, &
&(&B, &
3LQ
QF
6&/B, &
Figure 15. Pin numbering
QF
'$7B'
'$7B'
'$7B'
'$7B'
'$7B'
'$7B'
'$7B&.
'$7B&.
HDMI2C1-14HD
3
Electrical characteristics
Electrical characteristics
Table 3. Absolute maximum ratings (limiting values)
Symbol
Parameter
Test conditions
Value
Unit
Vpp_BUS
ESD discharge on HDMI BUS side (pin 14 to 26, and pin
Contact discharge
28), IEC 61000-4-2 level 4
±8(1)
kV
Vpp_IC
ESD discharge (all pins), HBM JESD22-A114D level 2 Contact discharge
±2
kV
Tstg
Storage temperature range
-55 to +150
°C
Top
Operating temperature range
-40 to +85
°C
TL
Maximum lead temperature
260
°C
6
V
-0.3 to 6
V
VDD_5V
VDD_IC
Supply voltages
VDD_CEC
VDD_CEC_IC
Inputs
Logical input min/max voltage range
1. With a 100 nF capacitor connected to the 5V_OUT pin.
Table 4. Power supply characteristics (Tamb = 25 °C)
Symbol
Parameter
VDD_CEC
VDD_CEC_IC
VDD_IC
Test conditions
Min. Typ. Max.
CEC supply voltage, bus side
2.97
CEC supply voltage, IC side
Low-voltage ASIC supply voltage
3.3
Unit
3.63
V
1.62
3.63
V
1.62
3.63
V
5 V input supply voltage range
4.9
5.0
5.3
V
+5 V power on reset
3.5
3.8
4.1
V
VDD_CEC_ON CEC power on reset
2.6
2.8
2.95
V
VDD_5V
VDD_5V_ON
(1)
IQS_5V
IQS_IC
IQS_CEC
Quiescent currents on VDD_5V,
VDD_IC, VDD_CEC, VDD_CEC_IC
IQS_CEC_IC
Back drive current for 5V_OUT,
SDA, SCL, HPD
tested pin = 5 V
Rth
Junction to ambient thermal
resistance
Copper heatsink as shown by
Figure 28
TSD
Thermal Shutdown threshold
ILEAK
PTOTAL_SB
Standby conditions
600
VDD_5V = 5 V, VDD_IC = 1.8 V,
VDD_CEC = 3.3 V
VDD_CEC_IC = 1.8 V
Idle-state on CEC and DDC links,
HPD and 5V_OUT links open
75
µA
200
40
VDD_5V = 0 V, VDD_IC = 0 V,
1
75
120
VDD_5V = VDD_IC = 0V
VDD_CEC = 3.3V
VDD_CEC_IC = 3.3V
DocID023674 Rev 2
µA
°C/W
150
°C
0.8
mW
17/32
32
Electrical characteristics
HDMI2C1-14HD
1. In order to activate the DDC functional block, the 3 following conditions have to be met:
- VDD_5V has to reach the VDD_5V_ON threshold
- The inputs and outputs of the bidirectional level shifter must be set to a high level after the power-on
- The HPD line has to be activated one time
Table 5. CEC electrical characteristics(1)
Symbol
VTup_CEC
Parameter
Test conditions
Min. Typ. Max.
Upward input voltage threshold on bus side
2.0
VTdown_CEC Downward input voltage threshold on bus side
0.8
VHYST_CEC Input hysteresis on bus side
TRISE_CEC
Output rise-time (10% to 90%)
TFALL_CEC
Output fall-time (90% to 10%)
IOFF_CEC
VIL_CEC_IC
RUP_CEC = 14.1 k(2)
CCEC_CABLE = 7.9 nF(2)
VDD_5V = 0 V
VDD_IC = 0 V,
VDD_CEC = 3.3 V
Input low level on IC side
RON_CEC
CIN_CEC
1.
V
250
µs
50
µs
1.8
µA
0.5
VIH_CEC_IC Input high level on IC side
V
VIH_CEC_IC = 1.8 V
1.5
VIH_CEC_IC = 3.3 V
1.9
V
On resistance across CEC and CEC_IC pins CEC pin to 0 V
VDD_5V = 0 V
VDD_CEC = 0 V
VDD_IC = 0 V
VBIAS = 0 V, f = 1 MHz,
VOSC = 30 mV
Input capacitance on CEC link
V
V
0.4
Leakage current in powered-off state
Unit
100
25(3)
pF
Tamb = 25 °C, VDD_CEC = 3.3 V, VDD_CEC_IC = 1.8 V, unless otherwise specified
2. Test conditions are compliant with worst case CEC specification:
- Correspond to two 27 k +5% pull-up resistances in parallel (compliant with HDMI CTS)
- Max capacitance corresponding to 9 equipment chained on the CEC bus
3. Maximum capacitance allowed at connector output is 200 pF in HDMI 1.4 specification
Table 6. 5V_out current limiter electrical characteristics(1)
Value
Symbol
Parameter
Unit
Min.
Typ.
Max.
I5V_OUT = 55 mA
20
50
95(2)
mV
Output current
V5V_OUT = 0 V
55
115
mA
Low level on FAULT pin
RPU_FAULT = 10 k
0.3
V
VDROP
Drop-out voltage
I5V_OUT
(3)
VL_FAULT
Test conditions
1. Tamb = 25°C, VDD_5V = 5 V, unless otherwise specified
2. HDMI 1.4 specification requires a maximum of 100 mV voltage-drop
3. HDMI 1.4 standard specifies a minimal current capability of 55 mA, and an over-current protection of no more than 500 mA
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HDMI2C1-14HD
Electrical characteristics
Table 7. HPD, HEAC, and utility line electrical characteristics(1)
Value
Symbol
Parameter
Test conditions
Unit
Min.
IPULL_DOWN Pull-down current in HPD block
VTH_HPD
HPD input threshold
CIN_HPD
CIN_UTILIT Input capacitance
Y
fCUT_HEAC
Typ.
Max.
15
25
µA
1.7
V
1.0
VDD_5V = 0 V, VBIAS = 0 V
f = 1 MHz, VOSC = 30 mV
Cut-off frequency of HEAC bus
9
pF
500
MHz
1. Tamb = 25°C, VDD_5V = 5 V, unless otherwise specified.
Table 8. DDC bus (SDA and SCL lines) electrical characteristics(1)
Value
Symbol
Parameter
Test conditions
Unit
Min.
VTup_BUS
Upward input voltage threshold on bus side
3.5
VTdown_BUS Downward input voltage threshold on bus side
1.5
VHYST_BUS Input hysteresis on bus side
1.0
V
V
1.3
V
Output low level
Current sunk by SDAand SCL
pin is 3 mA
0.35
V
TRISE_BUS
Output rise-time (30% to 70%)
CBUS = 750 pF(2)
RUP = 2 K //47 K + 10%(3)
500
ns
TFALL_BUS
Output fall-time (30% to 70%)
50
ns
VOL_BUS
VTup_IC
Upward input voltage threshold on IC side
55
60
65
%VDD_IC
VTdown_IC
Downward input voltage thresholds IC side
35
40
45
%VDD_IC
20
%VDD_IC
17(4)
pF
VOL_IC
CIN_DDC
1.
Typ. Max.
Output low level on IC side
Current sunk by SDA_IC or
SCL_IC pins is 500 µA
Input capacitance on DDC link
VDD_5V = 0 V
VDD_IC = 0 V
VDD_CEC = 0 V
VBIAS = 0 V, f = 1 MHz
VOSC = 30 mV
9
Tamb = 25 °C, VDD_5V = 5 V, VDD_IC = 1.8 V, unless otherwise specified
2. Maximum load capacitance allowed on I2C entire link (cable + connector) is 750 pF in HDMI 1.4 specification.
3. Two pull-up resistors in parallel (sink 47 k+ source 2 k).
4. Maximum capacitance allowed at connector output is 50 pF in HDMI 1.4 specification
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32
Electrical characteristics
HDMI2C1-14HD
Table 9. TMDS links electrical characteristics(1)
Value
Symbol
Parameter
Test conditions
Unit
Min.
fCUT_TMDS
Bandwidth at - 3dB
VBR
Breakdown voltage
IRM
Leakage current
CI/O-GND
Single Ended mode
4.7(2)
Differential mode
6.5(2)
Max.
GHz
6
V
VRM = 3.3 V
Capacitance input/output to
VI/O=0 V, f=1 MHz, VOSC=30 mV
ground
100
nA
1.5
pF
Clamping voltage
IPP= 16 A, IEC61000-4-2, I/O to GND,
ESD_DISCH = 1 µF
10
V
CI/O-GND
Capacitance variation
VI/O = 0V, f=1 MHz, VOSC=30 mV
50
fF
ZDIFF
Differential impedance
tr = 200ps (10%-90%)
Z0DIFF=100
VCL
1.
Typ.
85
100
115
Tamb =25°C, VDD_5V = 5V, unless otherwise specified
2. The bandwidth is large enough to operate up to 340 MHz as HDMI clock frequency, corresponding to 10.2 Gbps total data
rate, 3.4 Gbps on each lane
Figure 16. TMDS line S21 frequency curve
S dd21
S21(dB)
0
-3
-6
S cc21
-9
-12
F(Hz)
-15
100k
20/32
1M
10M
100M
DocID023674 Rev 2
1G
HDMI2C1-14HD
Electrical characteristics
Figure 17. TMDS line differential far end crosstalk curve
0
dB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
F(Hz)
-120
-130
10M
30M
100M
300M
1G
D2-D1_FEXT
3G
10G
D2-CLK_FEXT
Figure 18. TMDS line: remaining voltage when positive 8 kV ESD surge applied
20 V/div
100.9 V
1
1 VPP: ESD peak voltage
2 VCL :clamping voltage @ 30 ns
3 VCL :clamping voltage @ 60 ns
4 VCL :clamping voltage @ 100 ns
13.1 V
2
11.7 V
3
7.5 V
4
20 ns/div
Figure 19. TMDS line: remaining voltage when negative 8 kV ESD surge applies
20 V/div
-4.8 V
3.3 V
-67.9 V
2
-5.1 V
4
3
1
1 VPP: ESD peak voltage
2 VCL :clamping voltage @ 30 ns
3 VCL :clamping voltage @ 60 ns
4 VCL :clamping voltage @ 100 ns
20 ns/div
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Electrical characteristics
HDMI2C1-14HD
Figure 20. Eye diagram of TMDS line: D0, D1, D2 and CLK lanes (1.485 Gbps)
250 mV/div
112.2 ps/div
Figure 21. Eye diagram of TMDS line: D0, D1, D2 and CLK lanes (3.350 Gbps)
250 mV/div
49.8 ps/div
Figure 22. TDR of TMDS lines: D0, D1, D2, CLK lanes
TDR rise time (10%-90%): 200ps
100 Ω
89.8 Ω
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Electrical characteristics
Figure 23. CEC typical waveforms (source to sink communication)
C2 = 1.00 V/div
C3 = 500 m V/div
100 µs/div
Figure 24. CEC typical waveforms (sink to source communication)
C2 = 1.00 V/div
C3 = 500 m V/div
100 µs/div
Figure 25. DDC typical waveforms (sink to source communication)
C2 = 1.00 V/div
C3 = 500 m V/div
2 µs/div
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32
Electrical characteristics
HDMI2C1-14HD
Figure 26. DDC typical waveforms (source to sink communication)
C2 = 1.00 V/div
C3 = 500 m V/div
2 µs/div
Figure 27. HPD typical waveforms (timing)
C2 = 1.00 V/div
C3 = 500 m V/div
1 µs/div
Figure 28. HEAC single ended mode typical bandwidth
0
dB
-3
-6
-9
-12
-15
F(Hz)
-18
100k
24/32
1M
HEAC
-
10M
f/Hz
DocID023674 Rev 2
100M
1G
10G
HDMI2C1-14HD
4
Package information
Package information
Epoxy meets UL94, V0
Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1
QFN package information
Figure 29. QFN package outline
DocID023674 Rev 2
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32
Package information
HDMI2C1-14HD
Table 10. QFN package mechanical data
Dimensions
Ref.
Inches(1)
Millimeters
Typ.
Min.
Max.
Typ.
Min.
Max.
A
0.85
0.90
0.95
0.033
0.035
0.037
A1
0.00
0.05
0.000
b
0.18
0.25
0.30
0.007
0.010
0.012
D
3.40
3.50
3.60
0.134
0.137
0.141
D2
2.25
2.30
2.35
0.088
0.090
0.092
E
6.40
6.50
6.60
0.251
0.255
0.259
E2
5.25
5.30
5.35
0.206
0.208
0.210
e
0.50
0.002
0.020
La
0.00
0.10
0.20
0.00
0.004
0.008
Lb
0.15
0.25
0.30
0.006
0.01
0.012
Lc
0.20
0.30
0.40
0.008
0.012
0.016
ddd
0.09
0.003
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 30. QFN footprint recommendation (dimensions in mm)
3,1 1&
3,1 1&
3,1
26/32
DocID023674 Rev 2
HDMI2C1-14HD
4.2
Package information
Packing information
Figure 31. Marking specification
2C1-14HD
CCC
Y
WW
e3
G
WX
CCC : Country of origin
Y : Assy Year
W W : Assy Week
G : Eco Level
W X : Diffusion traceability
Figure 32. Tape and reel outline
2.0
∅1.55
4.0
1.75
7.5
16.0
6.75
∅1.5
0.9
All dimension in mm
3.75
8.0
User direction of unreeling
DocID023674 Rev 2
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32
Recommendation on PCB assembly
HDMI2C1-14HD
5
Recommendation on PCB assembly
5.1
Stencil opening design
1.
General recommendation on stencil opening design
a)
Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 33. Stencil opening dimensions
L
T
b)
W
General design rule
Stencil thickness (T) = 75 ~ 125 µm
W
Aspect Ratio = ----- 1,5
T
LW
Aspect Area = ---------------------------- 0,66
2T L + W
2.
Reference design
a)
Stencil opening thickness: 100 µm
b)
Stencil opening for central exposed pad: Opening to footprint ratio is 50%.
c)
Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 34. Recommended stencil window position
300 µm
13 µm
474 µm
500 µm
7 µm
286 µm
0.23
0.50
0.30
0.50
0.25
2.30
5.3 mm
300 µm
2.3 mm
1.7 mm
5.30
0.25
750 µm
3.8 mm
Stencil window
Footprint
28/32
DocID023674 Rev 2
0.45
HDMI2C1-14HD
5.2
5.3
5.4
Recommendation on PCB assembly
Solder paste
1.
Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste recommended.
3.
Offers a high tack force to resist component displacement during PCB movement.
4.
Use solder paste with fine particles: powder particle size 20-45 µm.
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Standard tolerance of ± 0.05 mm is recommended.
4.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB is recommended during solder paste
printing, pick and place and reflow soldering by using optimized tools.
PCB design preference
1.
To control the solder paste amount, closed vias are recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced.
Symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
DocID023674 Rev 2
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32
Recommendation on PCB assembly
5.5
HDMI2C1-14HD
Reflow profile
Figure 35. ST ECOPACK® recommended soldering reflow profile for PCB mounting
240-245 °C
Temperature (°C)
250
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
Note:
30/32
30
60
90
120
150
180
210
240
270
300
Minimize air convection currents in the reflow oven to avoid component movement.
DocID023674 Rev 2
HDMI2C1-14HD
6
Ordering information
Ordering information
Figure 36. Ordering information scheme
HDMI2C
1
-
14
HD
HDMI and I2C compliant links
HDMI port type
1: source ports
Number of protected links
14 lines protected according to IEC 6100-4-2
Version
HD: Full speed of HDMI supported
Table 11. Ordering information
7
Order code
Marking
Package
Weight
Base qty
Delivery mode
HDMI2C1-14HD
2C1-14HD
QFN
51,6 mg
4,000
Tape and Reel
Revision history
Table 12. Document revision history
Date
Revision
Changes
23-Jan-2013
1
Initial release
04-May-2015
2
Updated Features, Applications, Description and Figure 30. Added
Figure 2 and Back drive protection. Updated Table 1, Table 4,Table 9
and reformatted to current standard.
DocID023674 Rev 2
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32
HDMI2C1-14HD
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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DocID023674 Rev 2
