HDMI2C1-14HDS
ESD protection and signal conditioning
for HDMI™ 2.0 and HDMI™ 1.4 source
Datasheet − production data
Benefits
• Speed-up hardware design and certification of
HDMI application
1
18
• Pin map sequence compliant with HDMI
connector type A
2
17
• Minimal PCB footprint in consumer area
16
• Ultra low power consumption in stand-by mode
24
3
23
22
21
20
19
Exposed thermal die
4
15
5
14
6
13
7
8
9
10
11
• Wake-up from stand-by through CEC bus
• Improved HDMI interface ruggedness and user
experience
• Long and/or poor quality cable support
12
Complies with the following standards
• HDMI standard
• IEC 61000-4-2 level 4
• JESD22-A114D level 2
Features
• HDMI compliant from -40 to 85 °C
Applications
• 8 kV contact ESD protection on connector side
• Consumer and computer electronics HDMI
Sink device such as:
– HD set-top boxes
– DVD and Blu-Ray Disk systems
– Notebook
– PC graphic cards
• Supports direct connection to low-voltage
HDMI ASIC and/or CEC driver (down to 1.8 V)
• TMDS high bandwidth ESD protection
compatible with 4 K-2 K 60 fps.
• DDC (I2C) link protection, bi-directional signal
conditioning circuit, and dynamic pull-up
•
CEC bus protection, bi-directional level-shifter,
backdrive protection, and independent
structure from main power supply
Description
• HEAC link protection
• HPD pull down and signal conditioning
The HDMI2C1-14HDS is a fully integrated ESD
protection and signal conditioning device for
control links of HDMI transmitters (Source).
• Short-circuit protection on 5 V output
• Over temperature protection
• Proposed in QFN 24 leads 500 μm pitch
September 2015
This is information on a product in full production.
HDMI ™ : the HDMI logo and high definition
multimedia interface are trademarks or registered
trademarks of HDMI Licensing LLC.
The HDMI2C1-14HDS is a simple solution that
provides HDMI designers with an easy and fast
way to reach full compliancy with the stringent
HDMI CTS on a wide temperature range.
DocID025842 Rev 3
1/28
www.st.com
HDMI2C1-14HDS
Contents
1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
CEC line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
DDC bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
HEAC link and HPD line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1
HPD line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2
HEAC link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
+5V protection and fault line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
TMDS channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.6
Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
4.1
QFN package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Recommendation on PCB assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
Stencil opening design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
Solder paste . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3
Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4
PCB design preference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5
Reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
DocID025842 Rev 3
HDMI2C1-14HDS
Functional description
The HDMI2C1-14HDS is a fully integrated ESD protection and signal conditioning device for
control links and TMDS data video channels of HDMI transmitters (Source).
The control stage provides a bidirectional buffer, integrating signal conditioning and dynamic
pull-up on DDC bus for maximum system robustness and signal integrity. The HEAC (HDMI
Ethernet and Audio return Channels) function is supported, making the component fully
compliant with HDMI version. A bidirectional CEC block is integrated, able to wake-up the
application from stand-by mode (all power supply off, except the CEC power supply). The
integrated TMDS links ESD protection allows a video data rate up to 10.2 Gbps,
corresponding to the maximal speed specified by the HDMI standard. All video format
specified by HDMI standard (up to 1080p60) are supported, giving maximal flexibility to
designers. The +5 V supplied to the cable is protected against accidental surge current and
short circuit. All these features are provided in a single 24 leads QFN package saving space
on the board.
The HDMI2C1-14HDS is a simple solution that provides HDMI designers with an easy and
fast way to reach full compliancy with the stringent HDMI CTS on a wide temperature range.
9''B,&
9''B&(&B,&
9''B9
9B287
9''B&(&
&(&
Figure 1. Pin out, top view
)$8/7B,&
'$7B'
&(&B,&
'$7B'
6&/B,&
'$7B'
6'$B,&
'$7B'
+3'B,&
'$7B'
87,/,7<
'$7B'
6'$
6&/
&.
&.
1&
*1'
+3'
1
Functional description
DocID025842 Rev 3
3/28
28
Application information
HDMI2C1-14HDS
2
Application information
2.1
CEC line description
The CEC bus is described in the HDMI standards as the consumer electronics control. It
provides control functions between all the various audiovisual equipment chained in the
user's environment.
The CEC block integrated in the HDMI2C1-14HDS implements a level shifter, shifting the
cable CEC line from +3.3 V CEC voltage (VDD_CEC) down to the ASIC power supply voltage
(VDD_IC) that can be as low as 1.8 V. The Figure 2 shows the functional diagram of the
integrated CEC block.
Figure 2. CEC link functional block diagram
VDD_CEC_IC
VDD_CEC
decoupling
capacitance
Enable
IEC61000-4-2
RPU_CEC_IC
Ctrl
circuit
HBM
CEC_IC
Anti back drive
diode
UVLO
decoupling
capacitance
CEC
driver
HDMI
connector
VDD_CEC
1
3
RPU_CEC_BUS
VDD_CEC_IC
CEC
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
In case of no activity on the CEC bus, or if the CEC driver is off (VDD_CEC = 0), the output
CEC pin is put in high impedance mode (open circuit) protecting the circuitry and the
application against hazardous backdrive.
The Figure 3 illustrates the normal operating mode of the CEC functional block when either
the IC from the source on the sink drives the communication.
Figure 3. CEC simplified
CEC_IC
CEC_IC
ASIC side
VDD_CEC_IC
VDD_CEC_IC
VIH_CEC_IC
VIL_CEC_IC
t
t
Cable side
CEC
CEC
VDD_CEC
VDD_CEC
90%
VTup_CEC
VTdown_CEC
t
10%
Block in high
impedance
tFALL_CEC
4/28
VHYST_CEC
Level shifting
Block in high
impedance
Source IC drives
DocID025842 Rev 3
t
Block in high
impedance
Level shifting
Sink drives through HDMI cable
Block in high
impedance
HDMI2C1-14HDS
Application information
In case the application is set in stand-by mode, the +5 V main supply of the application is
generally powered off in order to reduce as much as possible the global power
consumption. The CEC driver can be the only device still working in low power mode,
allowing a wake up of the whole application through the CEC line. When the main power
supply +5 V is switched off, and if the CEC bus is still active (VDD_CEC power in on state),
the HDMI2C1-14HDS keeps the CEC bus working properly while all other outputs of the
component are put in high impedance mode.
The CEC output (cable side) integrates a protection against ESD which is compliant with
IEC61000-4-2 standard, level 4 (8 kV contact).
DDC bus description
The DDC bus is described in the HDMI standards as the Display Data Channel. The
topology corresponds to an I2C bus that must be compliant with the I2C bus specification
version 2.1 (January 2000). The DDC bus is made of 2 lines: data line (SDA) and clock line
(SCL). It is used to create a point to point communication link from the Source to the Sink.
EEDID and HDCP protocols are especially flowing through this link, making this I2C
communication channel a key element in the HDMI application.
The DDC block integrated in the HDMI2C1-14HDS allows a bidirectional communication
between the cable and the ASIC. It is fully compliant with the HDMI standard and its CTS,
and with the I2C bus specification version 2.1. It is shifting the 5 V voltage from the cable
(V5V_OUT) down to the ASIC voltage level (VDD_IC) that can be as low as 1.8 V. The Figure 4
shows the functional diagram of the DDC block integrated in the HDMI2C1-14HDS device.
Figure 4. The DDC functional block diagram (SCL and SDA lines)
VDD_IC
+5V
decoupling
capacitance
VDD_IC
VDD_5V
5V_OUT
1
3
RPU_ASIC
UVLO
11
13
15
17
SCL_IC
SDA_IC
SCL
SDA
IEC61000-4-2
reshaping
circuit
Drive
6
8
9
RPU_BUS
Enable
5
7
dynamic pull -up
VDD_5V
2
4
5V_OUT
HDMI
ASIC
HBM
2.2
19
10
12
14
16
18
HDMI
connector
The Figure 5 illustrates the electrical parameters of the DDC block specified in Table 8.
DocID025842 Rev 3
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28
Application information
HDMI2C1-14HDS
Figure 5. Simplified view of the electrical parameters of the DDC functional block
SDA_IC
ASIC side
VDD_IC
Vtup_IC
V Tdown_IC
t
SDA
5V_OUT
Cable side
70%
Vtup_BUS
V Tdown_BUS
V HYST_BUS
30%
t
T FALL_BUS
T RISE_BUS
IC drives
Cable drives
The HDMI standard specifies that the max capacitance of the cable can reach up to 700 pF.
Knowing that the max capacitance of the sink input can reach up to 50 pF, this means that
the I2C driver must be able to drive a load capacitance up to 750 pF. On the other hand, the
I2C standard specifies a maximum rise time of the signal must be lower than 1 µs in order to
keep the signal integrity. Taking into account the max cable capacitance of 750 pF, it is not
possible to guarantee a rise time lower than 1 µs in worst case. Therefore, a dynamic pullup has been integrated at the output of SDA and SCL lines and synchronized with the I2C
driver. This signal booster accelerates for a short period the charging time of the equivalent
cable capacitance, allowing driving any HDMI cable. The Figure 6 illustrates the benefit of
the dynamic pull-up integrated in the HDMI2C1-14HDS device.
6/28
DocID025842 Rev 3
HDMI2C1-14HDS
Application information
Figure 6. Benefit of the dynamic pull-up on the DDC bus
I2C driver with dynamic pull-up
I2C driver without dynamic pull-up
5V_OUT
5V_OUT
dynamic pull -up
RPU_BUS
logical
circuitry
synchronized
with I2C bus
750pF
RPU_BUS
750pF
HDMI™ cable model
HDMI™ cable model
IC control
VDD_IC
IC control
VDD_IC
Signal on the cable
Signal on the cable
5V_OUT
5V_OUT
Rise time out of I2C specification
Risk of communication failure
Rise time compliante with I2C specification
Signal integrity even on 750 pF load capacitance
In order to activate the DDC lines, the VDD_5V has to reach the VDD_ON threshold (see
Table 4). The inputs and outputs of the bidirectional level shifters (SDA, SCL, SDA_IC,
SCL_IC) must be set to a high level after the power-on, and the HPD line has to be activated
on time.
The DDC outputs (SCL and SDA on cable side) integrate a protection against ESD which is
compliant with IEC61000-4-2 standard, level 4 (8kV contact).
DocID025842 Rev 3
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28
Application information
2.3
HDMI2C1-14HDS
HEAC link and HPD line description
The HDMI2C1-14HDS proposes a unique solution in order to manage and protect both the
HEAC and the HPD links. The Figure 7 shows an overview of the function diagram of the
integrated block.
Figure 7. HEAC / HPD / Utility functional block diagram
decoupling
capacitance
VDD_IC
HDMI
connector
VDD_IC
HPD
or
HPD / HEAC-
1
3
IEC61000-4-2
HPD_IC
HBM
HDMI
ASIC
7
11
13
15
Utility
IEC61000-4-2
6
8
9
IC
matching
2
4
5
17
Utility / HEAC+
19
10
12
14
16
18
This block simplifies the design and the PCB layout of the HPD and HEAC functions.
Both HPD and Utility inputs (cable side) integrate a protection against ESD which is
compliant with IEC61000-4-2 standard, level 4 (8 kV contact).
2.3.1
HPD line description
The HPD line is described in the HDMI standard as the hot plug detect function. This line is
used by the source device in order to detect if a sink device is connected through an HDMI
cable.
The integrated HPD block is pulling down the line via a current source. When the input
voltage is detected to be higher than a threshold level VTH_HPD, the signal is converted into
a high state level on the ASIC side, at the voltage level of the ASIC power supply VDD_IC.
Otherwise, CEC_IC pin remains in low state.
The electrical parameters relevant to the HPD block and specified by theTable 7 are
illustrated in the Figure 8.
8/28
DocID025842 Rev 3
HDMI2C1-14HDS
Application information
Figure 8. Simplified view of the electrical parameters of the HPD block
Signal on HPD link
5V
VIL_HPD
HPD_IC signal
VDD_IC
2.3.2
HEAC link
The HEAC link is described in the HDMI 1.4 standards as the HDMI ethernet and audio
return channel. It corresponds physically to one differential wired pair made of the Utility line
and the HPD line. Two signals are transmitted through this link.
The first signal corresponds to the HDMI ethernet channel (HEC). The signal is transmitted
in differential mode (bidirectional) through the HEAC link. It is specified by the 100Base-TX
IEEE 802.3 standard (fast ethernet 100Mbps over twisted pair). Therefore, the HEC
integrates an ethernet link into the video cable, enabling IP-based applications over the
HDMI cable.
The second signal corresponds to the audio return channel (ARC). The signal is transmitted
in common mode (unidirectional, from sink to source) through the HEAC link. It is specified
by the IEC 60958-1 standard. The ARC function integrates an upstream audio capability,
simplifying the cabling of the audiovisual equipment. It is no more necessary to use a
coaxial cable from TV to audio amplifier.
The HDMI2C1-14HDS helps the designer to implement this high added value HEAC
function in the application, protecting the link against the ESD with no disturbance of the
signal.
2.4
+5V protection and fault line
The +5 V power supply that the source device has to provide to the HDMI cable is described
by the HDMI standard. It must be protected against accidental short circuit that could occur
on the cable side.
The HDMI2C1-14HDS device embeds a low drop current limiter. If an overcurrent is
detected, the HDMI2C1-14HDS limits the current through the +5 V power supply. If the
current is too high (short circuit), the device opens the +5 V.
Furthermore, the HDMI2C1-14HDS device embeds also an over temperature protection
(OTP). If the internal temperature of the device is reaching a too high value, the +5 V supply
is even opened in order to protect the application.
DocID025842 Rev 3
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28
Application information
HDMI2C1-14HDS
In case either the current limiter or the OTP is triggered, the fault pin switches down to a low
state level (open drain topology) in order to inform the HDMI ASIC that an abnormal
situation has been detected (option).
An under voltage lockout (UVLO) is also integrated in the block. It checks the main +5 V
power supply state, and enable the +5V_OUT only if the main power supply has reach a
minimal value VDD_5V_ON.
The Figure 9 shows the functional diagram of the current limiter block.
Figure 9. +5V functional block diagram
HDMI
connector
5V
UVLO
3
decoupling
capacitance
OTP
IEC61000-4-2
VDD_IC
1
+5V_OUT
Low drop current limiter
Current
sensor
HBM
decoupling
capacitance
VDD_5V
7
Ctrl
RPU_FAULT
11
15
17
FAULT
6
8
9
13
HDMI
ASIC
2
4
5
19
10
12
14
16
18
IC
HBM
or
To summarize, the short circuit protection and the over temperature protection features are
providing a high robustness level of the application. On top of this, the fault line feature can
be used in order to improve the user experience.
The 5V_OUT pin integrates a protection against ESD which is compliant with IEC61000-4-2
standard, level 4 (8 kV contact). The decoupling capacitance is mandatory, according to the
power management state of the art.
10/28
DocID025842 Rev 3
HDMI2C1-14HDS
2.5
Application information
TMDS channels
The TMDS (Transient Minimized Differential Signaling) channels are described by the HDMI
standard. A total of 4 unidirectional differential pairs are used to transmit the video data to
the Sink device. There are 3 channels dedicated to the video data, and 1 channel dedicated
to the clock. The frequency of the TMDS clock is 1/10 of the video data frequency.
The HDMI2C1-14HDS provides a simple PCB layout solution, directly compliant with HDMI
connector type A. It protects the application against the ESD according the IEC61000-4-2
level 4 standard (+/-8 kV contact). The high bandwidth of this ESD protection allows to
transmit HD video data with no disturbance of the signal up to 3.4Gbps per channel.
Figure 10. TMDS lines ESD protection functional diagram
HDMI
connector
DAT_D2+
1
DAT_D2-
3
DAT_D1+
5
7
DAT_D1-
9
DAT_D0+
11
DAT_D0-
13
DAT_CLK+
15
17
4
6
8
10
12
14
16
18
19
IEC61000-4-2
DAT_CLK-
2
2.6
Application block diagrams
The Figure 11 shows an application block diagram proposal implementing all the possible
options. The diagram shows that the CEC driver can be totally independent from the HDMI
ASIC. By this way, even if the +5 V power supply and/or if the HDMI ASIC is sleeping in
stand-by mode, the CEC bus is still active in low power mode. By this way, the designer has
then the tools to optimize the power consumption of the global application in stand-by mode,
and in the same time, has the possibility to implement a smart wake-up through the CEC
bus enhancing the final user experience.
DocID025842 Rev 3
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28
Application information
HDMI2C1-14HDS
Figure 11. Application block diagram
VDD_IC
HDMI2C1-14HDS
4 TMDS channels
8 lines
+5V
VDD_5V
C3
R7
C4
+5V power
5V_OUT
VDD_IC
over current
detect
C2
FAULT
R3 R2
HPD_IC
HPD
HEAC-
VDD_IC
HPD
HPD / HEAC-
SDA
SDA
R4
R5
DDC data
SDA_IC
DDC clock
SCL_IC
SCL
HDMI connector
VDD_IC
HDMI ASIC
TMDS data2+
TMDS data2TMDS data1+
TMDS data1TMDS data0+
TMDS data0TMDS clock+
TMDS clock-
TMDS
lines
SCL
Utility
Utility / HEAC+
HEAC+
VDD_CEC_IC
VDD_CEC
VDD_CEC_IC
R6
CEC
driver
VDD_CEC
C5
D1
C1
CEC_IC
GND
CEC
R1
CEC bus
Table 1. Block diagrams references
Ref.
Typical values
R1
27 kΩ
Pull-up resistance on CEC bus, specified by the HDMI standard
R2, R3
1.8 kΩ
Pull-up resistances on DDC bus, specified by the HDMI standard
R4, R5
10 kΩ
Pull-up resistance on DDC bus, ASIC side, value selected to be
compliant with I2C levels
R6
Note:
12/28
Comment
270 kΩ to 1 MΩ Pull-up resistance on CEC line, ASIC side
R7
10 kΩ
Pull-up resistance on FAULT line (option)
D1
BAT54
Small schottky diode blocking backdrive current flowing toward the
VDD_CEC supply
C1 to C5
100 nF
Decoupling capacitance on power supplies
SCL_IC, SDA_IC, and CEC_IC have to be driven with an ASIC working with open drain
outputs.
DocID025842 Rev 3
HDMI2C1-14HDS
Application information
Table 2. Pin description
Pin
Name
Fault line output ASIC side
13
DAT_D0-
TMDS data D0-
CEC_IC
CEC output ASIC side
14
DAT_D0+
TMDS data D0+
3
SCL_IC
DDC output ASIC side
15
DAT_D1-
TMDS data D1-
4
SDA_IC
SDA output ASIC side
16
DAT_D1+
TMDS data D1+
5
HPD_IC
HPD output ASIC side
17
DAT_D2-
TMDS data D2-
6
Utility
Utility/HEAC+ input HDMI
cable side
18
DAT_D2+
TMDS data D2+
7
HPD
HPD/HEAC- input HDMI
cable side
19
CEC
CEC output HDMI cable side
8
SDA
DDC output HDMI cable side
20
VDD_CEC
CEC supply HDMI cable side
9
SCL
DDC output HDMI cable side
21
5V_OUT
+5 V power supply HDMI cable side
10
CK-
TMDS CK+
22
VDD_5V
+5 V main power supply
11
CK+
TMDS CK-
23
VDD_CEC_IC
12
NC
None connected
24
VDD_IC
CEC supply ASIC side
HDMI ASIC power supply
9''B9
9B287
9''B&(&
&(&
Figure 12. Pin numbering
)$8/7B,&
'$7B'
&(&B,&
'$7B'
6&/B,&
'$7B'
6'$B,&
'$7B'
+3'B,&
'$7B'
87,/,7<
'$7B'
&.
1&
&.
*1'
6&/
2
9''B&(&B,&
FAULT_IC
Description
6'$
1
Description
9''B,&
Name
+3'
Pin
DocID025842 Rev 3
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28
Electrical characteristics
3
HDMI2C1-14HDS
Electrical characteristics
Table 3. Absolute maximum ratings (limiting values)
Symbol
Parameter
ESD discharge on HDMI cable side (pin 6 to 11, pin 13
to 19 and pin 21), IEC 61000-4-2 level 4
Vpp_BUS
Test conditions
Value
Unit
Contact discharge
±8(1)
kV
±2
kV
ESD discharge (all pins), HBM JESD22-A114D level 2 Contact discharge
Vpp_IC
Tstg
Storage temperature range
-55 to +150
°C
Top
Operating temperature range
-40 to +85
°C
TL
Maximum lead temperature
260
°C
6
V
-0.3 to 6
V
VDD_5V
VDD_IC
Supply voltages
VDD_CEC
VDD_CEC_IC
Inputs
Logical input min/max voltage range
1. With a 100 nF capacitor connected to the 5V_OUT pin.
Table 4. Power supply characteristics (Tamb = 25 °C)
Symbol
Parameter
Test conditions
Min. Typ. Max.
3.63
V
1.62
3.63
V
Low-voltage ASIC supply voltage
1.62
3.63
V
5 V input supply voltage range
4.9
5.0
5.3
V
+5 V power on reset
3.5
3.8
4.1
V
VDD_CEC_ON CEC power on reset
2.6
2.8
2.95
V
VDD_CEC
VDD_CEC_IC
VDD_IC
VDD_5V
VDD_5V_ON
(1)
CEC supply voltage, bus side
2.97
CEC supply voltage, IC side
IQS_5V
IQS_IC
IQS_CEC
Quiescent currents on VDD_5V,
VDD_IC, VDD_CEC, VDD_CEC_IC
IQS_CEC_IC
Rth
Junction to ambient thermal
resistance
TSD
Thermal Shutdown threshold
PTOTAL_SB
Standby conditions
600
VDD_5V = 5V, VDD_IC = 1.8V,
VDD_CEC = 3.3V
VDD_CEC_IC = 1.8V
Idle-state on CEC and DDC links,
HPD and 5V_OUT links open
75
200
Copper heatsink as shown by
Figure 18
75
120
VDD_5V = VDD_IC = 0V
VDD_CEC = 3.3V
VDD_CEC_IC = 3.3V
- VDD_5V has to reach the VDD_ON threshold
- The inputs and outputs of the bidirectional level shifter must be set to a high level after the power-on
- The HPD line has to be activated one time
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µA
40
1. In order to activate the DDC functional block, the 3 following conditions have to be met:
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3.3
Unit
°C/W
150
°C
0.8
mW
HDMI2C1-14HDS
Electrical characteristics
Table 5. CEC electrical characteristics(1)
Symbol
VTup_CEC
Parameter
Test conditions
Min. Typ. Max.
Upward input voltage threshold on bus side
2.0
VTdown_CEC Downward input voltage threshold on bus side
0.8
VHYST_CEC Input hysteresis on bus side
RUP_CEC = 14.1 k Ω(2)
C CEC_CABLE = 7.9 nF(2)
Output rise-time (10% to 90%)
TFALL_CEC
Output fall-time (90% to 10%)
IOFF_CEC
Leakage current in powered-off state
VIL_CEC_IC
VDD_5V = 0 V
VDD_IC = 0 V,
VDD_CEC = 3.3 V
Input low level on IC side
RON_CEC
CIN_CEC
1.
V
250
µs
50
µs
1.8
µA
0.5
VIH_CEC_IC Input high level on IC side
V
VIH_CEC_IC = 1.8 V
1.5
VIH_CEC_IC = 3.3 V
1.9
On resistance across CEC and CEC_IC pins CEC pin to 0 V
VDD_5V = 0 V
VDD_CEC = 0 V
VDD_IC = 0 V
VBIAS = 0 V, f = 1 MHz,
VOSC = 30 mV
Input capacitance on CEC link
V
V
0.4
TRISE_CEC
Unit
25
V
100
Ω
30(3)
pF
Tamb = 25 °C, VDD_CEC = 3.3 V, VDD_CEC_IC = 1.8 V, unless otherwise specified
2. Test conditions are compliant with worst case CEC specification:
- pull up resistance 2 times 27 k
Ω +5% in parallel
- Max capacitance corresponding to 9 equipment chained on the CEC bus
3. Maximum capacitance allowed at connector output is 200 pF in HDMI specification
Table 6. HDMI 5V_out current limiter electrical characteristics(1)
Value
Symbol
Parameter
VDROP
Drop-out voltage
I5V_OUT
Output
current(3)
VL_FAULT
Low level on FAULT pin
Test conditions
Unit
Min.
Typ.
Max.
I5V_OUT = 55 mA
20
50
95(2)
mV
V5V_OUT = 0 V
55
115
mA
0.3
V
RPU_FAULT = 10 k Ω
1. Tamb = 25°C, VDD_5V = 5 V, unless otherwise specified
2. HDMI specification requires a maximum of 100 mV voltage-drop
3. Maximum allowed output current is 500 mA when a sink is powered off in HDMI specification
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28
Electrical characteristics
HDMI2C1-14HDS
Table 7. HPD, HEAC, and utility line electrical characteristics(1)
Value
Symbol
Parameter
Test conditions
Unit
Min.
IPULL_DOWN
VTH_HPD
Pull-down current in HPD block
HPD input threshold level
CIN_HPD
CIN_UTILITY
Input capacitance
fCUT_HEAC
Cut-off frequency of HEAC bus
Typ.
Max.
15
25
µA
1.7
V
25
pF
1.0
VDD_5V = 0 V, VBIAS = 0 V
f = 1 MHz, VOSC = 30 mV
21
500
MHz
1. Tamb = 25°C, VDD_5V = 5 V, unless otherwise specified.
Table 8. DDC bus (SDA and SCL lines) electrical characteristics(1)
Value
Symbol
Parameter
Test conditions
Unit
Min.
VTup_BUS
Upward input voltage threshold on bus side
3.5
VTdown_BUS Downward input voltage threshold on bus side
1.5
VHYST_BUS Input hysteresis on bus side
1.0
V
V
1.3
V
Output low level
Current sunk by SDA and SCL
pin is 3 mA
0.35
V
TRISE_BUS
Output rise-time (30% to 70%)
CBUS = 750 pF(2)
RUP = 2 K Ω //47 K Ω + 10%(3)
500
ns
TFALL_BUS
Output fall-time (30% to 70%)
50
ns
VOL_BUS
VTup_IC
Upward input voltage threshold on IC side
55
60
65
%VDD_IC
VTdown_IC
Downward input voltage thresholds IC side
35
40
45
%VDD_IC
20
%VDD_IC
32(4)
pF
VOL_IC
CIN_DDC
1.
Typ. Max.
Output low level on IC side
Current sunk by SDA_IC or
SCL_IC pins is 500 µA
Input capacitance on DDC link
VDD_5V = 0 V
VDD_IC = 0 V
VDD_CEC = 0 V
VBIAS = 0 V, f = 1 MHz
VOSC = 30 mV
27
Tamb = 25 °C, VDD_5V = 5 V, VDD_IC = 1.8 V, unless otherwise specified
2. Maximum load capacitance allowed on I2C entire link (cable + connector) is 750 pF in HDMI specification.
3. Two pull-up resistors in parallel (sink + source). Typical value is 47 k
specification.
Ω and maximum value is 47 k Ω + 10% in HDMI
4. Maximum capacitance allowed at connector output is 50 pF in HDMI specification
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HDMI2C1-14HDS
Electrical characteristics
Table 9. TMDS links electrical characteristics (1)
Symbol
Parameter
Test conditions
Min.
Typ.
8.7(2)
Single ended mode
fCUT_TMDS
Bandwidth at -3 dB
VBR
Breakdown voltage
IRM = 1 mA
IRM
Leakage current
VRM = 3.3 V
Capacitance I/O to ground
VI/O = 0 V, f = 1 MHz,
VOSC = 30 mV
0.6
CI/O_I/O
Capacitance I/O to I/O
VI/O = 0 V, f = 1 MHz,
VOSC = 30 mV
0.3
ZDIFF
Differential impedance
tr = 200 ps (10%-90%)
Z0DIFF = 100 Ω
CI/O_GND
1.
Max.
Differential mode
GHz
6
4.5
85
Unit
V
100
100
nA
1.0
pF
pF
115
Ω
Tamb = 25 °C, VDD_CEC = 3.3 V, VDD_CEC_IC = 1.8 V, unless otherwise specified
2. The bandwidth is enough large to operate up to 340 MHz for HDMI clock frequency (10.2Gbps total data rate)
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28
Electrical characteristics
HDMI2C1-14HDS
Figure 13. CEC typical waveforms (IC to cable communication)
C2 = 1.00 V/div
top = 3.29 V
fall = 2.34 µs
base = -12.0 mV
rise = 459.98 µs
C3 = 500 mV/div
200 µs/div
Figure 14. CEC typical waveforms (cable to IC communication)
C2 = 1.00 V/div
C3 = 500 mV/div
top = 1.80 V
fall = 966.6 ns
base = 31.0 mV
rise = 120.02 µs
200 µs/div
Figure 15. DDC typical waveforms (IC to cable communication)
C2 = 1.00 V/div
top = 4.99 V
rise = 454.8 ns
fall = 78.07 ns
base = 90.0 mV
C3 = 500 mV/div
2 µs/div
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HDMI2C1-14HDS
Electrical characteristics
Figure 16. DDC typical waveforms (cable to IC communication)
C2 = 1.00 V/div
C3 = 500 mV/div
top = 1.80 V
rise = 1.25 µs
fall = 1.97 ns
base = 17.8 mV
2 µs/div
Figure 17. HPD typical waveforms (timing)
C2 = 1.00 V/div
C3 = 500 mV/div
top = 1.80 V
rise = 37.83 ns
fall = 9.47 ns
base = -6.8 mV
1 µs/div
Figure 18. HEAC single ended mode typical bandwidth
0
dB
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
100k
F(Hz)
1M
10M
HEAC+
DocID025842 Rev 3
100M
1G
10G
HEAC -
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28
Electrical characteristics
HDMI2C1-14HDS
Figure 19. TMDS line S21 frequency response
0
dB
-1
-2
-3
-4
-5
F(Hz)
-6
100k
1M
10M
CLKD0-
D1D2-
100M
CLK+
D0+
1G
10G
D1+
D2+
Figure 20. TDR of TMDS lines
PCB+HDMI2C1-14HDS
DAT2 lane
Figure 21. Eye diagram of TMDS line: D0, D1, D2 and CLK lanes at 3.35Gbps
250mV/div
Board alone
49.8ps/div
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HDMI2C1-14HDS
Electrical characteristics
Figure 22. Eye diagram of TMDS line: D0, D1, D2 and CLK lanes at 3.35Gbps
250mV/div
Board + HDMI2C1-14HDS
49.8ps/div
Figure 23. TMDS line: remaining voltage when positive 8 kV ESD applies
50 V/div
VPP : ESD peak voltage
VCL :clamping voltage at 30 ns
3 VCL :clamping voltage at 60 ns
4 VCL :clamping voltage at 100 ns
1
2
160 V 1
33 V 2
18 V3
16 V 4
20 ns/div
Figure 24. TMDS line: remaining voltage when negative ESD applies
50 V/div
-2 V
-23 V 2
-173 V
1
-9 V
4
3
VPP: ESD peak voltage
VCL :clamping voltage @ 30 ns
VCL :clamping voltage @ 60 ns
3
VCL :clamping voltage @ 100 ns
4
1
2
20 ns/div
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28
Package information
4
HDMI2C1-14HDS
Package information
•
Epoxy meets UL94, V0
•
Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1
QFN package information
Figure 25. QFN package outline
e
b
E
E2
K
L
D2
D
A
A1
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HDMI2C1-14HDS
Package information
Table 10. QFN package mechanical data
Dimensions
Ref
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.80
0.90
1.00
0.031
0.035
0.039
A1
0.00
0.02
0.05
0.000
0.000
0.002
b
0.18
0.25
0.30
0.007
0.009
0.011
D
4.00 BSC
0.157
E
4.00 BSC
0.157
e
0.50 BSC
0.020
K
0.15
0.100
0.106
0.110
D2
2.55
2.70
2.80
0.100
0.106
0.110
E2
2.55
2.70
2.80
0.006
L
0.30
0.40
0.50
0.011
0.0157
0.0196
Figure 26. PCB footprint recommendation (dimensions in mm)
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28
Package information
4.2
HDMI2C1-14HDS
Packing information
Figure 27. Marking specification
CCC: Country of origin
Y: Assy year
W W: Assy week
e4
G
14HDS
Y WW
CCC
Figure 28. Tape and reel specification
2.0
Ø 1.5
1.75
4.0
0.30
4.35
16.0
8.5
1.5
0.25
4.35
8.0
1.10
All dimensions are typical values in mm
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User direction of unreeling
DocID025842 Rev 3
1.5
HDMI2C1-14HDS
Recommendation on PCB assembly
5
Recommendation on PCB assembly
5.1
Stencil opening design
1.
General recommendation on stencil opening design
a)
Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 29. Stencil opening dimensions
L
T
b)
W
General design rule
Stencil thickness (T) = 75 ~ 125 µm
W
Aspect Ratio = ----- ≥ 1.5
T
L×W
Aspect Area = ---------------------------- ≥ 0.66
2T ( L + W )
2.
Reference design
a)
Stencil opening thickness: 100 µm
b)
Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 30. Recommended stencil window position
250 µm
570 µm
600 µm
237 µm
4.4 mm
0.25 mm
0.60 mm
2.7 mm
2.7 mm
2.7 mm
4.4 mm
1.9 mm
0.5 mm
Stencil window
Footprint
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28
Recommendation on PCB assembly
5.2
5.3
5.4
5.5
HDMI2C1-14HDS
Solder paste
1.
Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste recommended.
3.
Offers a high tack force to resist component displacement during PCB movement.
4.
Use solder paste with fine particles: powder particle size 20-45 µm.
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Standard tolerance of ± 0.05 mm is recommended.
4.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB is recommended during solder paste
printing, pick and place and reflow soldering by using optimized tools.
PCB design preference
1.
To control the solder paste amount, closed vias are recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced.
Symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
Reflow profile
Figure 31. ST ECOPACK® recommended soldering reflow profile for PCB mounting
240-245 °C
Temperature (°C)
250
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
Note:
26/28
30
60
90
120
150
180
210
240
270
300
Minimize air convection currents in the reflow oven to avoid component movement.
DocID025842 Rev 3
HDMI2C1-14HDS
6
Ordering information
Ordering information
Figure 32. Ordering information scheme
HDMI2C
1
-
14
HDS
HDMI and I2C compliant links
HDMI port type
1: source ports
Number of protected links
14 lines protected according to IEC 6100-4-2
Version
HSD: HD1080p supported
Table 11. Ordering information
7
Order code
Marking
Package
Weight
Base qty
Delivery mode
HDMI2C1-14HDS
14HDS
QFN_24L
44 mg
4,000
Tape and Reel
Revision history
Table 12. Document revision history
Date
Revision
Changes
25-Jul-2014
1
Initial release
10-Dec-2014
2
Updated Figure 26.
04-Sep-2015
3
Updated Figure 1, Figure 12 and Table 2. Reformatted to current
standards.
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HDMI2C1-14HDS
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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