HDMI2C1-6C1

HDMI2C1-6C1 Datasheet ESD protection and signal booster for HDMI source control stage interface Features • • • • • QFN_18L 3.5 x 3.5 pitch 0.5 mm • HDMI2C1-6C1 VDD_5V 5V_OUT OT P UVLO FAULT VDD_IC SCL_IC UVLO I2C driver Booster SDA_IC HPD_IC SDA SCL HPD HEACHEAC+ VDD_CEC_IC matching UVLO Utility VDD_CEC • • • • • Driver CEC CEC_IC Product status link HDMI2C1-6C1 • For HDMI 1.4, 2.0 & 2.1 application, operating temperature from -40 to 85 °C 8 kV contact ESD protection on connector side (IEC 61000-4-2 level 4) Supports direct connection to low-voltage HDMI ASIC and/or CEC driver (down to 1.8 V) High integration level in 1 package DDC (I2C) link protection, bi-directional signal conditioning circuit and dynamic pull-up CEC bus protection, bi-directional level-shifter, backdrive protection, and independent structure from main power supply HEAC link protection and line matching HPD pull down, signal conditioning with level shifter and backdrive protection Short-circuit protection on 5V output Proposed in 500 µm pitch QFN 18L 3.5 x 3.5 Benefits: – Minimal PCB footprint in tablet, set top box, game console and other consumer application – Protection of ultra-sensitive HDMI ASICs – Wake-up from stand-by through CEC bus – Ultra low power consumption in stand-by mode – Improved HDMI interface ruggedness and user experience – Long and/or poor quality cable support with dynamic pull-up on DDC bus Complies with the following standards: – Dedicated for HDMI 1.4, 2.0 and 2.1 version – IEC 61000-4-2 level 4 – JESD22-A114D level 2 Applications Consumer and computer electronics HDMI Source device such as: • Tablet, smartphone and notebook • HD set-top boxes • Game console • DVD and Blu-Ray Disk systems • PC graphic cards Description The HDMI2C1-6C1 is an integrated ESD protection and signal conditioning device for control links of HDMI transmitters (Source). This device is a simple solution that provides HDMI designers with an easy and fast way to reach full compliance with the stringent HDMI CTS on a wide temperature range. HDMI logo and high-definition multimedia interface are trademarks or registered trademarks of HDMI licensing LLC. DS9943 - Rev 3 - May 2019 For further information contact your local STMicroelectronics sales office. www.st.com HDMI2C1-6C1 Functional description 1 Functional description The HDMI2C1-6C1 is a fully integrated ESD protection and signal conditioning device for control stage of HDMI transmitters (Source). The component offers two buffers, integrating signal conditioning dynamic pull-up on DDC bus for maximum system robustness and signal integrity. A bidirectional CEC block is integrated, able to wake-up the application from stand-by mode (all power supply off, except the CEC power supply). The +5 V supplied to the cable is protect against accidental surge current and short circuit. All these features are provided in a 18 leads QFN package featuring natural PCB routing, cost optimization and saving space on the board. The HDMI2C1-6C1 is a simple solution that provides HDMI designers with an easy and fast way to reach full compliance with the stringent HDMI CTS on a wide temperature range. STMicroelectronics proposes also a large range of high speed ESD protections and common mode filter (ECMF series) dedicated to the TMDS lanes giving the flexibility to the designer to filter and protect these (high speed video link against ESD strikes and EMC issues). 5V_OUT VDD_5V VDD_CEC_IC VDD_IC Figure 1. Pin configuration (bump side) pin out, top view FAULT VDD_CEC CEC_IC CEC GND SCL_IC SDA HPD HDP_IC UTILITY SCL HEAC+ SDA_IC HEACDS9943 - Rev 3 GND page 2/23 HDMI2C1-6C1 Application information 2 Application information 2.1 CEC line description The DDC bus is described in the HDMI standards as the display data channel. The topology corresponds to an I2C bus that must be compliant with the I2C bus specification UM10204 revision 5 (October 2012). The DDC bus is made of 2 lines: data line (SDA) and clock line (SCL). It is used to create a point to point communication link from the source to the sink. EEDID and HDCP protocols are especially flowing through this link, making this I2C communication channel a key element in the HDMI application. The DDC block integrated in the HDMI2C1-6C1 allows a bidirectional communication between the cable and the ASIC. It is fully compliant with the HDMI 2.0 standard (I2C bus specification) and its CTS. It is shifting the 5 V voltage from the cable (V5V_OUT) down to the ASIC voltage level (VDD_IC) that can be as low as 1.8 V. The Figure 2. DDC buffer functional diagram (SCL and SDA lines) shows the functional diagram of the DDC block integrated in the HDMI2C1-6C1 device. Figure 2. DDC buffer functional diagram (SCL and SDA lines) VDD_IC +5V decoupling capacitance VDD_5V VDD_IC UVLO IEC61000-4-2 HBM Drive 6 18 16 14 12 10 8 7 SCL SDA res haping circuit 19 17 15 13 11 9 RPU_BUS dynamic pull-up 5V_OUT Enable 5 5V_OUT HDMI ASIC SCL_IC SDA_IC 4 3 RPU_ASIC 2 1 5V_OUT HDMI connector The Figure 3. Simplified view of the electrical parameters of the DDC block illustrates the electrical parameter of the DDC block specified by the Table 7. DDC bus (SDA and SCL) line electrical characteristics (Tamb = 25 °C, VDD_5V = 5 V, VDD_IC = 1.8 V, unless otherwise specified) . DS9943 - Rev 3 page 3/23 HDMI2C1-6C1 DDC bus description ASIC side Figure 3. Simplified view of the electrical parameters of the DDC block SDA_IC V DD_IC V tup_IC V Tdown_ IC t SDA VDD_5V Cable side 5V_OUT 70% V tup_BU S V Tdown_ BUS V HYST_B US 30% t T FALL_B US T RISE_B US Source IC drives Sink drives through HDMI cable The HDMI standard specifies that the max capacitance of the cable can reach up to 700 pF. Knowing that the max capacitance of the Sink input can reach up to 50 pF, this means that the I2C buffer must be able to drive a load capacitance up to 750 pF. On the other hand, the I2C standard specifies a maximum rise time (30%-70%) of the signal must be lower than 1µs in order to keep the signal integrity. Taking into account the max cable capacitance of 750 pF, it is not possible to guarantee a rise time lower than 1µs in worst case. Therefore, a dynamic pull-up has been integrated at the output of SDA and SCL lines and synchronized with the I2C driver. This signal booster accelerates for a short period the charging time of the equivalent cable capacitance, allowing driving any HDMI cable. The Figure 4. Benefit of the dynamic pull-up on the DDC bus illustrates the benefit of the dynamic pull-up integrated in the HDMI2C1-6C1 device. DS9943 - Rev 3 page 4/23 HDMI2C1-6C1 DDC bus description Figure 4. Benefit of the dynamic pull-up on the DDC bus I2C driver without dynamic pull-up I2C driver with dynamic pull-up 5V_ OUT 5V_ OUT dynamic pull - up RPU_BUS 750pF RPU_BUS 750pF HDMI™ cable model IC control HDMI™ cable model IC control VDD_IC Signal on the cable Signal on the cable 5V_OUT Rise time out of I2C specification Risk of communication failure Rise time compliant with I2C specification Signal integrity even on 750pF load capacitance In order to activate the DDC bus, both following conditions must be respected: VDD_5V must be higher than the VDD_ON threshold (see Table 3. Power supply characteristics (Tamb = 25 °C)), and all inputs and outputs (SDA, SCL, SDA_IC, SCL_IC) must be set to a high level at the same time. The DDC outputs (SCL and SDA on cable side) integrate a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8 kV contact). 2.2 DDC bus description The DDC bus is described in the HDMI standards as the display data channel. The topology corresponds to an I2C bus that must be compliant with the I2C bus specification UM10204 revision 5 (October 2012). The DDC bus is made of 2 lines: data line (SDA) and clock line (SCL). It is used to create a point to point communication link from the source to the sink. EEDID and HDCP protocols are especially flowing through this link, making this I2C communication channel a key element in the HDMI application. The DDC block integrated in the HDMI2C1-6C1 allows a bidirectional communication between the cable and the ASIC. It is fully compliant with the HDMI 2.0 standard (I2C bus specification) and its CTS. It is shifting the 5 V voltage from the cable (V5V_OUT) down to the ASIC voltage level (VDD_IC) that can be as low as 1.8 V. The Figure 2. DDC buffer functional diagram (SCL and SDA lines) shows the functional diagram of the DDC block integrated in the HDMI2C1-6C1 device. DS9943 - Rev 3 page 5/23 HDMI2C1-6C1 DDC bus description Figure 2. DDC buffer functional diagram (SCL and SDA lines) VDD_IC +5V decoupling capacitance VDD_5V VDD_IC UVLO 4 3 RPU_ASIC 2 1 5V_OUT IEC61000-4-2 Drive 6 18 16 14 12 10 8 7 SCL SDA res haping circuit HBM 19 17 15 13 11 9 SCL_IC SDA_IC RPU_BUS 5V_OUT Enable dynamic pull-up HDMI ASIC 5 5V_OUT HDMI connector The Figure 3. Simplified view of the electrical parameters of the DDC block illustrates the electrical parameter of the DDC block specified by the Table 7. DDC bus (SDA and SCL) line electrical characteristics (Tamb = 25 °C, VDD_5V = 5 V, VDD_IC = 1.8 V, unless otherwise specified) . ASIC side Figure 3. Simplified view of the electrical parameters of the DDC block SDA_IC V DD_IC V tup_IC V Tdown_ IC t SDA VDD_5V Cable side 5V_OUT 70% V tup_BU S V Tdown_ BUS V HYST_B US 30% t T FALL_B US T RISE_B US Source IC drives Sink drives through HDMI cable The HDMI standard specifies that the max capacitance of the cable can reach up to 700 pF. Knowing that the max capacitance of the Sink input can reach up to 50 pF, this means that the I2C buffer must be able to drive a load capacitance up to 750 pF. On the other hand, the I2C standard specifies a maximum rise time (30%-70%) of the signal must be lower than 1µs in order to keep the signal integrity. Taking into account the max cable capacitance of 750 pF, it is not possible to guarantee a rise time lower than 1µs in worst case. Therefore, a dynamic pull-up has been integrated at the output of SDA and SCL lines and synchronized with the I2C driver. This signal booster accelerates for a short period the charging time of the equivalent cable capacitance, allowing driving any HDMI cable. The Figure 4. Benefit of the dynamic pull-up on the DDC bus illustrates the benefit of the dynamic pull-up integrated in the HDMI2C1-6C1 device. DS9943 - Rev 3 page 6/23 HDMI2C1-6C1 DDC bus description Figure 4. Benefit of the dynamic pull-up on the DDC bus I2C driver without dynamic pull-up I2C driver with dynamic pull-up 5V_ OUT 5V_ OUT dynamic pull - up RPU_BUS 750pF RPU_BUS 750pF HDMI™ cable model IC control HDMI™ cable model IC control VDD_IC Signal on the cable Signal on the cable 5V_OUT Rise time out of I2C specification Risk of communication failure Rise time compliant with I2C specification Signal integrity even on 750pF load capacitance In order to activate the DDC bus, both following conditions must be respected: VDD_5V must be higher than the VDD_ON threshold (see Table 3. Power supply characteristics (Tamb = 25 °C)), and all inputs and outputs (SDA, SCL, SDA_IC, SCL_IC) must be set to a high level at the same time. The DDC outputs (SCL and SDA on cable side) integrate a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8 kV contact). DS9943 - Rev 3 page 7/23 HDMI2C1-6C1 HEAC link and HPD line description 2.3 HEAC link and HPD line description The HDMI2C1-6C1 proposes a unique solution to manage and to protect both the HEAC and the HPD link. The shows an overview of the function diagram of the integrated block. Figure 5. HEAC / HPD Utility functional block diagram HDMI connector 4 6 5 Utility m atching IEC61000-4-2 HEAC+ Utility / HEAC+ 18 16 14 12 10 8 7 HEAC- 19 17 15 13 11 9 HBM IEC61000-4-2 HPD_IC or IC HPD / HEAC- 3 HPD HDMI ASIC 2 VDD_IC 1 decoupling capacitance VDD_IC This block simplifies the design and the PCB layout of the HPD + HEAC functions. Simply connect the 2 pins from the HDMI connector to one side of the device, and then use the 3 dedicated outputs on the other side of the device to manage separately the HPD and the HEAC links. Note that HEAC- and HEAC+ must be kept non connected when unused (to avoid to connect to GND when unused). Both HPD and Utility inputs (cable side) integrate a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8 kV contact) HPD line description The HPD line is described in the HDMI standards as the hot plug detect function. This line is used by the source device in order to detect if a sink device is connected through an HDMI cable. The integrated HPD block is pulling down the line via a current source. When the input voltage is detected to be higher than a threshold level, the signal is converted into a high state level on the ASIC side, at the voltage level of the ASIC power supply VDD_IC. Otherwise, CEC_IC pin remains in low state. The electrical parameters relevant to the HPD block and specified by the Table 6. HPD, HEAC, and utility line electrical characteristics(Tamb = 25 °C, VDD_5V = 5 V, unless otherwise specified) are shown by the Figure 6. Simplified view of the electrical parameters of the HPD block. DS9943 - Rev 3 page 8/23 HDMI2C1-6C1 +5 V protection and fault line Figure 6. Simplified view of the electrical parameters of the HPD block Signal on HPD link 5V VTH_HPD HPD_IC signal VDD_IC HEAC link The HEAC link is described in the HDMI 1.4 standards as the HDMI ethernet and audi return channel. It corresponds physically to one differential wired pair made of the Utility line and the HPD line. Two signals are transmitted through this link. The first signal corresponds to the HDMI ethernet channel (HEC). The signal is transmitted in differential mode (bidirectional) through the HEAC link. It is specified by the 100Base-TX IEEE 802.3 standard (Fast Ethernet 100 Mbps over twisted pair). Therefore, the HEC integrates an ethernet link into the video cable, enabling IP-based applications over the HDMI cable. The second signal corresponds to the audio return channel (ARC). The signal is transmitted in common mode (unidirectional, from sink to source) through the HEAC link. It is specified by the IEC 60958-1 standard. The ARC integrates an upstream audio capability, simplifying the cabling of the audiovisual equipment. It is no more necessary to use a coaxial cable from TV to audio amplifier. The HDMI2C1-6C1 helps the designer to implement this high added value HEAC function in the application, protecting the link against the ESD with no disturbance of the signal. It provides 2 distinct outputs HEAC+ and HEAC in order to ease as much as possible the PCB layout. Note that HEAC- and HEAC+ must be kept Non Connected when unused (to avoid to connect to GND when unused). 2.4 +5 V protection and fault line The +5 V power supply that the source device has to provide to the HDMI cable is described by the HDMI standard. It must be protected against accidental short circuit that could occur on the cable side. The HDMI2C1-6C1 device embeds a low drop current limiter. If an overcurrent is detected, the HDMI2C1-6C1 limits the current through the +5 V power supply. If the current is too high (short circuit), the device opens the +5V. Furthermore, the HDMI2C1-6C1 device embeds also an over temperature protection (OTP). If the internal temperature of the device is reaching a too high value, the +5 V supply is opened in order to protect the application. In case either the current limiter or the OTP is triggered, a logic signal is sent over the Fault line in order to inform the HDMI ASIC that an abnormal situation has been detected (option). An under voltage lockout (UVLO) is also integrated in the block. It checks the main +5 V power supply state, and enable the +5V_OUT only if the main power supply has reach a minimal value VDD_5V_ON. The Figure 7. 5 V link functional diagram shows the functional diagram of the current limiter block. DS9943 - Rev 3 page 9/23 HDMI2C1-6C1 +5 V protection and fault line Figure 7. 5 V link functional diagram HDMI connector FAULT 2 4 3 6 5 7 decoupling capacitance 18 16 14 12 10 8 Ctrl RPU_FAULT 19 17 15 13 11 9 HDMI ASIC OTP UVLO IEC61000-4-2 VDD_IC +5V_OUT Low drop current limiter Curr ent se nsor HBM decoupling capacitance VDD_5V 1 5V IC HBM or To summarize, the short circuit protection and the over temperature protection features are providing a high robustness level of the application. On top of this, the fault line feature can be used in order to improve the user experience. The 5V_OUT pin integrates also a protection against ESD which is compliant with IEC61000-4-2 standard, level 4 (8 kV contact). The decoupling capacitance is mandatory accordingly to the power management state of the art. DS9943 - Rev 3 page 10/23 HDMI2C1-6C1 Application block diagrams 2.5 Application block diagrams The Figure 8 shows an application block diagram proposal, with all possible options implemented. The diagram shows that the CEC driver can be totally independent from the HDMI ASIC. By this way, even if the +5V power supply and/or if the HDMI ASIC is sleeping in stand-by mode, the CEC bus is still active in low power mode. By this way, the designer has then the tools to optimize the power consumption of the global application in stand-by mode, and in the same time, has the possibility to implement a smart wake-up through the CEC bus enhancing the final user experience. Figure 8. Application block diagram VDD_IC +5V HDMI2C1-6C1 +5V pow er HDMI ASIC 5V_OUT VDD_5V R7 C3 C4 C2 VDD_IC over curr ent detect R3 R2 HDMI connector VDD_IC FAULT HPD HPD_IC VDD_IC HPD HPD / HEAC- R4 R5 DDC data SDA_IC SDA SDA DDC clo ck SCL_IC SCL SCL HEAC- HEAC- HEAC+ HEAC+ VDD_CEC VDD_CEC_IC VDD_CEC_IC R6 CEC driver Utility / HEAC+ Utility VDD_CEC C5 D1 C1 CEC_IC R1 CEC CEC bus GND Table 1. External component recommendations Note: DS9943 - Rev 3 Ref. Typical value R1 27 kΩ Pull-up resistance on CEC bus, specified by the HDMI standard R2, R3 1.8 kΩ Pull-up resistance on DDC bus, specified by the HDMI standard R4, R5 10 kΩ Pull-up resistance on DDC bus, ASIC side, value selected to be compliant with I2C levels R6 270 kΩ to 1 MΩ R7 10 kΩ Pull-up resistance on FAULT line (option) D1 BAT54 Small Schottky diode blocking backdrive current flowing toward the VDD_CEC supply C1 to C5 100 nF Decoupling capacitance on power supplies Comment Pull-up resistance on CEC line, ASIC side. SCL_IC, SDA_IC and CEC_IC have to be driven with an ASIC working with open drain outputs. page 11/23 HDMI2C1-6C1 Application block diagrams 18 FAULT 5V_OUT VDD_5V VDD_CEC_IC VDD_IC Figure 9. Pin numbering 15 1 14 CEC_IC CEC GND SCL_IC GND SDA_IC SCL 5 10 9 UTILITY HEAC+ HEAC- 6 DS9943 - Rev 3 SDA HPD HDP_IC VDD_CEC page 12/23 HDMI2C1-6C1 Electrical characteristics 3 Electrical characteristics Table 2. Absolute maximum ratings (limiting values) Symbol VPP_BUS VPP_IC Parameter Test conditions Value ESD discharge on HDMI cable side (pins 8 to 16) Contact discharge ±8(1) IEC 61000-4-2 level 4 Air discharge ±15 ESD discharge (all pins) Contact discharge ±2 HBM ‑JESD22-A114D, level 2 Air discharge ±2 Unit kV kV TSTG Storage temperature range -55 to +150 °C TOP Operating temperature range -40 to +85 °C 260 °C 6 V -0.3 to 6 V TL Maximum lead temperature VDD_5V, VDD_IC, VDD_CEC, VDD_CEC_IC Inputs Supply voltages Logical input min / max voltage range 1. With a 1 µF low ESR capacitor connected to the 5V_OUT pin Table 3. Power supply characteristics (Tamb = 25 °C) Symbol Parameter VDD_CEC VDD_CEC_IC VDD_IC VDD_5V VDD_5V_ON (1) VDD_5V_ON IQS_5V Test conditions Typ. Max. CEC supply voltage, bus side 2.97 3.3 3.63 V CEC supply voltage, IC side 1.62 3.63 V Low-voltage ASIC supply voltage 1.62 3.63 V 5 V input supply voltage range 4.9 5.0 5.3 kV +5 V power on reset 3.5 3.8 4.1 °C CEC power on reset 2.6 2.8 2.95 V VDD_5V = 5 V, VDD_IC = 1.8 V, VDD_CEC = 3.3 V, VDD_CEC_IC = 1.8 V, idlestate on CEC and DDC links, HPD and 5V_OUT links open Rth Junction to ambient thermal resistance Copper heatsink as shown by Figure 15 TSD Thermal Shutdown threshold IQS_CEC IQS_CEC_IC PTOTAL_SB Unit Min. Quiescent currents on VDD_5V, VDD_IC, VDD_CEC, VDD_CEC_IC IQS_IC Value Standby conditions 600 75 200 µA 40 70 120 VDD_5V = VDD_IC = 0 V, VDD_CEC = 3.3 V, VDD_CEC_IC = 3.3 V °C/W 150 °C 0.8 mW 1. In order to activate the DDC lines functional block the 3 following conditions have to be met: DS9943 - Rev 3 • VDD_5V has to reach the VDD_ON threshold • The inputs and outputs of the bidirectional level shifters must be set to a high level after the power-on • The HPD line has to be activated one time page 13/23 HDMI2C1-6C1 Electrical characteristics Table 4. CEC electrical characteristics (Tamb = 25 °C, VDD_CEC = 3.3 V, VDD_CEC_IC = 1.8 V, unless otherwise specified) Symbol Parameter Test conditions VTup_CEC Upward input voltage threshold on bus side VTdown_CEC Downward input voltage threshold on bus side Value Min. Output rise-time (10% to 90%) TFALL_CEC Output fall-time (90% to 10%) IOFF_CEC Leakage current in powered-off state 0.8 0.4 VDD_5V = 0 V, VDD_IC = 0 V, VDD_CEC = 3.3 Input low level on IC side VIH_CEC_IC Input high level on IC side Unit V V RUP_CEC = 14.1 kΩ(1), CCEC_CABLE = 7.9 nF (1) VIL_CEC_IC Max. 2.0 VHYST_CEC Input hysteresis on bus side TRISE_CEC Typ. V 250 µs 50 µs 1.8 µA 0.5 V VDD_CEC_IC = 1.8 V 1.5 V VDD_CEC_IC = 3.3 V 1.9 V 100 Ω 30(2) pF RON_CEC On resistance across CEC and CEC_IC pins CEC pin to 0 V CIN_CEC Input capacitance on CEC link VDD_5V = 0 V, VDD_CEC = 0 V,VDD_IC = 0 V, VBIAS = 0 V, f = 1 MHz, VOSC = 30 mV 25 1. Test conditions are compliant with worst case CEC specification: • Correspond to two 27 kΩ +5% pull-up resistances in parallel (compliant with HDMI CTS) • Max capacitance corresponding to 9 equipment chained on the CEC bus 2. Maximum capacitance allowed at connector output is 200 pF in HDMI 1.4 specification Table 5. HDMI 5V_OUT current limiter electrical characteristics (Tamb = 25 °C, VDD_5V = 5 V, unless otherwise specified) Symbol VDROP I5V_OUT Parameter Test conditions Drop-out voltage I5V_OUT = 55mA Output current VL_FAULT Low level on FAULT pin V5V_OUT = 0V Value Unit Min. Typ. Max. 20 50 95(1) mV 115(2) mA 0.3 V 55 RPU_FAULT = 10 kΩ 1. HDMI 1.4 specification requires a maximum of 100mV voltage-drop 2. Maximum allowed output current is 500 mA when a sink is powered off in HDMI 1.4 specification DS9943 - Rev 3 page 14/23 HDMI2C1-6C1 Electrical characteristics Table 6. HPD, HEAC, and utility line electrical characteristics(Tamb = 25 °C, VDD_5V = 5 V, unless otherwise specified) Symbol Parameter Test conditions Value Min. Max. 15 25 µA 1.7 V 25 pF IPULL_DOWN Pull-down current in HPD block VTH_HPD HPD input low-level CIN_HPD CIN_Utility Input capacitance VDD_5V = 0 V, VBIAS = 0 V, f = 1 MHz, VOSC = 30 mV 21 Cut-off frequency of HEAC bus Single ended mode 200 fCUT_HEAC Unit Typ. 1.0 Table 7. DDC bus (SDA and SCL) line electrical characteristics (Tamb = 25 °C, VDD_5V = 5 V, VDD_IC = 1.8 V, unless otherwise specified) Symbol Parameter Test conditions VTup_BUS Upward input voltage threshold on bus side Value Min. 1.5 VHYST_BUS Input hysteresis on bus side 1.0 TRISE_BUS Output rise-time (30%-70%) TFALL_BUS Output fall-time (70%-30%) Unit Max. 3.5 VTdown_BUS Downward input voltage threshold on bus side VOL_BUS Typ. V V 1.3 V Current sunk by SDA pin is 3 mA 0.35 V CBUS = 750 pF(1), RUP = 2 kΩ // 47 kΩ + 10%(2) 500 ns 50 ns VTup_IC Upward input voltage threshold on IC side 55 60 65 %VDD_IC VTdown_IC Downward input voltage threshold on IC side 35 40 45 %VDD_IC VOL_IC Output low-level on IC side Current sunk by SDA_IC pin, SCL_IC pins is 500 µA 20 %VDD_IC Input capacitance on DDC link VDD_5V = 0 V, VDD_IC = 0 V, VDD_CEC = 0 V, VBIAS = 0V , f = 1 MHz, VOSC = 30mV CIN_DDC 27 32(3) 1. Maximum load capacitance allowed on I2C entire link (cable plus connector) is 750pF in HDMI 1.4 specification. 2. Two pull-up resistors in parallel (sink 47 kΩ + source 2 kΩ). 3. Maximum capacitance allowed at connector output is 50pF in HDMI 1.4 specification DS9943 - Rev 3 page 15/23 HDMI2C1-6C1 Electrical characteristics Figure 10. CEC typical waveforms (IC to cable communication) Figure 11. CEC typical waveforms (IC to cable communication) DS9943 - Rev 3 page 16/23 HDMI2C1-6C1 Electrical characteristics Figure 12. DDC typical waveforms (IC to cable communication) Figure 13. DDC typical waveforms (Cable to IC communication) DS9943 - Rev 3 page 17/23 HDMI2C1-6C1 Electrical characteristics Figure 14. HPD typical waveform (Timing) Figure 15. HEAC single ended mode typical waveform DS9943 - Rev 3 page 18/23 HDMI2C1-6C1 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 QFN package information Figure 16. QFN package outline e b E E2 K L D2 D A A1 DS9943 - Rev 3 page 19/23 HDMI2C1-6C1 QFN package information Table 8. 0201 package mechanical data Dimensions Ref. Millimeters Min. Typ. Max. A 0.51 0.55 0.60 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 3.50 D2 1.99 2.14 E 2.24 3.50 E2 1.99 2.14 e 2.24 0.50 L 0.30 K 0.20 0.40 0.50 Figure 17. QFN footprint recommendation (dimensions in mm) 0.50 0.30 0.50 3.60 2.20 0.50 0.20 2.20 3.60 DS9943 - Rev 3 page 20/23 HDMI2C1-6C1 Ordering information 5 Ordering information Figure 18. Ordering information scheme HDMI2C 1 - 6 - C1 HDMI and I2C compliant link HDMI port type Source Number of protected links 6 lines protected according to IEC 61000-4-2 Package typpe C1 = QFN Table 9. Ordering information Note: DS9943 - Rev 3 Order code Marking Package Weight Base qty. Delivery mode HDMI2C1-6C1 tbd QFN tbd tbd tbd More information is available in AN2348 application note : • STMicroelectronics 400 micro-meter Flip Chip: package description and recommendation for use page 21/23 HDMI2C1-6C1 Revision history Table 10. Document revision history DS9943 - Rev 3 Date Revision Changes 25-Jul-2014 1 Initial release. 10-Aug-2018 2 Minor text changes to improve readability. 15-May-2019 3 Updated Figure 18. page 22/23 HDMI2C1-6C1 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS9943 - Rev 3 page 23/23