HSP031-1BM6
Datasheet
Very low clamping Ethernet 10 Gbps single line ESD protection
Features
•
•
•
•
High ESD protection level exceeding IEC 61000-4-2 level 4:
–
±30kV (contact discharge)
–
±30kV (air discharge)
High IEC 61000-4-5 surge capability: 10 A
Very low dynamic resistance: 0.25 Ohm
Low capacitance: 0.7 pF
Application
•
1G/2.5G/5G/10G Ethernet
Description
The HSP031-1BM6 is a single channel ESD array with a rail to rail architecture
designed to protect 2 differential lines from over voltages event caused by ESD,
surge (8/20 µs).
Packaged in a QFN-6L, the device is designed specifically for the protection of highspeed differential lines such as Ethernet 10 Gbps.
Product status link
HSP031-1BM6
Product summary
Order code
HSP031-1BM6
Package
QFN-6L
Packing
Tape and reel
DS13343 - Rev 1 - May 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
HSP031-1BM6
Characteristics
1
Characteristics
Table 1. Absolute maximum ratings Tamb = 25 °C
Symbol
Parameter
VPP
Peak pulse voltage
IPP
Peak pulse current
Tj
Tstg
TL
Value
IEC 61000-4-2 contact discharge
30
IEC 61000-4-2 air discharge
30
8/20 µs
Unit
kV
10
A
Operating junction temperature range
-55 to +150
°C
Storage temperature range
-55 to +150
°C
260
°C
Maximum lead temperature for soldering during 10 s
Figure 1. Electrical characteristics (definition)
DS13343 - Rev 1
page 2/13
HSP031-1BM6
Characteristics
Table 2. Electrical characteristics Tamb = 25 °C
Symbol
Parameter
VRM
Reverse working voltage
IRM
Leakage current
Test conditions
Value
Min. Typ. Max.
VRM = 3.3 V
3.3
V
50
nA
10.5
V
VTRIG
Maximum off-state voltage
9
IHOLD
Minimum on-state current
38
mA
VH
Minimum on-state voltage
1.3
V
1
Ipp = 10 A - 8/20 µs
VCL
Clamping voltage
IEC 61000-4-2, +/- 8 kV contact discharge at 30 ns
TLP measurement (pulse duration 100 ns), IPP = 16 A
Rd
CLINE
S21
fc
DS13343 - Rev 1
Unit
TLP, pulse duration = 100 ns
7
V
8
V
5.9
V
0.25
Ω
Line capacitance
V I/O = 0 V, f = 3 GHz, VOSC = 30 mV
0.7
Attenuation measurement
f < 600 MHz
0.1
dB
5
GHz
-3 db
0.9
pF
page 3/13
HSP031-1BM6
Characteristics (curves)
1.1
Characteristics (curves)
Typical curves unless otherwise specified.
Figure 2. Peak pulse current versus initial junction
temperature (maximum value)
15
I PP(A)
Figure 3. Peak pulse current versus clamping voltage
(maximum value)
VCL(V)
8
8/20µs
8/20µs
8/20 µs
Tj initial = 25 °C
7
10
6
5
5
4
Tj( °C)
I PP(A)
3
0
25
50
75
100
125
150
Figure 4. Leakage current versus junction temperature
10000
1
175
IR(nA)
3
4
5
6
7
8
10
IR(nA)
Tj = 25 °C
1.5
1000
9
Figure 5. Leakage current versus reverse voltage
2
V RM = 3.3V
2
1
0.5
100
0
10
-0.5
-1
1
-1.5
Tj( °C)
0.1
25
DS13343 - Rev 1
50
75
100
125
VR(V)
-2
150
-4
-3
-2
-1
0
1
2
3
4
page 4/13
HSP031-1BM6
Characteristics (curves)
Figure 6. ESD response to IEC 61000-4-2 (+8 kV contact
discharge)
Figure 7. ESD response to IEC 61000-4-2 (-8 kV contact
discharge)
Figure 8. Positive TLP measurement
Figure 9. Negative TLP measurement
35
VCL (V)
I(A)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0
30
-5
25
-10
20
-15
15
-20
10
-25
5
VCL(V)
-30
0
0
1
2
3
4
5
6
7
8
9
Figure 10. Line capacitance versus frequency
1
C (pF)
I(A)
10
Figure 11. Line capacitance versus junction temperature
0.8
Vosc = 30 mVRMS
Tj = 25 °C
0.9
-35
C (pF)
f = 3 GHz
Vosc = 30 mVRMS
0.7
0.8
0.6
0.7
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
1.0E+07
DS13343 - Rev 1
Tj(°C)
f(Hz)
1.0E+08
1.0E+09
0
-40
-20
0
20
40
60
80
100
120
140
160
page 5/13
HSP031-1BM6
Characteristics (curves)
Figure 12. Line capacitance at a frequency of 3 GHz
versus reverse voltage
1.0
Figure 13. S21
C (pF)
Vosc = 30 mVRMS
Tj = 25 °C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-4.0
Vr (V)
-3.0
DS13343 - Rev 1
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
page 6/13
HSP031-1BM6
Package information
2
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
2.1
QFN-6L package information
Figure 14. QFN-6L package outline
E
D
Sideview
A1
A
Top view
L
e
0.05
b1
b2
Bottom view
Table 3. QFN-6L mechanical data
Symbol
Dimesions (milimeters)
Min.
Typ.
Max.
A
0.45
0.50
0.55
A1
0.00
A3
0.127
b1
0.15
0.20
0.25
b2
0.35
0.40
0.45
D
1.55
1.60
1.65
E
0.95
1.00
1.05
e
L
DS13343 - Rev 1
0.05
0.50
0.28
0.38
0.48
page 7/13
HSP031-1BM6
QFN-6L package information
Figure 15. Tape outline
Pin 1 located according to EIA - 481
P0
Ø D0
E
F
W
P1
P2
Ø D1
K0
User direction of unreeling
Note:
Pocket dimensions are not on scale
Pocket shape may vary depending on package
Table 4. Tape dimensions values
Dimensions
Millimeters
Ref.
DS13343 - Rev 1
Min.
Typ.
Max.
D0
1.45
1.55
1.65
D1
0.50
0.60
0.70
F
3.45
3.50
3.55
E
1.65
1.75
1.85
K0
0.67
0.72
0.77
P0
3.9
4
4.1
P1
3.9
4
4.1
P2
1.95
2.00
2.05
W
7.9
8.0
8.2
page 8/13
HSP031-1BM6
Recommendation on PCB assembly
3
Recommendation on PCB assembly
3.1
Footprint
SMD footprint design is recommended.
Figure 16. Footprint in mm
0.200
0.240
1.400
0.580
0.400
0.200
1.300
3.2
Stencil opening design
1.
Reference design
a.
Stencil opening thickness: 75 μm / 3 mils
b.
Stencil aperture ratio: 90%
Figure 17. Recommended stencil window position in mm
0.310
0.190
0.270
1.370
0.550
0.380
0.215
1.285
3.3
Solder paste
1.
2.
3.
4.
DS13343 - Rev 1
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
“No clean” solder paste is recommended.
Offers a high tack force to resist component movement during high speed.
Solder paste with fine particles: powder particle size is 20-38 μm.
page 9/13
HSP031-1BM6
Placement
3.4
Placement
1.
2.
3.
4.
5.
6.
3.5
PCB design preference
1.
2.
3.6
Manual positioning is not recommended.
It is recommended to use the lead recognition capabilities of the placement system, not the outline centering
Standard tolerance of ±0.05 mm is recommended.
3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste
and cause solder joints to short. Too low placement force can lead to insufficient contact between package
and solder paste that could cause open solder joints or badly centered packages.
To improve the package placement accuracy, a bottom side optical control should be performed with a high
resolution tool.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder
paste printing, pick and place and reflow soldering by using optimized tools.
To control the solder paste amount, the closed via is recommended instead of open vias.
The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is
recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away.
Reflow profile
Figure 18. ST ECOPACK® recommended soldering reflow profile for PCB mounting
250
240-245 °C
Temperature (°C)
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
30
60
90
120
150
180
210
240
270
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
Note:
Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020.
DS13343 - Rev 1
300
page 10/13
HSP031-1BM6
Ordering information
4
Ordering information
Figure 19. Ordering information scheme
HSP 03
1 - 1B
M6
High speed protection
Breakdown voltage
03 = 3.3V
Version
Direction
1B = 1 bidirectional line
Package
M6 = QFN - 6L (1.0 mm x 1.6 mm)
Table 5. Ordering information
Order code
Marking
Package
Weight
Base qty.
Delivery mode
HSP031-1BM6
HE (1)
QFN-6L
2.27 mg
3000
Tape and reel
1. The marking can be rotated by 90° to differentiate assembly location
DS13343 - Rev 1
page 11/13
HSP031-1BM6
Revision history
Table 6. Document revision history
DS13343 - Rev 1
Date
Version
25-May-2020
1
Changes
Initial release.
page 12/13
HSP031-1BM6
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS13343 - Rev 1
page 13/13
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