HSP051-4N10

HSP051-4N10 4-line ESD protection for high speed lines Datasheet - production data Applications The HSP051-4N10 is designed to protect against electrostatic discharge on sub micron technology circuits driving:      µQFN 1.9x1 10L HDMI 1.4 and 2.0 Digital video Interface Display port USB 3.0 and 3.1 Serial ATA Description The HSP051-4N10 is a 4-channel ESD array with a rail to rail architecture designed specifically for the protection of high speed differential lines. Features         Flow-through routing to keep signal integrity Ultralarge bandwidth: 10 GHz Ultralow capacitance:  0.2 pF (I/O to I/O)  0.35 pF (I/O to GND) Very low dynamic resistance: 0.48 Ω 100 Ω differential impedance Low leakage current: 100 nA at 25 °C Extended operating junction temperature range: -40 °C to 150 °C RoHS compliant The ultralow variation of the capacitance ensures very low influence on signal-skew. The large bandwidth makes it compatible with HDMI 2.0 4K/2K (= 5.94 Gbps) and USB 3.1 (= 10 Gbps) The device is packaged in μQFN 1.9 mm x 1 mm with a 400 μm pitch. Figure 1: Functional schematic (top view) Benefits    High ESD protection level High integration Suitable for high density boards Complies with the following standards   MIL STD 883G-Method 3015-7: class 3B  8 kV IEC 61000-4-2, level 4  25 kV (air discharge)  8 kV (contact discharge) May 2017 DocID025979 Rev 2 This is information on a product in full production. 1/12 www.st.com Characteristics 1 HSP051-4N10 Characteristics Table 1: Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value IEC61000-4-2 contact discharge 8 IEC61000-4-2 air discharge 25 Unit Vpp Peak pulse voltage kV Tstg Storage junction temperature range -65 to +150 Tj Operating junction temperature range -40 to +150 TL Maximum lead temperature for soldering during 10 s °C 260 Table 2: Electrical characteristics (Tamb = 25 °C) Symbol Test condition Min. 4.5 Typ. Max. IR = 1 mA IRM VRM = 3.6 V VCL IPP = 1 A, 8/20 μs VCL IEC 61000-4-2, +8 kV contact (IPP = 16 A), measured at 30 ns Rd Dynamic resistance, pulse duration 100 ns I/O to GND 0.48 GND to I/O 0.96 CI/O - I/O VI/O = 0 V F = 200 MHz to 9 GHz 0.2 0.3 pF CI/O - GND VI/O = 0 V F = 200 MHz to 2.5 GHz 0.4 0.55 pF F = 2.5 GHz to 9 GHz 0.35 0.45 pF Zdiff 5.8 Unit VBR fC 2/12 Parameter 10 V 100 nA 10 V 13 -3 dB V Ω 10 Time domain reflectometry: tr = 200 ps (10 - 90%), Z0 = 100 Ω DocID025979 Rev 2 85 100 GHz 115 Ω HSP051-4N10 1.1 Characteristics Characteristics (curves) Figure 2: Leakage current versus junction temperature (typical values) Figure 3: S21 attenuation measurement S21 (db) 0 100 -0.5 IR (nA) -1 VR = VRM = 3.6V -1.5 -2 -2.5 10 -3 -3.5 -4 Tj (°C) 1 25 50 75 100 125 -4.5 150 -5 10M 100M 1G 10G 100G F/Hz Figure 4: Eye diagram - HDMI mask at 3.4 Gbps per channel (without HSP051-4N10) Figure 5: Eye diagram - HDMI mask at 3.4 Gbps per channel (with HSP051-4N10) Figure 6: Eye diagram - HDMI 2.0 mask at 5.94 Gbps per channel (without HSP051-4N10, with worst case reference cable and EQ) Figure 7: Eye diagram - HDMI 2.0 mask at 5.94 Gbps per channel (with HSP051-4N10, with worst case reference cable and EQ) DocID025979 Rev 2 3/12 Characteristics HSP051-4N10 Figure 8: Eye diagram - USB 3.0 gen. 1 (5.0 Gbps) without HSP051-4N10 (with reference cable and equalizer) Figure 9: Eye diagram - USB 3.0 gen. 1 (5.0 Gbps) with HSP051-4N10 (with reference cable and equalizer) Figure 10: Eye diagram - USB 3.1 gen.2 (10.0 Gbps) without HSP051-4N10 (with reference cable, equalizer A = 6 dB and DFE) Figure 11: Eye diagram - USB 3.1 gen.2 (10.0 Gbps) with HSP051-4N10 (with reference cable, equalizer A = 6 dB and DFE) Figure 13: ESD response to IEC 61000-4-2 (-8 kV contact discharge) Figure 12: ESD response to IEC 61000-4-2 (+8 kV contact discharge) 50 V / Div 50 V / Div 1 2 3 4 V CL: Peak clamping voltage V CL :clamping voltage at 30 ns VCL :clamping voltage at 60 ns V CL :clamping voltage at 100 ns 1 184 V 2 13 V 3 11 V VCL: Peak clamping voltage VCL :clamping voltage @ 30 ns VCL :clamping voltage @ 60 ns VCL :clamping voltage @ 100 ns 4 10 V 20 ns / Div 4/12 DocID025979 Rev 2 20 ns / Div HSP051-4N10 Characteristics Figure 14: TLP measurement (pulse duration 100 ns, rise time 10 ns, average window 70 ns 90ns) DocID025979 Rev 2 Figure 15: TDR measurement 5/12 Package information 2 HSP051-4N10 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 2.1 µQFN1.9x1 10L package information Figure 16: µQFN1.9x1 10L package outline E A Side view Bottom view A1 Top view E2 D b e k D2 L2 6/12 DocID025979 Rev 2 HSP051-4N10 Package information Table 3: µQFN1.9x1 10L package mechanical data Dimensions Ref. Millimeters Min. Typ. Max. A 0.28 0.32 0.35 A1 0.00 0.02 0.05 b 0.15 0.20 0.25 D 1.85 1.90 1.95 D2 0.15 0.20 0.25 E 0.95 1.00 1.05 E2 0.88 0.93 0.98 e 0.40 k 0.21 L2 0.05 0.02 Figure 17: Footprint recommendations (dimensions in mm) 0,2 0,4 0,4 0.07 0,93 0,21 0,56 Figure 18: Marking HC 0,2 the marking codes can be rotated by 180° to differentiate assembly location. In no case should this product marking be used to orient the component for placement on a PCB. Only pin 1 mark is to be used for this purpose. DocID025979 Rev 2 7/12 Package information HSP051-4N10 Figure 19: µQFN1.9x1 10L tape and reel specification 8/12 DocID025979 Rev 2 HSP051-4N10 3 Recommendation on PCB assembly Recommendation on PCB assembly Figure 20: Recommended stencil window position 0,14 0,24 0,66 0,53 0,19 0,4 3.1 Solder paste 1. 2. 3. 4. 3.2 Halide-free flux qualification ROL0 according to ANSI/J-STD-004. “No clean” solder paste is recommended. Offers a high tack force to resist component movement during high speed. Solder paste with fine particles: powder particle size is 20-45 μm. Placement 1. 2. 3. 4. 5. 6. 3.3 0,4 Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of ±0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. DocID025979 Rev 2 9/12 Recommendation on PCB assembly HSP051-4N10 Figure 21: Printed circuit board layout recommendations 1 10 400µm Via to GND Via to GND 5 Footprint pad 3.4 6 PCB tracks Reflow profile Figure 22: ST ECOPACK® recommended soldering reflow profile for PCB mounting Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC JSTD-020. 10/12 DocID025979 Rev 2 HSP051-4N10 4 Ordering information Ordering information Figure 23: Ordering information scheme HSP 05 1 - 4 N10 High speed line protection Breakdown voltage Version Number of lines Package µQFN-10L 1.9x1.0mm Table 4: Ordering information 5 Order code Marking Package Weight Base qty. Delivery mode HSP051-4N10 HC µQFN-10L 1.61 mg 7000 Tape and reel Revision history Table 5: Document revision history Date Revision Changes 11-Jul-2014 1 Initial release. 19-May-2017 2 Updated Figure 16: "µQFN1.9x1 10L package outline" and Figure 19: "µQFN1.9x1 10L tape and reel specification" . DocID025979 Rev 2 11/12 HSP051-4N10 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 12/12 DocID025979 Rev 2