HVLED815PFTR

HVLED815PF Datasheet Offline LED driver with primary sensing and high power factor up to 15 W Features • • • • • • • • • High power factor capability (>0.9) 800 V, avalanche rugged internal 6Ω Power MOSFET Internal high voltage startup Primary sensing regulation (PSR) ±3% accuracy on constant LED output current Quasi-resonant (QR) operation Optocoupler not needed Open or short LED string management Automatic self-supply Applications • • Product status link HVLED815PF Description Table 1. Device summary Order code Package HVLED815PF HVLED815PFTR Packaging Tube SO16N AC-DC LED driver bulb replacement lamps up to 15 W, with high power factor AC-DC LED drivers up to 15 W Tape and reel The HVLED815PF device is a high voltage primary switcher intended for operating directly from the rectified mains with minimum external parts and enabling high power factor (>0.90) to provide an efficient, compact, and cost-effective solution for LED driving. It combines a high-performance low voltage PWM controller chip and an 800 V, avalanche rugged Power MOSFET in the same package. There is no need for an optocoupler thanks to the patented primary sensing regulation (PSR) technique. The device ensures protection against LED string fault (open or short). Product label DS9147 - Rev 6 - September 2022 For further information contact your local STMicroelectronics sales office. www.st.com Principle application circuit Figure 1. Application circuit for high power factor LED driver–single range input Lin Bridge Diode 2 1 Lf CON1 Rsnubber Rf 1A_DIP Csnubber F1 + J2 9 3 4 8 Cf Vout O u tp o u t D i o d e 7 6 TRANSFORMER 4 J1 CON1 C12 Cout Bulk C13 Cout SMD R12 Minimum Load J3 CON1 Lf CON1 Rf VIN D5 U1 HVLED8xxPF Rsense RA 1 Rsense R1 (500 - 1.5k)CS 2 RB VCC 3 C_Vcc (10uF MIN) 4 CS CS 220pF-1nF COS Filter (1uF) ROS SOURCE C_ILED (10uF) 5 Rf b DMG 6 Rf (8k-15k) Cf (330nF-680nF) 7 NA 8 Cp (1n-10nF) DRAIN DRAIN VCC DRAIN GND DRAIN ILED DMG COMP N.A. 16 S nubber D iode J4 10 2 5 - Cf T1 1 Cin EMI FILTER 3 VIN Cin DS9147 - Rev 6 1 C10 Y 1 - SAFETY 15 14 13 CS DMG VCC RPF D4 Rdmg D2 1N 4148 C_VCC (470nF) R-VCC (10-100ohm) HVLED815PF Principle application circuit page 2/32 1 Rf 1A_DIP Bridge Diode 2 1 Lf CON1 Rsnubber F2 Csnubber J7 Cin EMI FILTER 3 VIN + DS9147 - Rev 6 Figure 2. Application circuit for standard LED driver 9 3 4 8 Vout O u tp o u t D i o d e 1 6 TRANSFORMER C16 Cout Bulk J5 CON1 C27 Cout SMD R18 Minimum Load J6 CON1 Lf Rf U2 HVLED8xxPF Rsense 1 Rsense 2 VCC 3 C_Vcc (10uF) 4 C_ILED (10uF) 5 Rf b DMG 6 Rf (8.2k-15k) Cf (330nF/680nF) 7 NA 8 Cp (1nF/10nF) SOURCE CS DRAIN DRAIN VCC DRAIN GND DRAIN 16 S nubber D iode CON1 2 5 Cf 4 J8 10 7 - Cf T2 C23 Y 1 - SAFETY 15 14 13 ILED DMG COMP N.A. DMG VCC Rdmg D8 1N 4148 C_VCC (470nF) R-VCC (10ohm) HVLED815PF Principle application circuit page 3/32 DS9147 - Rev 6 2 Block diagram Figure 3. HVLED815PF block diagram + VIN VCC HV start-up & Supply Logic DRAIN LED Vref PROTECTION & FEEDFORWARD LOGIC DEMAG LOGIC RDMG RFB DMG DRIVING LOGIC CONSTANT CURRENT REGULATION 3.3 V VCS VILED Vref OCP 1V Constant Voltage Regulation COMP RCOMP RA ILED CS GND R1 SOURCE CLED RSENSE CCOMP RPF ROS HVLED815PF Block diagram page 4/32 HVLED815PF Pin description and connection diagrams 3 Pin description and connection diagrams Figure 4. Pin connection (top view) 3.1 SOURCE 11 16 16 DRAIN CS 22 15 15 DRAIN VCC 33 14 14 DRAIN GND 44 13 13 DRAIN ILED 55 12 12 N.C. DMG 66 11 11 N.A. COMP 77 10 10 N.A. N.A. 88 9 N.A. Pin description Table 2. Pin description No. 1 Name Function SOURCE Source connection of the internal power section. Current sense input. 2 CS Connect this pin to the SOURCE pin (through an R1 resistor) to sense the current flowing in the MOSFET through an RSENSE resistor connected to GND. The CS pin is also connected through dedicated ROS, RPF resistors to the input and auxiliary voltage, in order to modulate the input current flowing in the MOSFET according to the input voltage and therefore achieving a high power factor. See Section 5.11 for more details. The resulting voltage is compared with the voltage on the ILED pin to determine MOSFET turn- off. The pin is equipped with 250 ns blanking time after the gate drive output goes high for improved noise immunity. If a second comparison level located at 1 V is exceeded, the IC is stopped and restarted after VCC has dropped below 5 V. Supply voltage of the device. 3 VCC 4 GND A capacitor, connected between this pin and ground, is initially charged by the internal high voltage startup generator; when the device is running, the same generator keeps it charged in case the voltage supplied by the auxiliary winding is not sufficient. This feature is disabled in case a protection is tripped. A small bypass capacitor (100 nF typ.) to GND may be useful to get a clean bias voltage for the signal part of the IC. Ground. Current return for both the signal part of the IC and the gate drive. All of the ground connections of the bias components should be tied to a trace going to this pin and kept separate from any pulsed current return. Constant current (CC) regulation loop reference voltage. DS9147 - Rev 6 5 ILED 6 DMG An external capacitor CLED is connected between this pin and GND. An internal circuit develops a voltage on this capacitor that is used as the reference for the MOSFET’s peak drain current during CC regulation. The voltage is automatically adjusted to keep the average output current constant. Transformer demagnetization sensing for quasi-resonant operation and output voltage monitor. A negativegoing edge triggers the MOSFET turn-on, to achieve quasi-resonant operation (zero voltage switching). page 5/32 HVLED815PF Thermal data No. Name Function The pin voltage is also sampled-and-held right at the end of transformer demagnetization to get an accurate image of the output voltage to be fed to the inverting input of the internal, transconductance-type, error amplifier, whose non-inverting input is referenced to 2.5 V. The maximum IDMG sunk/sourced current must not exceed ±2 mA (AMR) in all the VIN range conditions. No capacitor is allowed between the pin and the auxiliary transformer. 3.2 Output of the internal transconductance error amplifier. The compensation network is placed between this pin and GND to achieve stability and good dynamic performance of the voltage control loop. 7 COMP 8 N.A Not available. These pins must be connected to GND. 9–11 N.A Not available. These pins must be left not connected. 12 N.C Not internally connected. Provision for clearance on the PCB to meet safety requirements. 13– 16 DRAIN Drain connection of the internal power section. The internal high voltage startup generator sinks current from this pin as well. Pins connected to the internal metal frame to facilitate heat dissipation. Thermal data Table 3. Thermal data Symbol DS9147 - Rev 6 Parameter Max. value Unit RthJP Thermal resistance, junction to pin 10 °C/W RthJA Thermal resistance, junction to ambient 110 °C/W PTOT Maximum power dissipation at TA = 50°C 0.9 W TSTG Storage temperature range -55 to 150 °C TJ Junction temperature range -40 to 150 °C page 6/32 HVLED815PF Electrical specifications 4 Electrical specifications 4.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Pin VDS 1, 13–16 Parameter Drain-to-source (ground) voltage Value Unit -1 to 800 V 1 A 50 mJ ID 1, 13–16 Drain Eav 1, 13–16 Single pulse avalanche energy (TJ = 25°C, ID = 0.7 A) VCC 3 Supply voltage (ICC < 25 mA) Self-limiting V IDMG 6 Zero current detector current ±2 mA VCS 2 Current sense analog input -0.3 to 3.6 V VCOMP 7 Analog input -0.3 to 3.6 V current(1) 1. Limited by maximum temperature allowed. 4.2 Electrical characteristics Table 5. Electrical characteristics VCC = 14 V (unless otherwise specified). Limits are production tested at TJ = TA = 25°C, and are guaranteed by statistical characterization in the range TJ -25 to +125°C. Symbol Parameter Test condition Min. Typ. Max. Unit 800 - - V µA Power section V(BR)DSS Drain-source breakdown ID < 100 µA; TJ = 25°C IDSS OFF-state drain current VDS = 750 V; TJ = 125°C(1) See Figure 5 - - 80 ID = 250 mA; TJ = 25°C - 6 7.4 ID = 250 mA; TJ = 125°C(1) - - 14.8 RDS(on) COSS Drain-source ON-state resistance Effective (energy related) output capacitance (1) Ω - See Figure 6 High voltage startup generator VSTART ICHARGE Min. drain start voltage ICHARGE < 100 µA 40 50 60 VCC startup charge current VDRAIN > VStart; VCC < VCCOn TJ = 25°C 4 5.5 7 VDRAIN > VStart; VCC0.90) and an efficient, compact, and costeffective solution for LED driving. It combines a high- performance low voltage PWM controller chip and an 800 V, avalanche rugged Power MOSFET, in the same package. The PWM is a current mode controller IC specifically designed for ZVS (“Zero Voltage Switching”) flyback LED drivers, with constant output current (CC) regulation using primary sensing feedback (PSR). This eliminates the need for the optocoupler, the secondary voltage reference, as well as the current sense on the secondary side, while still maintaining a good LED current accuracy. Moreover, it guarantees a safe operation when short-circuit of one or more LEDs occurs. The device can also provide a constant output voltage regulation (CV): it allows the application to be able to work safely when the LED string opens due to a failure. In addition, the device offers the shorted secondary rectifier (i.e., LED string shorted due to a failure) or transformer saturation detection. Quasi-resonant operation is achieved by means of a transformer demagnetization sensing input that triggers MOSFET turn-on. This input serves also as both output voltage monitor, to perform CV regulation, and input voltage monitor, to achieve mains-independent CC regulation (line voltage feedforward). The maximum switching frequency is top limited below 166 kHz, so that at medium-light load a special function automatically lowers the operating frequency while still maintaining the operation as close to ZVS as possible. At very light load, the device enters a controlled burst mode operation that, along with the built-in high voltage startup circuit and the low operating current of the device, helps minimize the residual input consumption. Although an auxiliary winding is required in the transformer to correctly perform CV/CC regulation, the chip is able to power itself directly from the rectified mains. This is useful especially during CC regulation, where the flyback voltage generated by the winding drops. 5.1 Application information The device is an off-line LED driver with all-primary sensing, based on quasi-resonant flyback topology, with high power factor capability. In particular, using different application schematic the device is able to provide a compact, efficient and cost-effective LED driver solution with high power factor (PF >0.9 - see application schematic in Figure 1) or with standard power factor (PF > 0.5/0.6 - see application schematic in Figure 2), based on the specific application requirements. Referring to the application schematic in Figure 1, the IC modulates the input current according to the input voltage providing the high power factor capability (PF > 0.9) keeping a good line regulation. This application schematic is intended for a single range input voltage. For wide range application a different reference schematic can be used; refer to AN4346 application note for further details. Moreover, the device is able to work in different modes depending on the LED's driver load condition (see Figure 11): 1. QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET's turn-on to the transformer's demagnetization by detecting the resulting negative-going edge of the voltage across any winding of the transformer. Then the system works close to the boundary between discontinuous (DCM) and continuous conduction (CCM) of the transformer. As a result, the switching frequency is different for different line/load conditions (see the hyperbolic-like portion of the curves in Figure 11). Minimum turn-on losses, low EMI emission and safe behavior in short-circuit are the main benefits of this kind of operation. 2. Valley-skipping mode at medium/ light load. Depending on voltage on COMP pin, the device defines the maximum operating frequency of the converter. As the load is reduced, MOSFET's turn-on does not occur any more on the first valley but on the second one, the third one and so on. In this way the switching frequency is no longer increased (piecewise linear portion in Figure 11). 3. Burst mode with no or very light load. When the load is extremely light or disconnected, the converter enters a controlled on/off operation with constant peak current. Decreasing the load result in frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulations or recommendations. Being the peak current very low, no issue of audible noise arises. DS9147 - Rev 6 page 12/32 HVLED815PF Power section and gate driver Figure 11. Multimode operation of HVLED815PF (constant voltage operation) f osc Input voltage f sw Valley-skipping mode Burst-mode Quasi-resonant mode 0 5.2 Pin Pinmax Power section and gate driver The power section guarantees safe avalanche operation within the specified energy rating as well as high dv/dt capability. The Power MOSFET has a VDSS of 800 V min. and a typical RDS(on) of 6 Ω. The internal gate driver of the Power MOSFET is designed to supply a controlled gate current during both turn-on and turn-off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the Power MOSFET cannot be turned on accidentally. 5.3 High voltage startup generator Figure 12 shows the internal schematic of the high voltage start-up generator (HV generator). It includes an 800 V-rated N-channel MOSFET, whose gate is biased through the series of a 12 MΩ resistor and a 14 V Zener diode, with a controlled, temperature compensated current generator connected to its source. The HV generator input is in common with the DRAIN pins, while its output is the supply pin of the device (VCC pin). A mains “UVLO” circuit (separated from the UVLO of the device that sense VCC) keeps the HV generator off if the drain voltage is below VSTART (50 V typical value). DS9147 - Rev 6 page 13/32 HVLED815PF High voltage startup generator Figure 12. High voltage start-up generator–internal schematic DRAIN 14V Vcc_OK 12M Mains UVLO HV_EN IHV VCC CONTROL Icharge GND With reference to the timing diagram of Figure 13, when power is applied to the circuit and the voltage on the input bulk capacitor is high enough, the HV generator is sufficiently biased to start operating, thus it will draw about 5.5 mA (typical) to the VCC capacitor. Most of this current will charge the bypass capacitor connected between the VCC pin and ground and make its voltage rise linearly. As soon as the VCC pin voltage reaches the VCC_ON turn on threshold (13 V typ.) the chip starts operating, the internal Power MOSFET is enabled to switch and the HV generator is cut off by the Vcc_OK signal asserted high. The IC is powered by the energy stored in the VCC capacitor. The chip is able to power itself directly from the rectified mains: when the voltage on the VCC pin falls below VCC_RESTART (10.5 V typ.), during each MOSFET's off-time the HV current generator is turned on and charges the supply capacitor until it reaches the VCC_ON threshold. In this way, the self-supply circuit develops a voltage high enough to sustain the operation of the device. This feature is useful especially during constant current (CC) regulation, when the flyback voltage generated by the auxiliary winding alone may not be able to keep VCC pin above VCC_RESTART. DS9147 - Rev 6 page 14/32 HVLED815PF Secondary side demagnetization detection and triggering block Figure 13. Timing diagram–normal power-up and power-down sequences VIN VStart t VCC VccON Vccrestart t DRAIN t ICHARGE 5.5 mA Normal operation CV mode Power-on 5.4 Power-off Normal operation CC mode t Secondary side demagnetization detection and triggering block The demagnetization detection (DMG) and triggering blocks switch on the Power MOSFET if a negative-going edge falling below 50 mV is applied to the DMG pin. To do so, the triggering block must be previously armed by a positive-going edge exceeding 100 mV. This feature is used to detect transformer demagnetization for QR operation, where the signal for the DMG input is obtained from the transformer's auxiliary winding used also to supply the IC. Figure 14. DMG block, triggering block Rdmg DMG DMG CLAMP BLANKING TIME STARTER Rf b Aux TURN-ON LOGIC + 110mV 60mV S Q From CC/CV Block LEB To Driv er R From OCP The triggering block is blanked after MOSFET's turn-off to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the DMG circuit erroneously. This TBLANK blanking time is dependent on the voltage on COMP pin: it is TBLANK = 30 µs for VCOMP = 0.9 V, and decreases almost linearly down to TBLANK = 6 µs for VCOMP = 1.3 V. DS9147 - Rev 6 page 15/32 HVLED815PF Constant current operation The voltage on the pin is both top and bottom limited by a double clamp, as illustrated in the internal diagram of the DMG block of Figure 14. The upper clamp is typically located at 3.3 V, while the lower clamp is located at -60 mV. The interface between the pin and the auxiliary winding will be a resistor divider. Its resistance ratio as well as the individual resistance values will be properly chosen (see Section 5.6 , Section 5.7 , and Section 5.11 ). Please note that the maximum IDMG sunk/sourced current has to not exceed ±2 mA (AMR) in all the VIN range conditions. No capacitor is allowed between DMG pin and the auxiliary transformer. The switching frequency is top limited below 166 kHz, as the converter's operating frequency tends to increase excessively at light load and high input voltage. A starter block is also used to start up the system, that is, to turn on the MOSFET during converter power-up, when no or a too small signal is available on the DMG pin. The starter frequency is 2 kHz if COMP pin is below burst mode threshold; i.e., 1 V, while it becomes 8 kHz if this voltage exceeds this value. After the first few cycles initiated by the starter, as the voltage developed across the auxiliary winding becomes large enough to arm the DMG circuit, MOSFET's turn-on will start to be locked to transformer demagnetization, hence setting up QR operation. The starter is activated also when the IC is in “Constant Current” regulation and the output voltage is not high enough to allow the DMG triggering. If the demagnetization completes - hence a negative-going edge appears on the DMG pin - after a time exceeding time TBLANK from the previous turn-on, the MOSFET will be turned on again, with some delay to ensure minimum voltage at turn-on. If, instead, the negative- going edge appears before TBLANK has elapsed, it will be ignored and only the first negative-going edge after TBLANK will turn-on the MOSFET. In this way one or more drain ringing cycles will be skipped (““valley-skipping mode”, Figure 15) and the switching frequency will be prevented from exceeding 1/TBLANK. Figure 15. Drain ringing cycle skipping as the load is progressively reduced VDS VDS TON TFW TW VDS t TOSC t TOSC Pin = Pin' t TOSC Pin = Pin'' < Pin' Pin = Pin''' < Pin'' (limit condition) Note: 5.5 When the system operates in valley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for cycle-by-cycle energy balance may fall in between. Thus one or more longer switching cycles will be compensated by one or more shorter cycles and vice versa. However, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage. Constant current operation Figure 16 presents the principle used for controlling the average output current of the flyback converter. The voltage of the auxiliary winding is used by the demagnetization block to generate the control signal for the internal MOSFET switch Q. A resistor R in series with it absorbs a current equal to VILED/R, where VILED is the voltage developed across the capacitor CLED capacitor. The flip-flop's output is high as long as the transformer delivers current on secondary side. This is shown in Figure 17. DS9147 - Rev 6 page 16/32 HVLED815PF Constant current operation Figure 16. Current control principle . Iref VILED + R DMG DEMAG LOGIC CC From CS pin Q S Rdmg To PWM Logic Q R Icled Rf b Aux ILED CLED Figure 17. Constant current operation–switching cycle waveforms IPRIM t ISEC t TONSEC Q t ICLED IREF t VILED/R T The capacitor CLED has to be chosen so that its voltage VILED can be considered as a constant. Since it is charged and discharged by currents in the range of some ten µA (IREF = 20 µA typ.) at the switching frequency rate, a capacitance value in the range 4.7–10 nF is suited for switching frequencies in the ten kHz. When high power factor schematic is implemented, a higher capacitor value should be used (i.e., 1–10 µF). The average output current IOUT can be expressed as: DS9147 - Rev 6 page 17/32 HVLED815PF Constant voltage operation I TONSEC IOUT = SEC 2 × T (1) Where ISEC is the secondary peak current, TONSEC is the conduction time of the secondary side, and T is the switching period. Taking into account the transformer ratio N between primary and secondary side, ISEC can also be expressed as a function of the primary peak current IPRIM: As in steady state the average current ICLED: ISEC = N ∙ IPRIM IREF ∙ T − TONSEC + Which can be solved for VILED: V IREF − ILED ∙ TONSEC = 0 R VILED = R × IREF ∙ T T = VCLED ∙ T T ONSEC ONSEC (2) (3) (4) Where VCLED = R * IREF and is internally defined (0.2 V typical–see Table 5). The VILED pin voltage is internally compared with the CS pin voltage (constant current comparator): I VCS = RSENSE ∙ IPRIM = RSENSE ∙ SEC N (5) Combining Eq. (1), Eq. (2), Eq. (4), and Eq. (5), the average output current results: VCLED IOUT = N 2 ∙ RSENSE (6) Eq. (6) shows that the average output current IOUT no longer depends on the input voltage VIN or the output voltage VOUT, nor on transformer inductance values. The external parameters defining the output current are the transformer ratio n and the sense resistor RSENSE. Eq. (6) is valid for both standard and high power factor implementation. 5.6 Constant voltage operation The IC is specifically designed to work in primary regulation and the output voltage is sensed through a voltage partition of the auxiliary winding, just before the auxiliary rectifier diode. Figure 18 shows the internal schematic of the constant voltage mode and the external connections. Due to the parasitic wires resistance, the auxiliary voltage is representative of the output just when the secondary current becomes zero. For this purpose, the signal on DMG pin is sampled-and-held at the end of transformer's demagnetization to get an accurate image of the output voltage and it is compared with the error amplifier internal reference voltage VREF (2.51 V typ. - see Table 5). During the MOSFET's OFF-time the leakage inductance resonates with the drain capacitance and a damped oscillation is superimposed on the reflected voltage. The S/H logic is able to discriminate such oscillations from the real transformer's demagnetization. When the DMG logic detects the transformer's demagnetization, the sampling process stops, the information is frozen and compared with the error amplifier internal reference. The internal error amplifier is a transconductance type and delivers an output current proportional to the voltage unbalance of the two outputs: the output generates the control voltage that is compared with the voltage across the sense resistor, thus modulating the cycle-by-cycle peak drain current. The COMP pin is used for the frequency compensation: usually, an RC network, which stabilizes the overall voltage control loop, is connected between this pin and ground. As a result, the output voltage VOUT at zero-load (i.e., no LED on the LED driver output) can be selected through the RFB resistor in according to the following equation: RFB = RDMG ∙ VREF NAUX − VREF NSEC ∙ VOUT (7) Where NAUX and NSEC are the auxiliary and secondary turn numbers, respectively. The RDMG resistor value can be defined depending on the application parameters (see Section 5.7 ). DS9147 - Rev 6 page 18/32 HVLED815PF Voltage feedforward block Figure 18. Voltage control principle–internal schematic S/H EA + + 2.5V Rf b Aux To PWM Logic - DMG Rdmg DEMAG LOGIC CV From CS pin COMP R C 5.7 Voltage feedforward block The current control structure uses the VCLED voltage to define the output current, according to Eq. (6) in Section 5.5 . Actually, the constant current comparator will be affected by an internal propagation delay TD, which will switch off the MOSFET with a peak current than higher the foreseen value. This current overshoot will be equal to: ∆ IPRIM = VIN ∙ TD LP (8) The previous terms introduce a small error on the calculated average output current set- point, depending on the input voltage. The HVLED815PF device implements a line feedforward function, which solves the issue by introducing an input voltage dependent offset on the current sense signal, in order to adjust the cycle-by-cycle current limitation. The internal schematic is shown in the following figure. Figure 19. Feedforward compensation–internal schematic DRAIN DMG Feedforward Logic . Rfb Aux IFF CC Block - Rdmg PWM LOGIC CC + Rff CS SOURCE Rsense During MOSFET's ON-time the current sourced from DMG pin is mirrored inside the ‘Feedforward Logic’ block in order to provide a feedforward current, IFF. Such ‘feedforward current’ is proportional to the input voltage according to the following equation: DS9147 - Rev 6 page 19/32 HVLED815PF Burst mode operation at no load or very light load N VIN ∙ AUX VIN NPRIM IFF = = m∙R Rdmg dmg (9) Where m is the primary-to-auxiliary turns ratio. According to the schematic in Figure 19, the voltage on the non-inverting comparator will be: V − = RSENSE ∙ ID + IFF ∙ RFF ∙ RSENSE (10) The offset introduced by feedforward compensation will be: VIN VOFFSET = R + RSENSE m ∙ Rdmg ∙ FF (11) As RFF >> RSENSE, the previous one can be simplified as: VIN VOFFSET = m ∙ Rdmg ∙ RFF (12) This offset is proportional to VIN and it is used to compensate the current overshoot, according to the following equation: VIN ∙ TD V ∙ RSENSE = m ∙ RIN ∙R LP dmg FF (13) Finally, the RDMG resistor can be calculated as follows: N LP ∙ RFF Rdmg = AUX ∙ NPRIM TD ∙ RSENSE (14) In this case the peak drain current does not depend on input voltage anymore, and as a consequence the average output current IOUT does not depend on the VIN input voltage. When high power factor is implemented (see Section 5.11 ), the feedforward current has to be minimized because the line regulation is assured by the external offset circuitry (see Figure 1). The maximum value is limited by the minimum IDMG internal current needed to guarantee the correct functionality of the internal circuitry: 5.8 Vin_min ac ∙ 2 N RdmgMAX = N AUX ∙ 100μA PRIM (15) Burst mode operation at no load or very light load When the voltage at the COMP pin falls 65 mV is below the internally fixed threshold VCOMPBM, the IC is disabled with the MOSFET kept in OFF state and its consumption reduced at a lower value to minimize VCC capacitor discharge. In this condition the converter operates in burst mode (one pulse train every TSTART = 500 µs), with minimum energy transfer. As a result of the energy delivery stop, the output voltage decreases: after 500 µs the controller switches on the MOSFET again and the sampled voltage on the DMG pin is compared with the internal reference VREF. If the voltage on the EA output, as a result of the comparison, exceeds the VCOMPL threshold, the device restarts switching, otherwise it stays OFF for another 500 µs period. In this way, the converter will work in burst mode with a nearly constant peak current defined by the internal disable level. A load decrease will then cause a frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulations. This kind of operation, shown in the timing diagrams of Figure 20along with the others previously described, is noise-free since the peak current is low. DS9147 - Rev 6 page 20/32 HVLED815PF Soft-start and starter block Figure 20. Load-dependent operating modes–timing diagrams COMP 50 mV hysteresis (Hys) VCOMPL IDS t Normal-mode 5.9 Burst-mode Normal-mode t Soft-start and starter block The soft-start feature is automatically implemented by the constant current block, as the primary peak current will be limited from the voltage on the CLED capacitor. During the startup, as the output voltage is zero, the IC will start in constant current (CC) mode with no high peak current operations. In this way the voltage on the output capacitor will increase slowly and the soft-start feature will be ensured. Actually, the CLED value is not important to define the soft-start time, as its duration depends on others circuit parameters, like transformer ratio, sense resistor, output capacitors and load. The user will define the best appropriate value by experiments. 5.10 Hiccup mode OCP The device is also protected against short-circuit of the secondary rectifier, short-circuit on the secondary winding or a hard-saturated flyback transformer. An internal comparator monitors continuously the voltage on CS pin and activates a protection circuitry if this voltage exceeds an internally fixed threshold VCSdis (1 V typ., see Table 5). To distinguish an actual malfunction from a disturbance (e.g., induced during ESD tests), the first time the comparator is tripped, the protection circuit enters a “warning state”. If in the subsequent switching cycle the comparator is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; if the comparator will be tripped again a real malfunction is assumed and the device will be stopped. This condition is latched as long as the device is supplied. While it is disabled, however, no energy is coming from the self-supply circuit; hence the voltage on the VCC capacitor will decay and cross the UVLO threshold after some time, which clears the latch. The internal start-up generator is still off, then the VCC voltage still needs to go below its restart voltage before the VCC capacitor is charged again and the device restarted. Ultimately, this will result in a low-frequency intermittent operation (hiccup mode operation), with very low stress on the power circuit. This special condition is illustrated in the timing diagram of Figure 21. DS9147 - Rev 6 page 21/32 HVLED815PF High power factor implementation Figure 21. Hiccup mode OCP–timing diagram VCC Secondary diode is shorted here VccON VccOFF Vccrest t VCS Vcsdis 1V VDS t Two switching cycles t 5.11 High power factor implementation Referring to the application schematic in Figure 1, two contributions are added on the CS pin in order to implement the high power factor capability (trough RPF resistor) and keeping a good line regulation (trough ROS resistor). This application schematic is intended for a single range input voltage. For wide range application a different reference schematic can be used; refer to AN4346 application note for further details. Through the RPF resistor a contribution proportional to the input voltage is added on the CS pin: as a consequence, the input current is proportional to the input voltage during the line period, implementing a high power factor correction. The contribution proportional to the input voltage is generated using the auxiliary winding, as a consequence a diode in series to the RPF resistor is needed. Through the ROS resistor a positive contribution proportional to the average value of the input voltage is added on the CS pin in order to keep a good line regulation. The voltage contribution proportional to the average value of the input voltage is generated through the low pass filter RA/RB resistor and COS capacitor. A diode in series to the RA/RB resistor is suggested to avoid the discharge of COS capacitor in any condition. The R1 resistor between CS and SOURCE pin is needed to add on the CS pin also the contribution proportional the output current trough the RSENSE resistor. DS9147 - Rev 6 page 22/32 HVLED815PF High power factor implementation Figure 22. High power factor implementation connection–single range input DRAIN DMG Feedf orward Logic1 . Rf b Aux IFF CC Block1 - Rdmg PWM LOGIC2 CC + Rf f CS RPF SOURCE R1 ROS VIN (after bridge diode) RA Rsense RB COS The components selection flow starts from the RDMG resistor: this resistor has to be selected in order to minimize the internal feedforward effect. The maximum selectable value is limited by the minimum internal current circuitry IDMG needed to guarantee the correct functionality of the internal circuitry: N V ∙ 2 RdmgMAX = AUX ∙ IN_MIN NPRIM 100μA (16) where NAUX and NPRIM are the auxiliary and primary turn numbers, respectively, and VIN_MIN is the minimum rms input voltage of the application (i.e., 88 V for 110 Vac or 175 V for 230 Vac range). The RFB resistor defines the VOUT output voltage value in the open circuit condition (no-load condition, i.e., no LED on the output of LED driver) and it can be selected using the following relationship: RFB = RDMG ∙ VREF NAUX − VREF NSEC ∙ VOUT (17) where NAUX and NSEC are the auxiliary and secondary turn's number respectively and VREF is the internal reference voltage (VREF = 2.51 V typ., see Table 5). The R1 resistor is typically selected in the range of 500 Ω - 1.5 kΩ in order to minimize the internal feedforward effect and to minimize the power dissipation on the RA/RB resistor offset circuitry. The RA, RB, ROS resistors are selected to add a positive offset on CS pin in order to keep a good line regulation over the input voltage range and cab be selected using the following equation: ROS = R1 ∙ VOS_TYP VCLED ∙ NSEC ∙ 2 ∙ POUT ∙ LP ∙ FSW − 1 VOUT ∙ NPRIM (18) Where VOS_TYP is the desired voltage across COS capacitor applying the VIN_TYP typical input voltage (i.e., VIN_TYP = 220 V for 176/264 Vac input range); FSW is the switching frequency and can be estimated using the following equation, where fT and fR are the transition and resonant frequency respectively: FSW = DS9147 - Rev 6 2 ∙ fT fT fT 1+ + 1+2∙ fR fR (19) page 23/32 HVLED815PF Layout recommendations fT = 1 2 POUT NSEC 1 2 ∙ η ∙ LP ∙ + VIN_TYP ∙ 2 VOUT ∙ NPRIM 1 fR = 2 ∙ π ∙ LP ∙ CD (20) (21) where CD is the total equivalent capacitor afferent at the drain node. Based on the desired voltage across the COS capacitor and calculated ROS resistor, then the sum of RA and RB can then calculated as a result of partitioning divider: RA + RB = ROS ∙ 2 −V VIN_TYP ∙ 2 ∙ π OS_TYP VOS_TYP (22) Using the previous ROS resistor value the RPF resistor can be estimated using the following equation: RPF = N VIN_TYP ∙ 2 ∙ N AUX PRIM NAUX VIN_TYP ∙ 2 ∙ N ∙ ROS + VOS_TYP ∙ RDMG PRIM ∙ ROS ∙ RDMG (23) Finally, the current sense resistor RSENSE can be estimated in order to select the desired average output current value: N V RSENSE = PRIM ∙ 1 ∙ CLED NSEC 2 IOUT (24) Where VCLED is internally defined (0.2 V typ., see Table 5). 5.11.1 System design tips Starting from the previous estimated components value, further fine-tuning on the real LED driver board could be necessary and it can be easily done considering that: 5.12 • Decreasing/increasing the RPF resistor value, the power factor effect increases/decreases. • Decreasing/increasing the ROS resistor value, the line regulation effect increases/decreases. • Decreasing/increasing the ROS resistor value, the RA + RB resistors value should be increased/decreased to keep the desired voltage across the COS capacitor (Eq. (22)). • Decreasing/increasing the RSENSE resistor value the average output current increases/decreases (Eq. (24)). Layout recommendations A proper printed circuit board layout is essential for correct operation of any switch-mode converter, and this is true for the HVLED815PF device as well. Careful component placing, correct traces routing, appropriate traces widths and compliance with isolation distances are the major issues. In particular: • • • • • DS9147 - Rev 6 Current sense resistor (RSENSE) should be connected as close as possible to the SOURCE pin, maintaining the trace for the GND as short as possible. Resistor connected on CS pin (ROS, RPF, R1) should be connected as close as possible to the pin. Compensation network (RCOMP, CCOMP) should be connected as close as possible to the COMP pin, maintaining the trace for the GND as short as possible. Signal ground should be routed separately from power ground, as well from the sense resistor trace. DMG partition resistors (RDMG, RFB) should be connected as close as possible to the DMG pin, minimizing the equivalent parasitic capacitor on DMG pin. page 24/32 HVLED815PF Layout recommendations Figure 23. Suggested routing for the LED driver AC AC VCC DRAIN RDMG DMG RFB COMP ILED GND CS RPF ROS R1 RCOMP CCOMP SOURCE CLED RSENSE DS9147 - Rev 6 page 25/32 HVLED815PF Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 Package mechanical data Figure 24. SO16N package outline 0016020_F DS9147 - Rev 6 page 26/32 HVLED815PF Package mechanical data Table 6. SO16N package mechanical data Symbol Dimensions (mm) Min. Typ. Max. A - - 1.75 A1 0.10 - 0.25 A2 1.25 - - b 0.31 - 0.51 c 0.17 - 0.25 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e - 1.27 - h 0.25 - 0.50 L 0.40 - 1.27 k 0 - 8° ccc - - 0.10 Figure 25. SO16N recommended footprint (dimensions are in mm) DS9147 - Rev 6 page 27/32 HVLED815PF Revision history Table 7. Document revision history Date Revision Changes 26-Jul-2012 1 Initial release. 29-Aug-2012 2 Added Table 2: Pin description on page 7. 23-Oct-2012 3 31-Jan-2013 4 Modified TJ value on Table 3: Thermal data. Updated TJ value in note 2 (below Table 5: Electrical characteristics). Minor text changes. Added sections from 4.1 to 4.12. Modified Figure 1: Application circuit for high power factor LED driver - single range input and Figure 2: Application circuit for standard LED driver. Updated Section : Features on page 1 (replaced ±5% by ±3% in accuracy on constant LED output current). 18-Feb-2014 5 Updated Table 5: Electrical characteristics (updated Test condition, Values and Units of VCLED symbol, added note 6. below Table 5). Updated Section 5: Package information (reversed order of Figure 24: SO16N package outline and Table 6: SO16N package mechanical data, updated titles of Figure 24 and Table 6). Minor modifications throughout document. Throughout document: - minor text edits 13-Sep-2022 6 In Table 5: - added notes below table title (were footnotes 1 and 2); changed footnote numbers: 1 (was 3), 2 (was 4), 3 (was 5), 4 (was 6) - changed VCC_ON maximum value to 14.8 (was 14) DS9147 - Rev 6 page 28/32 HVLED815PF Contents Contents 1 Principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5 3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 5.1 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 Secondary side demagnetization detection and triggering block . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Constant current operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 Constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 Voltage feedforward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.8 Burst mode operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.9 Soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.10 Hiccup mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.11 High power factor implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.11.1 5.12 6 System design tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DS9147 - Rev 6 page 29/32 HVLED815PF List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Device summary . . . . . . . . . . . . Pin description. . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . Absolute maximum ratings . . . . . Electrical characteristics . . . . . . . SO16N package mechanical data Document revision history . . . . . . DS9147 - Rev 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 5 . 6 . 7 . 7 27 28 page 30/32 HVLED815PF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. DS9147 - Rev 6 Application circuit for high power factor LED driver–single range input . Application circuit for standard LED driver . . . . . . . . . . . . . . . . . . . . HVLED815PF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF-state drain and source current test circuit . . . . . . . . . . . . . . . . . COSS output capacitance variation . . . . . . . . . . . . . . . . . . . . . . . . . Startup current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quiescent current test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating supply current test circuit. . . . . . . . . . . . . . . . . . . . . . . . . Quiescent current during fault test circuit . . . . . . . . . . . . . . . . . . . . . Multimode operation of HVLED815PF (constant voltage operation) . . . High voltage start-up generator–internal schematic . . . . . . . . . . . . . . Timing diagram–normal power-up and power-down sequences. . . . . . DMG block, triggering block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drain ringing cycle skipping as the load is progressively reduced . . . . Current control principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant current operation–switching cycle waveforms . . . . . . . . . . . Voltage control principle–internal schematic . . . . . . . . . . . . . . . . . . . Feedforward compensation–internal schematic. . . . . . . . . . . . . . . . . Load-dependent operating modes–timing diagrams. . . . . . . . . . . . . . Hiccup mode OCP–timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . High power factor implementation connection–single range input . . . . Suggested routing for the LED driver . . . . . . . . . . . . . . . . . . . . . . . . SO16N package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO16N recommended footprint (dimensions are in mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 4 . 5 . 9 . 9 10 10 11 11 13 14 15 15 16 17 17 19 19 21 22 23 25 26 27 page 31/32 HVLED815PF IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS9147 - Rev 6 page 32/32