IIS3DWB
Datasheet
Ultra-wide bandwidth, low-noise, 3-axis digital vibration sensor
Features
LGA-14L
(2.5 x 3.0 x 0.83 mm) typ.
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3-axis vibration sensor with digital output
User-selectable full-scale: ±2/±4/±8/±16 g
Ultra-wide and flat frequency response range: from dc to 6 kHz (±3 dB point)
Ultra-low noise density: down to 75 µg/√Hz in 3-axis mode / 60 µg/√Hz in singleaxis mode
High stability of the sensitivity over temperature and against mechanical shocks
Extended temperature range from -40 to +105 °C
Low power: 1.1 mA with all 3 axes delivering full performance
SPI serial interface
Low-pass or high-pass filter with selectable cut-off frequency
Interrupts for wake-up / activity - inactivity / FIFO thresholds
Embedded FIFO: 3 kB
Embedded temperature sensor
Embedded self-test
Supply voltage: 2.1 V to 3.6 V
Compact package: LGA 2.5 x 3 x 0.83 mm 14-lead
ECOPACK, RoHS and “Green” compliant
Applications
Product status link
IIS3DWB
Product summary
Order code
IIS3DWBTR
IIS3DWB
Temp.
range [°C]
-40 to +105
Package
LGA-14
Packing
Tape and
reel
Product labels
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Vibration monitoring
Condition monitoring
Predictive maintenance
Test and measurements
Description
Tray
The IIS3DWB is a system-in-package featuring a 3-axis digital vibration sensor with
low noise over an ultra-wide and flat frequency range. The wide bandwidth, low
noise, very stable and repeatable sensitivity, together with the capability of operating
over an extended temperature range (up to +105 °C), make the device particularly
suitable for vibration monitoring in industrial applications.
The high performance delivered at low power consumption together with the digital
output and the embedded digital features like the FIFO and the interrupts are
enabling features for battery-operated industrial wireless sensor nodes.
The IIS3DWB has a selectable full-scale acceleration range of ±2/±4/±8/±16 g and is
capable of measuring accelerations with a bandwidth up to 6 kHz with an output data
rate of 26.7 kHz. A 3 kB first-in, first-out (FIFO) buffer is integrated in the device to
avoid any data loss and to limit intervention of the host processor.
DS12569 - Rev 6 - August 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
IIS3DWB
The MEMS sensor module family from ST leverages the robust and mature
manufacturing processes already used for the production of micromachined
accelerometers and gyroscopes to serve automotive, industrial and consumer
markets. The sensing elements are manufactured using ST’s proprietary
micromachining process, while the embedded IC interfaces are developed using
CMOS technology.
The IIS3DWB has a self-test capability which allows checking the functioning of the
sensor in the final application. The IIS3DWB is available in a 14-lead plastic land grid
array (LGA) package and is guaranteed to operate over an extended temperature
range from -40 °C to +105 °C.
DS12569 - Rev 6
page 2/59
IIS3DWB
Pin description
1
Pin description
Figure 1. Pin connections
Table 1. Pin desription
Pin #
Name
1
SDO/SA0
2
RES
Function
SPI 4-wire interface serial data output (SDO)
I²C(1) least significant bit of the device address (SA0)
Connect to VDD_IO or GND
3
RES
Connect to VDD_IO or GND
4
INT1
Programmable interrupt #1
5
VDD_IO(2)
6
GND
Connect to GND
7
GND
Connect to GND
8
VDD(2)
9
INT2
Programmable interrupt #2
10
RES
Connect to VDD_IO or leave unconnected(3)
11
RES
Connect to VDD_IO or leave unconnected(3)
Power supply for I/O pins
Power supply
I²C/SPI(1) mode selection
12
CS
(1: SPI idle mode / I²C(1) communication enabled;
0: SPI communication mode / I²C(1) disabled)
13
SPC/SCL
14
SDI/SDO/SDA
SPI serial port clock (SPC)
I²C serial clock (SCL)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
I²C serial data (SDA)
1. Only the SPI interface supports all the device features and capabilities. Due to limited throughput, the I²C interface can be
used only in single-axis mode and it is not recommended.
2. Recommended 100 nF filter capacitor.
3. Leave pin electrically unconnected and soldered to PCB.
DS12569 - Rev 6
page 3/59
IIS3DWB
Default pin configuration
1.1
Default pin configuration
The IIS3DWB default pin configuration and behavior is given in the table below.
Table 2. Default pin status
Pin#
Name
1
SDO/SA0
2
3
Function
Default status
Recommended connection
SPI 4-wire interface serial data output (SDO)
Input without pull-up
I²C least significant bit of the device address
(SA0)
Pull-up is enabled if bit SDO_PU_EN=1 in
reg 02h
Application specific
RES
Reserved
Input without pull-up
Connect to VDD_IO or GND
RES
Reserved
Input without pull-up
Connect to VDD_IO or GND
4
INT1
Programmable interrupt #1
Input with pull-down
5
VDD_IO
Power supply for I/O pin
-
6
GND
Ground
-
Must be set to 0 or left unconnected
during device power-up.
After device power-up, connection is
application specific.
7
GND
Ground
-
8
VDD
Power supply
-
9
INT2
Programmable interrupt #2
Output forced to GND
Application specific
10
RES
Reserved
Input with pull-up
Connect to VDD_IO or leave pin
electrically unconnected and soldered to
PCB
11
RES
Reserved
Input with pull-up
Connect to VDD_IO or leave pin
electrically unconnected and soldered to
PCB
I²C/SPI mode selection
12
CS
(1: SPI idle mode / I²C communication
enabled;
0: SPI communication mode / I²C disabled)
13
SPC/SCL
SPI serial port clock (SPC)
I²C serial clock (SCL)
Input with pull-up
Pull-up is disabled if bit I2C_DISABLE=1
in reg 13h
Application specific
Input without pull-up
Application specific
Input without pull-up
Application specific
SPI serial data input (SDI)
14
SDI/SDO/SDA 3-wire interface serial data output (SDO)
I²C serial data (SDA)
DS12569 - Rev 6
page 4/59
IIS3DWB
Module specifications
2
Module specifications
2.1
Mechanical characteristics
@Vdd = 3.0 V, T = +25 °C unless otherwise noted.
The product is factory calibrated at 3.0 V. The operational power supply range is from 2.1 V to 3.6 V.
Table 3. Mechanical characteristics
Symbol
Parameter
Test conditions
Min.(1)
Typ.(2)
Max.(1)
Unit
±2
FS
±4
Linear acceleration measurement range
g
±8
±16
@FS = ±2 g
So
@FS = ±4 g
Linear acceleration sensitivity(3)
@FS = ±8 g
0.061
-2%
@FS = ±16 g
SoDr
Linear acceleration sensitivity change vs. temperature(4)
TyOff
Linear acceleration zero-g level offset accuracy(5)
TCOff
Linear acceleration zero-g level change vs.
Acceleration noise density 3 axes
delta from T = +25°C
ODR_ACC
enabled(6)
Signal bandwidth
±1
±2
%
±60
+180
mg
mg/°C
X-axis
75
110
Y-axis
75
110
Z-axis
110
190
X-axis
60
90
Y-axis
60
90
Z-axis
80
130
±3 dB point
5
Linear acceleration output data rate
ODR accuracy
mg/LSB
±1
Acceleration noise density only 1 axis enabled(6)
ODR
-180
temperature(4)
An
BW
+2%
0.244
0.488
from -40°C to +105°C
T = 25 °C
0.122
Error wrt 26667 Hz
6.3
kHz
26.667
kHz
±1
@Vdd 3.0 V, T = +25°C
µg/√Hz
±2
%
±0.03
%/°C
Error wrt 26667 Hz
ODR_TC
ODR change vs. temperature
@Vdd 3.0 V,
from -40°C to +105°C
delta from T = +25°C
F0
Sensor resonant frequency
Vst
Linear acceleration self-test output change(7)(8)(9)
Top
Operating temperature range
DS12569 - Rev 6
X-axis
6.9
Y-axis
6.9
Z-axis
7.0
FS = ±4 g
kHz
800
3200
mg
-40
+105
°C
page 5/59
IIS3DWB
Electrical characteristics
1. Min/Max values are based on characterization results at 3σ on a limited number of samples, not tested in
production and not guaranteed.
2. Typical specifications are not guaranteed.
3. Sensitivity values after factory calibration test and trimming.
4. Measurements are performed in a uniform temperature setup and they are based on characterization data
in a limited number of samples. Not measured in production and not guaranteed.
5. Values after factory calibration test and trimming.
6. Frequency range 100 Hz - 6.3 kHz. Noise density is independent of the FS selected.
7. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated
register for all axes.
8. The linear acceleration self-test output change is defined with the device in stationary condition as the
absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb =0.122 mg at
±4 g full scale.
9. Accelerometer self-test limits are full-scale independent. The self-test should be executed with FS setting
≥4 g.
2.2
Electrical characteristics
@ Vdd = 3.0 V, T = 25 °C unless otherwise noted.
Table 4. Electrical characteristics
Symbol
Vdd
Vdd_IO
Idd
IddPD
Ton
VIH(4)
(4)
Parameter
Test conditions
Typ. (2)
Max.(1)
Unit
Supply voltage
2.1
3.6
V
Power supply for I/O
1.62
Vdd + 0.1
V
1.1
1.3
mA
Accelerometer current consumption during power-down
5
16
µA
Turn-on time(3)
10
Accelerometer current consumption
ODR = 26.667 kHz
Digital high-level input voltage
ms
0.7 *VDD_IO
VIL
Digital low-level input voltage
VOH(4)
High-level output voltage
IOH = 4 mA(5)
VOL(4)
Low-level output voltage
IOL = 4 mA(5)
Top
Min.(1)
V
0.3 *VDD_IO
Operating temperature range
VDD_IO - 0.2
-40
V
V
0.2
V
+105(6)
°C
1. Min/Max values are based on characterization results at 3σ, not tested in production and not guaranteed.
2. Typical specifications are not guaranteed.
3. Time to obtain valid data switching from power-down to normal operation.
4. Guaranteed by design characterization and not tested in production.
5. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital
pad in order to guarantee the correct digital output voltage levels VOH and VOL.
6. The IIS3DWB has been qualified with HTOL@125°C for 1000h. In case, in the application, the IIS3DWB
has to be operated frequently at high temperature (>50°C), it is recommended, in order to maximize its
lifetime, to switch off the sensor, by setting its power supplies to 0 V, when the sensor is not needed to
perform measurements. The lower the duty cycle of the IIS3DWB in powered condition, the longer the
lifetime of the device which can be extrapolated based on the results of reliability trials.
DS12569 - Rev 6
page 6/59
IIS3DWB
Temperature sensor characteristics
2.3
Temperature sensor characteristics
@ Vdd = 3.0 V, T = 25 °C unless otherwise noted.
The product is factory calibrated at 3.0 V.
Symbol
TODR
Toff
TSen
T_delta_Acc
Parameter
Test condition
Min.(1)
Temperature refresh rate
Temperature
-15
Temperature sensitivity
Delta temperature
Max.(1)
104
offset(3)
accuracy(4)
Typ.(2)
Hz
+15
256
from 25°C to 105°C
Unit
°C
LSB/°C
4
°C
Temperature stabilization time(5)
10
ms
T_ADC_res
Temperature ADC resolution
16
bit
Top
Operating temperature range
TST
-40
+105
°C
1. Min/Max values are based on characterization results at 3σ on a limited number of samples, not tested in
production and not guaranteed.
2. Typical specifications are not guaranteed.
3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C. Absolute temperature accuracy can be
improved (reducing the effect of temperature offset) by performing OPC (one-point calibration) at room
temperature (25 °C).
4. Applicable if temperature offset is removed with OPC (one-point calibration) at room temperature (25 °C).
5. Time from power ON to valid output data.
DS12569 - Rev 6
page 7/59
IIS3DWB
Communication interface characteristics
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values
Symbol
Parameter
Value(1)
Min
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
20
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
SDO output disable time
Max
Unit
ns
100
10
MHz
ns
50
5
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
Figure 2. SPI slave timing diagram
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
DS12569 - Rev 6
page 8/59
IIS3DWB
Absolute maximum ratings
2.5
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device under these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
Table 6. Absolute maximum ratings
Symbol
Ratings
Maximum value
Unit
Vdd
Supply voltage
-0.3 to 4.8
V
TSTG
Storage temperature range
-40 to +125
°C
10,000
g
2
kV
0.3 to Vdd_IO +0.3
V
Sg
ESD
Vin
Acceleration g for 0.2 ms
Electrostatic discharge protection (HBM)
Input voltage on any control pin
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Note: Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS12569 - Rev 6
page 9/59
IIS3DWB
Terminology
2.6
2.6.1
Terminology
Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device.
Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards
the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the
output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value
from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes
very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large
number of sensors (see Table 3).
2.6.2
Zero-g level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on
both the X-axis and Y-axis, whereas the Z-axis will measure 1 g. Ideally, the output is in the middle of the dynamic
range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from
the ideal value in this case is called zero-g offset.
Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after
mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes
little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 3. The zero-g level
tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors.
DS12569 - Rev 6
page 10/59
IIS3DWB
Digital interface
3
Digital interface
3.1
SPI interface
The registers embedded inside the IIS3DWB may be accessed through the SPI serial interface that can be SW
configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3.
The SPI interface is mapped to the same pins as an I²C interface. However, since it is only with the throughput of
the SPI interface that all the device features and capabilities are supported, the I²C interface is not described. To
select/exploit the I²C interface, the CS line must be tied high (i.e connected to Vdd_IO).
Table 7. Serial interface pin description
Pin name
Pin description
SPI enable
CS
I²C(1)/SPI mode selection
(1: SPI idle mode / I²C(1) communication enabled;
0: SPI communication mode / I²C(1) disabled)
SPC/SCL
SPI serial port clock (SPC)
I²C(1) serial clock (SCL)
SPI serial data input (SDI)
SDI/SDO/SDA
3-wire interface serial data output (SDO)
I²C(1) serial data (SDA)
SDO/SA0
SPI 4-wire interface serial data output (SDO)
I²C(1) least significant bit of the device address (SA0)
1. Only the SPI interface supports all the device features and capabilities. Due to limited throughput, the I²C interface can be
used only in single-axis mode and it is not recommended.
DS12569 - Rev 6
page 11/59
IIS3DWB
SPI bus interface
3.2
SPI bus interface
The IIS3DWB SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.
The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO.
Figure 3. Read and write protocol (in mode 3)
CS
SPC
SDI
RW
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and
goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high
when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those
lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case
of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at
the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling
edge of SPC just before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is
read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the CTRL3_C (12h)
(IF_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL3_C
(12h) (IF_INC) bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
DS12569 - Rev 6
page 12/59
IIS3DWB
SPI bus interface
3.2.1
SPI read
Figure 4. SPI read protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by
adding blocks of 8 clock pulses to the previous one.
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...: data DO(...-8). Further data in multiple byte reads.
Figure 5. Multiple byte SPI read protocol (2-byte example) (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14DO13DO12 DO11DO10 DO9 DO8
DS12569 - Rev 6
page 13/59
IIS3DWB
SPI bus interface
3.2.2
SPI write
Figure 6. SPI write protocol (in mode 3)
CS
SPC
SDI
RW
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by
adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 7. Multiple byte SPI write protocol (2-byte example) (in mode 3)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
3.2.3
SPI read in 3-wire mode
A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial interface mode
selection).
Figure 8. SPI read protocol in 3-wire mode (in mode 3)
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
DS12569 - Rev 6
page 14/59
IIS3DWB
Functionality
4
Functionality
4.1
Operating modes
The IIS3DWB has two operating modes:
•
3-axis mode: all three axes (X, Y, Z) are simultaneously active and acceleration data can be read from the
sensor concurrently for the 3-axis (using registers OUTX_L_A (28h) and OUTX_H_A (29h); OUTY_L_A
(2Ah) and OUTY_H_A (2Bh); OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) or the FIFO registers:
FIFO_DATA_OUT (79h – 7Eh)
•
single-axis mode: only one axis is active. The active axis, among X or Y or Z, can be selected when the
device is in power-down mode. Acceleration data can be read from the registers associated with the active
axis or from the corresponding registers of the FIFO.
In single-axis mode, while the power consumption of IIS3DWB remains the same as 3-axis mode, the resolution
(noise density) of the active axis significantly improves.
To change the configuration of the active axis, the device should be in power-down mode. An example of the
procedure that can be applied is:
Set the device in power-down mode: CTRL1_XL (10h) XL_EN[2:0] = 000b
Enable the axis: CTRL6_C (15h) XL_AXIS_SEL[1:0] = xxb (00 = 3 axes; 01 = X-axis; 10 = Y-axis ; 11 = Z-axis)
Enable the device: CTRL1_XL (10h) XL_EN[2:0] = 101b
DS12569 - Rev 6
page 15/59
IIS3DWB
Block diagrams
4.2
Block diagrams
The IIS3DWB architecture is composed of the following functional blocks:
•
MEMS mechanical element
•
ADC
•
Low-pass digital filter (LPF1)
•
Composite filter
Figure 9. Accelerometer architecture
X A2D
M
E
M
S
S
E
N
S
O
R
dC/dV
converter
I2C/SPI
Interface
Low Pass
Filter
(LPF1)
A2D
Composite
Filter
Digital
Processing
and
functions
ZA2D
Temperature
sensor
Voltage and
current
reference
Interrupt
Mgmt
CS
SCL/SPC
SDA/SDIO
SDO
INT1
INT2
A2D
Trimming Circuit
& Test Interface
Clock & Phase
Generator
Power
Management
NVM Memory
Figure 10. Accelerometer composite filter
0
0
LPF2
1
User
Offset
1
USR_OFF_W
OFS_USR[7:0]
USR_OFF_ON_OUT
HPCF_XL_[2:0]
LPF2_XL_EN
ADC
LPF1
SPI/I2C
1
0
Wake-up
0
0
1
Activity /
Inactiivity
1
USR_OFF_ON_WU
FIFO
SLOPE_FDS
HPF
FDS
HPCF_XL_[2:0]
Slope
Filter
DS12569 - Rev 6
HPCF_XL_[2:0]
page 16/59
IIS3DWB
FIFO
4.3
FIFO
The presence of a FIFO allows consistent power saving for the system since the host processor does not need to
continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out
from the FIFO.
The IIS3DWB embeds 3 kbytes of data in FIFO to store the following data:
•
Accelerometer
•
Timestamp
•
Temperature
Writing data in the FIFO is triggered by the accelerometer data-ready signal.
It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32 compared to the
accelerometer BDR (Batch Data Rate).
The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows
recognizing the meaning of a word in FIFO.
FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the
BDR configuration is performed, the application can correctly reconstruct the timestamp and know exactly when
the change was applied without disabling FIFO batching. FIFO stores information of the new configuration and
timestamp in which the change was applied in the device.
The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) using the
WTM[8:0] bits. To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh))
can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the
number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of
these status events, the configuration can be set in INT1_CTRL (0Dh) and INT2_CTRL (0Eh).
The FIFO buffer can be configured according to six different modes:
•
Bypass mode
•
FIFO mode
•
Continuous mode
•
Continuous-to-FIFO mode
•
Bypass-to-Continuous mode
•
Bypass-to-FIFO mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register.
4.3.1
Bypass mode
In Bypass mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains
empty. Bypass mode is also used to reset the FIFO when in FIFO mode.
4.3.2
FIFO mode
In FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the
FIFO until it is full.
To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0]) to
'000'. After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL4 (0Ah)
(FIFO_MODE_[2:0]) to '001'.
The FIFO buffer memorizes up to 3 kbytes of data but the depth of the FIFO can be resized by setting the WTM
[8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). If the STOP_ON_WTM bit in FIFO_CTRL2 (08h) is set to
'1', FIFO depth is limited up to the WTM [8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h).
DS12569 - Rev 6
page 17/59
IIS3DWB
FIFO
4.3.3
Continuous mode
Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new
data arrives, the older data is discarded.
A FIFO threshold flag FIFO_STATUS2 (3Bh)(FIFO_WTM_IA) is asserted when the number of unread samples in
FIFO is greater than or equal to FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)(WTM [8:0]).
It is possible to route the FIFO_WTM_IA flag to the INT1 pin by writing in register INT1_CTRL (0Dh)
(INT1_FIFO_TH) = '1' or to the INT2 pin by writing in register INT2_CTRL (0Eh)(INT2_FIFO_TH) = '1'.
A full-flag interrupt can be enabled, INT1_CTRL (0Dh)(INT1_FIFO_FULL) = '1' or INT2_CTRL (0Eh)
(INT2_FIFO_FULL) = '1', in order to indicate FIFO saturation and eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag
in FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples
available in FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)(DIFF_FIFO_[9:0]).
4.3.4
Continuous-to-FIFO mode
In Continuous-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 011), FIFO behavior changes according
to the trigger event (wake-up) detected.
When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.
When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
4.3.5
Bypass-to-Continuous mode
In Bypass-to-Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '100'), data measurement storage
inside FIFO operates in Continuous mode when selected triggers are equal to '1', otherwise FIFO content is reset
(Bypass mode).
FIFO behavior changes according to the trigger event detected (wake-up).
4.3.6
Bypass-to-FIFO mode
In Bypass-to-FIFO mode FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '111'), data measurement storage inside FIFO
operates in FIFO mode when selected triggers (Wake-up) are equal to '1', otherwise FIFO content is reset
(Bypass mode)
4.3.7
FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes:
one tag byte (FIFO_DATA_OUT_TAG (78h), in order to identify the sensor, and 6 bytes of fixed data
(FIFO_DATA_OUT registers from (79h) to (7Eh)).
The DIFF_FIFO_[9:0] field in the FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) registers contains the number
of words (1 byte TAG + 6 bytes DATA) collected in FIFO.
In addition, it is possible to configure a counter of the batch events of the sensor. The flag COUNTER_BDR_IA in
FIFO_STATUS2 (3Bh) alerts that the counter has reached a selectable threshold (CNT_BDR_TH_[10:0] field in
COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows triggering the reading of FIFO
with the desired latency of one single sensor. The sensor is selectable using the TRIG_COUNTER_BDR bit in
COUNTER_BDR_REG1 (0Bh). As for the other FIFO status events, the flag COUNTER_BDR_IA can be routed
on the INT1 or INT2 pins by asserting the corresponding bits (INT1_CNT_BDR of INT1_CTRL (0Dh) and
INT2_CNT_BDR of INT2_CTRL (0Eh)).
DS12569 - Rev 6
page 18/59
IIS3DWB
Frequency response
5
Frequency response
The IIS3DWB has been specifically designed to provide a wide bandwidth with very flat frequency response in the
pass band and a very high attenuation in the stop band so to virtually eliminate any frequency aliasing.
The following figure illustrates the filtering chain and its components.
Figure 11. Filtering chain
f0=7 kHz
MEMS
Analog
Front-end+
ADC
Low-Pass
Filter
ADC
LPF1
26.7 kHz
Composite
Filter
Composite Filter
The output of the ADC converter is filtered with a digital low-pass filter to ensure the intended sensor’s frequency
response. The frequency response at the output of the LPF1 filter is indicated in the following figure.
Figure 12. Frequency response at the output of LPF1 filter
Note: Frequency response determined by CAD simulation – at the output of LPF1.
After the LPF1 filter, it is possible to enable another level of digital filtering through the digital composite filter (refer
to Figure 10. Accelerometer composite filter).
The digital composite filter could be:
•
High-pass filter
•
Low-pass filter
DS12569 - Rev 6
page 19/59
IIS3DWB
Frequency response
Figure 13. Frequency response with LPF2 enabled
Note: Frequency response determined by CAD simulation
Figure 14. Frequency response with HPF enabled
Note: Frequency response determined by CAD simulation
DS12569 - Rev 6
page 20/59
IIS3DWB
Typical performance characteristics
6
Typical performance characteristics
6.1
Frequency response measurements
The frequency response of the IIS3DWB, measured on a mechanical shaker, is indicated in the following figures.
Measurements have been performed with the IIS3DWB configured with the digital composite filter bypassed.
Figure 15. Frequency response - X-axis
Note: Characterization data on 10 parts. Not measured in production and not guaranteed.
Figure 16. Frequency response - Y-axis
Note: Characterization data on 10 parts. Not measured in production and not guaranteed.
DS12569 - Rev 6
page 21/59
IIS3DWB
Frequency response measurements
Figure 17. Frequency response - Z-axis
Note: Characterization data on 10 parts. Not measured in production and not guaranteed.
DS12569 - Rev 6
page 22/59
IIS3DWB
Sensitivity change versus temperature
6.2
Sensitivity change versus temperature
Figure 18. Sensitivity change versus temperature
Note: Characterization data. Not measured in production and not guaranteed.
6.3
ODR change versus temperature
Figure 19. ODR change versus temperature
Note: Characterization data. Not measured in production and not guaranteed.
DS12569 - Rev 6
page 23/59
IIS3DWB
Application hints
7
Application hints
7.1
IIS3DWB electrical connections
CS
SPC/SCL
SDI/SDO/SDA
Figure 20. IIS3DWB electrical connections
HOST
12
14
I2C/SPI (3/4-w)
1
SDO/SA0
11
TOP
VIEW
RES (1)
IIS3DWB
RES (1)
INT2
GND or Vdd IO
4
INT1
8
Vdd
VDD
C1
C2
Vdd_IO
GND
GND
7
GND
VDD_IO
5
I2C configuration
100nF
Rpu
Rpu
SCL
Vdd_IO
100nF
GND
SDA
Pull-up to be added
Rpu=10kOhm
The device core is supplied through the Vdd line while the I/O pads are supplied through the Vdd_IO line. Power
supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the the supply
pin of the device (common design practice).
The functionality of the device and the measured acceleration data are selectable and accessible through the I²C
or SPI interfaces. When using the I²C protocol, CS must be tied high. Every time the CS line is set to low level,
the I²C bus is internally reset.
All the functions, the threshold and the timing of the two interrupt pins can be completely programmed by the user
through the I²C/SPI interface.
Note: Only the SPI interface supports all the device features and capabilities. The I²C interface can be used only
in single-axis mode and it is not recommended.
DS12569 - Rev 6
page 24/59
IIS3DWB
Measuring the actual ODR
7.2
Measuring the actual ODR
For applications requiring higher ODR accuracy, it is possible to configure the device to generate an interrupt
signal on the INT1/2 pin each time new data is generated. By using an accurate timer (i.e. with a microcontroller)
it is possible to measure the time interval between consecutive interrupt signals obtaining a very accurate value of
the actual ODR of the device.
In order to enable the generation of the data_ready interrupt on the INT1 or INT2 pin:
•
The dataready_pulsed bit of the COUNTER_BDR_REG1 (0Bh) register should to be set to 1 (optional)
•
The INTx_ DRDY_XL bit of the INT1_CTRL (0Dh) / INT2_CTRL (0Eh) register has to be set to 1
Figure 21. Accurately measuring ODR
SPI
µC
IIS3DWB
INT1/2 pin
DS12569 - Rev 6
page 25/59
IIS3DWB
Register mapping
8
Register mapping
The table given below provides a listing of the 8/16-bit registers embedded in the device and the corresponding
addresses.
Table 8. Register address map
DS12569 - Rev 6
Name
Type
RESERVED
-
Register address
Hex
Binary
Default
Comment
01
PIN_CTRL
RW
02
RESERVED
-
03-06
00000010
00111111
FIFO_CTRL1
RW
07
00000111
00000000
FIFO_CTRL2
RW
08
00001000
00000000
FIFO_CTRL3
RW
09
00001001
00000000
FIFO_CTRL4
RW
0A
00001010
00000000
COUNTER_BDR_REG1
RW
0B
00001011
00000000
COUNTER_BDR_REG2
RW
0C
00001100
00000000
INT1_CTRL
RW
0D
00001101
00000000
INT2_CTRL
RW
0E
00001110
00000000
WHO_AM_I
R
0F
00001111
01111011
CTRL1_XL
RW
10
00010000
00000000
RESERVED
-
11
CTRL3_C
RW
12
00010010
00000100
CTRL4_C
RW
13
00010011
00000000
CTRL5_C
RW
14
00010100
00000000
CTRL6_C
RW
15
00010101
00000000
CTRL7_C
RW
16
00011100
00000000
CTRL8_XL
RW
17
00010111
00000000
RESERVED
-
18
CTRL10_C
RW
19
00011001
00000000
ALL_INT_SRC
R
1A
00011010
output
WAKE_UP_SRC
R
1B
00011011
output
RESERVED
-
1C-1D
STATUS_REG
R
1E
00011110
output
RESERVED
-
1F
00011111
OUT_TEMP_L
R
20
00100000
output
OUT_TEMP_H
R
21
00100001
output
RESERVED
-
22-27
OUTX_L_A
R
28
00101000
output
OUTX_H_A
R
29
00101001
output
OUTY_L_A
R
2A
00101010
output
page 26/59
IIS3DWB
Register mapping
DS12569 - Rev 6
Name
Type
OUTY_H_A
Register address
Default
Hex
Binary
R
2B
00101011
output
OUTZ_L_A
R
2C
00101100
output
OUTZ_H_A
R
2D
00101101
output
RESERVED
-
2E-39
FIFO_STATUS1
R
3A
00111010
output
FIFO_STATUS2
R
3B
00111011
output
RESERVED
-
3C-3F
TIMESTAMP0
R
40
01000000
output
TIMESTAMP1
R
41
01000001
output
TIMESTAMP2
R
42
01000010
output
TIMESTAMP3
R
43
01000011
output
RESERVED
-
44-55
SLOPE_EN
RW
56
01010111
00000000
RESERVED
-
57
INTERRUPTS_EN
RW
58
01011000
00000000
RESERVED
-
59-5A
WAKE_UP_THS
RW
5B
01011011
00000000
WAKE_UP_DUR
RW
5C
01011100
00000000
RESERVED
-
5D
MD1_CFG
RW
5E
01011110
00000000
MD2_CFG
RW
5F
01011111
00000000
RESERVED
-
60-62
INTERNAL_FREQ_FINE
R
63
01100011
output
RESERVED
-
64-72
X_OFS_USR
RW
73
01110011
00000000
Y_OFS_USR
RW
74
01110100
00000000
Z_OFS_USR
RW
75
01110101
00000000
RESERVED
-
76-77
FIFO_DATA_OUT_TAG
R
78
01111000
output
FIFO_DATA_OUT_X_L
R
79
01111001
output
FIFO_DATA_OUT_X_H
R
7A
01111010
output
FIFO_DATA_OUT_Y_L
R
7B
01111011
output
FIFO_DATA_OUT_Y_H
R
7C
01111100
output
FIFO_DATA_OUT_Z_L
R
7D
01111101
output
FIFO_DATA_OUT_Z_H
R
7E
01111110
output
Comment
page 27/59
IIS3DWB
Register description
9
Register description
9.1
PIN_CTRL (02h)
SDO pin pull-up enable/disable register (r/w)
Table 9. PIN_CTRL register
0
SDO_PU_EN
1
1
1
1
1
1
WTM1
WTM0
Table 10. PIN_CTRL register description
SDO_PU_EN
9.2
Enable pull-up on SDO pin
(0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up)
FIFO_CTRL1 (07h)
FIFO control register 1 (r/w)
Table 11. FIFO_CTRL1 register
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
Table 12. FIFO_CTRL1 register description
FIFO watermark threshold, in conjunction with WTM8 in FIFO_CTRL2 (08h).
WTM[7:0] 1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.
9.3
FIFO_CTRL2 (08h)
FIFO control register 2 (r/w)
Table 13. FIFO_CTRL2 register
STOP_ON
_WTM
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
WTM8
1. This bit must be set to '0' for the correct operation of the device.
Table 14. FIFO_CTRL2 register description
Sensing chain FIFO stop values memorization at threshold level
STOP_ON_WTM (0: FIFO depth is not limited (default);
1: FIFO depth is limited to threshold level, defined in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h))
FIFO watermark threshold, in conjunction with WTM_FIFO[7:0] in FIFO_CTRL1 (07h)
WTM8
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold
level.
DS12569 - Rev 6
page 28/59
IIS3DWB
FIFO_CTRL3 (09h)
9.4
FIFO_CTRL3 (09h)
FIFO control register 3 (r/w)
Table 15. FIFO_CTRL3 register
0(1)
0(1)
0(1)
0(1)
BDR_XL_3
BDR_XL_2
BDR_XL_1
BDR_XL_0
FIFO_
MODE_1
FIFO_
MODE_0
1. This bit must be set to '0' for the correct operation of the device.
Table 16. FIFO_CTRL3 register description
Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.
(0000: Accelerometer not batched in FIFO (default);
BDR_XL_[3:0]
1010: 26667 Hz;
1011 - 1111: not allowed)
9.5
FIFO_CTRL4 (0Ah)
FIFO control register 4 (r/w)
Table 17. FIFO_CTRL4 register
DEC_TS_
BATCH_1
DEC_TS_
BATCH_0
ODR_T_
BATCH_1
ODR_T_
BATCH_0
0(1)
FIFO_
MODE_2
1. This bit must be set to '0' for the correct operation of the device.
Table 18. FIFO_CTRL4 register description
Selects decimation for timestamp batching in FIFO.
Write rate will be the rate between XL BDR divided by decimation decoder.
DEC_TS_ BATCH[1:0]
(00: Timestamp not batched in FIFO (default);
01: Decimation 1: BDR_XL[Hz];
10: Decimation 8: BDR_XL[Hz]/8;
11: Decimation 32: BDR_XL[Hz]/32)
Selects batch data rate (write frequency in FIFO) for temperature data
ODR_T_ BATCH[1:0]
(00: Temperature not batched in FIFO (default);
11: 104 Hz)
FIFO mode selection
(000: Bypass mode: FIFO disabled;
001: FIFO mode: stops collecting data when FIFO is full;
010: Reserved;
FIFO_ MODE[2:0]
011: Continuous-to-FIFO mode: Continuous mode until trigger is deasserted, then FIFO mode;
100: Bypass-to-Continuous mode: Bypass mode until trigger is deasserted, then Continuous mode;
101: Reserved;
110: Continuous mode: if the FIFO is full, the new sample overwrites the older one;
111: Bypass-to-FIFO mode: Bypass mode until trigger is deasserted, then FIFO mode.)
DS12569 - Rev 6
page 29/59
IIS3DWB
COUNTER_BDR_REG1 (0Bh)
9.6
COUNTER_BDR_REG1 (0Bh)
Counter batch data rate register 1 (r/w)
Table 19. COUNTER_BDR_REG1 register
dataready
_pulsed
RST_
COUNTER
_BDR
0(1)
0(1)
0(1)
CNT_BDR
_TH_10
CNT_BDR
_TH_9
CNT_BDR
_TH_8
1. This bit must be set to '0' for the correct operation of the device.
Table 20. COUNTER_BDR_REG1 register description
Enables pulsed data-ready mode
dataready_pulsed
9.7
(0: Data-ready latched mode (returns to 0 only after an interface reading) (default); 1: Data-ready
pulsed mode (the data ready pulses are 18.75 µs long)
RST_
COUNTER_BDR
Resets the internal counter of batch events. This bit is automatically reset to zero if it was set to ‘1’.
CNT_BDR_TH_
[10:8]
In conjunction with CNT_BDR_TH[7:0] in COUNTER_BDR_REG2 (0Ch), sets the threshold for the
internal counter of batch events. When this counter reaches the threshold, the counter is reset and the
COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.
COUNTER_BDR_REG2 (0Ch)
Counter batch data rate register 2(r/w)
Table 21. COUNTER_BDR_REG2 register
CNT_BDR
_TH_7
CNT_BDR
_TH_6
CNT_BDR
_TH_5
CNT_BDR
_TH_4
CNT_BDR
_TH_3
CNT_BDR
_TH_2
CNT_BDR
_TH_1
CNT_BDR
_TH_0
Table 22. COUNTER_BDR_REG2 register description
CNT_BDR_TH_
[7:0]
DS12569 - Rev 6
In conjunction with CNT_BDR_TH[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the
internal counter of batch events. When this counter reaches the threshold, the counter is reset and the
COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.
page 30/59
IIS3DWB
INT1_CTRL (0Dh)
9.8
INT1_CTRL (0Dh)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried over INT1.
Table 23. INT1_CTRL register
0(1)
INT1_
CNT_BDR
INT1_
FIFO _FULL
INT1_
FIFO_ OVR
INT1_
FIFO_TH
INT1_
BOOT
0(1)
INT1_
DRDY_XL
0(1)
INT2_
DRDY_XL
1
1
1. This bit must be set to '0' for the correct operation of the device.
Table 24. INT1_CTRL register description
9.9
INT1_CNT_BDR
Enables COUNTER_BDR_IA interrupt on INT1.
INT1_ FIFO _FULL
Enables FIFO full flag interrupt on INT1 pin.
INT1_ FIFO_ OVR
Enables FIFO overrun interrupt on INT1 pin.
INT1_FIFO_TH
Enables FIFO threshold interrupt on INT1 pin.
INT1_BOOT
Enables boot status on INT1 pin
INT1_ DRDY_XL
Enables accelerometer data-ready interrupt on INT1 pin.
INT2_CTRL (0Eh)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried over INT2.
Table 25. INT2_CTRL register
0(1)
INT2_
CNT_BDR
INT2_
FIFO _FULL
INT2_
FIFO_ OVR
INT2_
FIFO_TH
INT2_
DRDY_TEMP
1. This bit must be set to '0' for the correct operation of the device.
Table 26. INT2_CTRL register description
9.10
INT2_CNT_BDR
Enables COUNTER_BDR_IA interrupt on INT2.
INT2_ FIFO _FULL
Enables FIFO full flag interrupt on INT2 pin.
INT2_ FIFO_ OVR
Enables FIFO overrun interrupt on INT2 pin.
INT2_FIFO_TH
Enables FIFO threshold interrupt on INT2 pin.
INT2_DRDY_TEMP
Enables temperature sensor data-ready interrupt on INT2 pin.
INT2_ DRDY_XL
Enables accelerometer data-ready interrupt on INT2 pin.
WHO_AM_I (0Fh)
Device identification register
Table 27. WHO_AM_I register
0
DS12569 - Rev 6
1
1
1
1
0
page 31/59
IIS3DWB
CTRL1_XL (10h)
9.11
CTRL1_XL (10h)
Accelerometer control register 1 (r/w)
Table 28. CTRL1_XL register
XL_EN_2
XL_EN_1
XL_EN_0
0(1)
FS1_XL
FS0_XL
LPF2_XL_EN
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 29. CTRL1_XL register description
Enables accelerometer:
XL_EN[2:0]
(000: Power-down (default);
101: accelerometer enabled;)
All other configurations are not allowed.
FS[1:0]_XL
Selects accelerometer full-scale (see Table 30).
Selects accelerometer high-resolution.
LPF2_XL_EN
(0: output from first stage digital filtering selected (default);
1: output from LPF2 second filtering stage selected)
Table 30. Accelerometer full-scale selection
DS12569 - Rev 6
FS[1:0]_XL
Full scale
00 (default)
±2 g
01
±16 g
10
±4 g
11
±8 g
page 32/59
IIS3DWB
CTRL3_C (12h)
9.12
CTRL3_C (12h)
Control register 3 (r/w)
Table 31. CTRL3_C register
BOOT
BDU
H_LACTIVE
PP_OD
SIM
IF_INC
0(1)
SW_RESET
1. This bit must be set to '0' for the correct operation of the device.
Table 32. CTRL3_C register description
Reboots memory content. Default value: 0
BOOT
(0: normal mode; 1: reboot memory content)
Note: the accelerometer must be ON. This bit is automatically cleared.
Block Data Update. Default value: 0
BDU
(0: continuous update;
1: output registers are not updated until MSB and LSB have been read)
H_LACTIVE
PP_OD
SIM
IF_INC
Interrupt activation level. Default value: 0
(0: interrupt output pins active high; 1: interrupt output pins active low)
Push-pull/open-drain selection on INT1 and INT2 pins. Default value: 0
(0: push-pull mode; 1: open-drain mode)
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).
Default value: 1
(0: disabled; 1: enabled)
Software reset. Default value: 0
SW_RESET (0: normal mode; 1: reset device)
This bit is automatically cleared.
DS12569 - Rev 6
page 33/59
IIS3DWB
CTRL4_C (13h)
9.13
CTRL4_C (13h)
Control register 4 (r/w)
Table 33. CTRL4_C register
0(1)
INT2_
on_INT1
0(1)
DRDY_
MASK
0(1)
0(1)
I2C_disable
1AX_TO_
3REGOUT
1. This bit must be set to '0' for the correct operation of the device.
Table 34. CTRL4_C register description
Enables bit to route all interrupt signals available on INT1 pin. Default value: 0
INT2_on_INT1
(0: interrupt signals divided between INT1 and INT2 pins;
1: all interrupt signals in logic OR on INT1 pin)
Enables data available
DRDY_MASK
(0: disabled;
1: mask DRDY on pin until filter settling ends.
Disables I²C interface. Default value: 0
I2C_disable
(0: SPI and I²C interfaces enabled (default); 1: I²C interface disabled)
1AX_TO_3REGOUT
9.14
In single-axis mode, uses output of XYZ registers to give 3 consecutive samples of the selected single
axis.
CTRL5_C (14h)
Control register 5 (r/w)
Table 35. CTRL5_C register
0(1)
ROUNDING1
ROUNDING0
0(1)
0(1)
0(1)
ST1_XL
ST0_XL
1. This bit must be set to '0' for the correct operation of the device.
Table 36. CTRL5_C register description
Circular burst-mode (rounding) read from the output registers. Default value: 00
ROUNDING[1:0]
(00: no rounding;
01: rounding enabled)
Linear acceleration sensor self-test enable. Default value: 00
ST[1:0]_XL
(00: Self-test disabled; Other: refer to Table 37)
Table 37. Linear acceleration sensor self-test mode selection
DS12569 - Rev 6
ST1_XL
ST0_XL
Self-test mode
0
0
Normal mode
0
1
Positive sign self-test
1
0
Negative sign self-test
1
1
Not allowed
page 34/59
IIS3DWB
CTRL6_C (15h)
9.15
CTRL6_C (15h)
Control register 6 (r/w)
Table 38. CTRL6_C register
0(1)
0(1)
0(1)
0(1)
USR_
OFF_W
0(1)
XL_AXIS_
SEL_1
XL_AXIS_
SEL_0
1. This bit must be set to '0' for the correct operation of the device.
Table 39. CTRL6_C register description
Weight of XL user offset bits of registers X_OFS_USR (73h), Y_OFS_USR (74h), Z_OFS_USR (75h)
USR_OFF_W
(0 = 2-10 g/LSB;
1 = 2-6 g/LSB)
Selects the active axis of the accelerometer in single-axis mode. Refer to Table 40
XL_AXIS_SEL[1:0] The selection or the switching of the active axis (3 axes or 1 axis among X, Y, Z) should be performed
when the device is in power-down condition
Table 40. Accelerometer active axis
9.16
XL_AXIS_ SEL[1:0]
Active axis
00 (default)
3 axes (XYZ)
01
X-axis
10
Y-axis
11
Z-axis
CTRL7_C (16h)
Control register 7 (r/w)
Table 41. CTRL7_C register
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
USR_OFF_
ON_OUT
0(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 42. CTRL7_C register description
Enables the accelerometer user offset correction block; it’s valid for the low-pass path - see
Figure 10. Accelerometer composite filter. Default value: 0
USR_OFF_ON_OUT
(0: accelerometer user offset correction block bypassed;
(1: accelerometer user offset correction block enabled)
DS12569 - Rev 6
page 35/59
IIS3DWB
CTRL8_XL (17h)
9.17
CTRL8_XL (17h)
Control register 8 (r/w)
Table 43. CTRL8_XL register
HPCF_XL_2
HPCF_XL_1
HP_REF_
MODE_XL
HPCF_XL_0
FASTSETTL_
MODE_XL
FDS
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 44. CTRL8_XL register description
HPCF_XL_[2:0]
Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to Table 45.
HP_REF_MODE_XL
Enables accelerometer high-pass filter reference mode (valid for high-pass path - FDS bit must be
‘1’ and HPCF_XL_[2:0] must be set to “111”). Default value: 0(1)
(0: disabled, 1: enabled)
Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after
FASTSETTL_MODE_XL writing this bit. Default value: 0
(0: disabled, 1: enabled)
FDS
Accelerometer low-pass / high-pass filter selection. Refer to Figure 10.
1. When enabled, the first output data have to be discarded.
Table 45. Accelerometer bandwidth configurations
Filter type
Low pass
High pass
DS12569 - Rev 6
FDS
0
1
LPF2_XL_EN
HPCF_XL_[2:0]
Bandwidth
0
-
6.3 kHz
000
ODR/4
001
ODR/10
010
ODR/20
011
ODR/45
100
ODR/100
101
ODR/200
110
ODR/400
111
ODR/800
000
SLOPE (ODR/4)
001
ODR/10
010
ODR/20
011
ODR/45
100
ODR/100
101
ODR/200
110
ODR/400
111
ODR/800
1
--
page 36/59
IIS3DWB
CTRL10_C (19h)
9.18
CTRL10_C (19h)
Control register 10 (r/w)
Table 46. CTRL10_C register
0(1)
0(1)
TIMESTAMP
_EN
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 47. CTRL10_C register description
Enables timestamp counter. Default value: 0
TIMESTAMP_EN
(0: disabled; 1: enabled)
The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and
TIMESTAMP3 (43h).
9.19
ALL_INT_SRC (1Ah)
Source register for all interrupts (r)
Table 48. ALL_INT_SRC register
TIMESTAMP
_ENDCOUNT
0
SLEEP_
CHANGE_IA
0
0
0
WU_IA
0
Table 49. ALL_INT_SRC register description
TIMESTAMP_ENDCOUNT
SLEEP_CHANGE_IA
WU_IA
DS12569 - Rev 6
Alerts timestamp overflow within 6.4 ms
Detects change event in activity/inactivity status. Default value: 0
(0: change status not detected; 1: change status detected)
Wake-up event status. Default value: 0
(0: event not detected, 1: event detected)
page 37/59
IIS3DWB
WAKE_UP_SRC (1Bh)
9.20
WAKE_UP_SRC (1Bh)
Wake-up interrupt source register (r)
Table 50. WAKE_UP_SRC register
0
SLEEP_
CHANGE_IA
0
SLEEP_
STATE_IA
WU_IA
X_WU
Y_WU
Z_WU
Table 51. WAKE_UP_SRC register description
Detects change event in activity/inactivity status. Default value: 0
SLEEP_CHANGE_IA
(0: change status not detected; 1: change status detected)
Sleep event status. Default value: 0
SLEEP_STATE_IA
(0: sleep event not detected; 1: sleep event detected)
Wakeup event detection status. Default value: 0
WU_IA
(0: wakeup event not detected; 1: wakeup event detected.)
Wakeup event detection status on X-axis. Default value: 0
X_WU
(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)
Wakeup event detection status on Y-axis. Default value: 0
Y_WU
(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)
Wakeup event detection status on Z-axis. Default value: 0
Z_WU
9.21
(0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected)
STATUS_REG (1Eh)
Status register (r)
Table 52. STATUS_REG register
0
0
0
0
0
TDA
0
XLDA
Table 53. STATUS_REG register description
Temperature new data available. Default: 0
TDA
(0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
Accelerometer new data available. Default value: 0
XLDA
(0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)
DS12569 - Rev 6
page 38/59
IIS3DWB
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
9.22
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.
Table 54. OUT_TEMP_L register
Temp7
Temp6
Temp5
Temp4
Temp3
Temp2
Temp1
Temp0
Temp10
Temp9
Temp8
Table 55. OUT_TEMP_H register
Temp15
Temp14
Temp13
Temp12
Temp11
Table 56. OUT_TEMP register description
Temp[15:0]
9.23
Temperature sensor output data
The value is expressed as two’s complement sign extended on the MSB.
OUTX_L_A (28h) and OUTX_H_A (29h)
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Table 57. OUTX_L_A register
D7
D6
D5
D4
D3
D2
D1
D0
Table 58. OUTX_H_A register
D15
D14
D13
D12
D11
D10
D9
D8
Table 59. OUTX_H_A register description
D[15:0]
DS12569 - Rev 6
X-axis linear acceleration value
D[15:0] expressed in two’s complement
page 39/59
IIS3DWB
OUTY_L_A (2Ah) and OUTY_H_A (2Bh)
9.24
OUTY_L_A (2Ah) and OUTY_H_A (2Bh)
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Table 60. OUTY_L_A register
D7
D6
D5
D4
D3
D2
D1
D0
Table 61. OUTY_H_A register
D15
D14
D13
D12
D11
D10
D9
D8
Table 62. OUTY_H_A register description
D[15:0]
9.25
Y-axis linear acceleration value
D[15:0] expressed in two’s complement
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
Table 63. OUTZ_L_A register
D7
D6
D5
D4
D3
D2
D1
D0
Table 64. OUTZ_H_A register
D15
D14
D13
D12
D11
D10
D9
D8
Table 65. OUTZ_H_A register description
D[15:0]
DS12569 - Rev 6
Z-axis linear acceleration value
D[15:0] expressed in two’s complement
page 40/59
IIS3DWB
FIFO_STATUS1 (3Ah)
9.26
FIFO_STATUS1 (3Ah)
FIFO status register 1 (r)
Table 66. FIFO_STATUS1 register
DIFF_
FIFO_7
DIFF_
FIFO_6
DIFF_
FIFO_5
DIFF_
FIFO_4
DIFF_
FIFO_3
DIFF_
FIFO_2
DIFF_
FIFO_1
DIFF_
FIFO_0
DIFF_
FIFO_9
DIFF_
FIFO_8
Table 67. FIFO_STATUS1 register description
Number of unread sensor data (TAG + 6 bytes) stored in FIFO
DIFF_FIFO_[7:0]
9.27
In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh).
FIFO_STATUS2 (3Bh)
FIFO status register 2 (r)
Table 68. FIFO_STATUS2 register
FIFO_
WTM_IA
FIFO_
OVR_IA
FIFO_
FULL_IA
COUNTER_
BDR_IA
FIFO_OVR_
LATCHED
0
Table 69. FIFO_STATUS2 register description
FIFO watermark status. Default value: 0
FIFO_WTM_IA
(0: FIFO filling is lower than WTM;
1: FIFO filling is equal to or greater than WTM)
Watermark is set through bits WTM[8:0] in FIFO_CTRL2 (08h) and FIFO_CTRL1 (07h).
FIFO_OVR_IA
FIFO_FULL_IA
COUNTER_BDR_IA
FIFO overrun status. Default value: 0
(0: FIFO is not completely filled; 1: FIFO is completely filled)
Smart FIFO full status. Default value: 0
(0: FIFO is not full; 1: FIFO will be full at the next ODR)
Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in COUNTER_BDR_REG1 (0Bh) and
COUNTER_BDR_REG2 (0Ch). Default value: 0
This bit is reset when these registers are read.
FIFO_OVR_LATCHED
DIFF_FIFO_[9:8]
DS12569 - Rev 6
Latched FIFO overrun status. Default value: 0
This bit is reset when this register is read.
Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00
In conjunction with DIFF_FIFO[7:0] in FIFO_STATUS1 (3Ah)
page 41/59
IIS3DWB
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h)
9.28
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3
(43h)
Timestamp first data output register (r). The value is expressed as a 32-bit word and the bit resolution is 12.5 µs.
Table 70. TIMESTAMP output registers
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D7
D14
D6
D13
D12
D5
D4
D11
D3
D10
D2
D9
D1
D8
D0
Table 71. TIMESTAMP output register description
D[31:0]
Timestamp output registers: 1LSB = 12.5 µs
The formula below can be used to calculate a better estimation of the actual timestamp resolution:
TS_Res = 1 / (80000 + (0.0015 * INTERNAL_FREQ_FINE * 80000))
where INTERNAL_FREQ_FINE is the content of INTERNAL_FREQ_FINE (63h).
9.29
SLOPE_EN (56h)
Slope enable (r/w)
Table 72. SLOPE_EN register
0(1)
0(1)
SLEEP_STATUS
_ON_INT
SLOPE_FDS
0(1)
0(1)
0(1)
LIR
1. This bit must be set to '0' for the correct operation of the device.
Table 73. SLOPE_EN register description
Activity/inactivity interrupt mode configuration. If the INT1_SLEEP_CHANGE or
INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or sleep change on the INT
SLEEP_STATUS_ON_INT pins. Default value: 0
(0: sleep change notification on INT pins; 1: sleep status reported on INT pins)
SLOPE_FDS
LIR
DS12569 - Rev 6
HPF or slope filter selection on wake-up and activity/inactivity functions. Default value: 0
(0: Slope filter applied; 1: HPF applied)
Latched Interrupt. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
page 42/59
IIS3DWB
INTERRUPTS_EN (58h)
9.30
INTERRUPTS_EN (58h)
Enables interrupt functions (r/w)
Table 74. INTERRUPTS_EN register
INTERRUPTS
_ENABLE
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 75. INTERRUPTS_EN register description
Enables wake-up and activity/inactivity interrupt logic. Default value: 0
INTERRUPTS_ENABLE
9.31
(0: interrupt disabled; 1: interrupt enabled)
WAKE_UP_THS (5Bh)
Wake-up configuration (r/w)
Table 76. WAKE_UP_THS register
0(1)
USR_OFF_
ON_WU
WK_THS5
WK_THS4
WK_THS3
WK_THS2
WK_THS1
WK_THS0
1. This bit must be set to '0' for the correct operation of the device.
Table 77. WAKE_UP_THS register description
9.32
USR_OFF_ON_WU
Drives the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the
wakeup function.
WK_THS[5:0]
Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in WAKE_UP_DUR (5Ch). Default
value: 000000
WAKE_UP_DUR (5Ch)
Wakeup and sleep mode functions duration setting register (r/w)
Table 78. WAKE_UP_DUR register
0(1)
WAKE_
DUR1
WAKE_
DUR0
WAKE_
THS_W
SLEEP_
DUR3
SLEEP_
DUR2
SLEEP_
DUR1
SLEEP_
DUR0
1. This bit must be set to '0' for the correct operation of the device.
Table 79. WAKE_UP_DUR register description
WAKE_DUR[1:0]
Wake up duration event. Default: 00
1LSB = 1 ODR_time
Weight of 1 LSB of wakeup threshold. Default: 0
WAKE_THS_W
(0: 1 LSB = FS_XL / (26);
1: 1 LSB = FS_XL / (28) )
SLEEP_DUR[3:0]
DS12569 - Rev 6
Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)
1 LSB = 512 ODR
page 43/59
IIS3DWB
MD1_CFG (5Eh)
9.33
MD1_CFG (5Eh)
Functions routing on INT1 register (r/w)
Table 80. MD1_CFG register
INT1_SLEEP
_CHANGE
0(1)
INT1_WU
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 81. MD1_CFG register description
Routing of activity/inactivity recognition event on INT1. Default: 0
INT1_SLEEP_CHANGE(1)
(0: routing of activity/inactivity event on INT1 disabled;
1: routing of activity/inactivity event on INT1 enabled)
Routing of wakeup event on INT1. Default value: 0
INT1_WU
(0: routing of wakeup event on INT1 disabled;
1: routing of wakeup event on INT1 enabled)
1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in
SLOPE_EN (56h) register.
9.34
MD2_CFG (5Fh)
Functions routing on INT2 register (r/w)
Table 82. MD2_CFG register
INT2_SLEEP
_CHANGE
0(1)
INT2_WU
0(1)
0(1)
0(1)
0(1)
INT2_
TIMESTAMP
1. This bit must be set to '0' for the correct operation of the device.
Routing of activity/inactivity recognition event on INT2. Default: 0
INT2_SLEEP_CHANGE(1)
(0: routing of activity/inactivity event on INT2 disabled;
1: routing of activity/inactivity event on INT2 enabled)
Routing of wakeup event on INT2. Default value: 0
INT2_WU
(0: routing of wakeup event on INT2 disabled;
1: routing of wake-up event on INT2 enabled)
INT2_TIMESTAMP
Enables routing on INT2 pin of the alert for timestamp overflow within 6.4 ms
1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in
SLOPE_EN (56h) register.
DS12569 - Rev 6
page 44/59
IIS3DWB
INTERNAL_FREQ_FINE (63h)
9.35
INTERNAL_FREQ_FINE (63h)
Internal frequency register (r)
Table 83. INTERNAL_FREQ_FINE register
FREQ_
FINE7
FREQ_
FINE6
FREQ_
FINE5
FREQ_
FINE4
FREQ_
FINE3
FREQ_
FINE2
FREQ_
FINE1
FREQ_
FINE0
Table 84. INTERNAL_FREQ_FINE register description
FREQ_FINE[7:0]
Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.15%.
8-bit format, 2's complement.
The formula below can be used to calculate a better estimation of the actual ODR:
ODR_Actual = (26667 + ((0.0015 * INTERNAL_FREQ_FINE) * 26667))
9.36
X_OFS_USR (73h)
Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is
internally subtracted from the acceleration value measured on the X-axis.
Table 85. X_OFS_USR register
X_OFS_
USR_7
X_OFS_
USR_6
X_OFS_
USR_5
X_OFS_
USR_4
X_OFS_
USR_3
X_OFS_
USR_2
X_OFS_
USR_1
X_OFS_
USR_0
Table 86. X_OFS_USR register description
X_OFS_USR_[7:0]
9.37
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127 127].
Y_OFS_USR (74h)
Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is
internally subtracted from the acceleration value measured on the Y-axis.
Table 87. Y_OFS_USR register
Y_OFS_
USR_7
Y_OFS_
USR_6
Y_OFS_
USR_5
Y_OFS_
USR_4
Y_OFS_
USR_3
Y_OFS_
USR_2
Y_OFS_
USR_1
Y_OFS_
USR_0
Table 88. Y_OFS_USR register description
Y_OFS_USR_[7:0]
DS12569 - Rev 6
Accelerometer Y-axis user offset calibration expressed in 2’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127].
page 45/59
IIS3DWB
Z_OFS_USR (75h)
9.38
Z_OFS_USR (75h)
Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is
internally subtracted from the acceleration value measured on the Z-axis.
Table 89. Z_OFS_USR register
Z_OFS_
USR_7
Z_OFS_
USR_6
Z_OFS_
USR_5
Z_OFS_
USR_4
Z_OFS_
USR_3
Z_OFS_
USR_2
Z_OFS_
USR_1
Z_OFS_
USR_0
Table 90. Z_OFS_USR register description
Z_OFS_USR_[7:0]
9.39
Accelerometer Z-axis user offset calibration expressed in 2’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127].
FIFO_DATA_OUT_TAG (78h)
FIFO tag register (r)
Table 91. FIFO_DATA_OUT_TAG register
TAG_
SENSOR_4
TAG_
SENSOR_3
TAG_
SENSOR_2
TAG_
SENSOR_1
TAG_
SENSOR_0
TAG_CNT_1
TAG_CNT_0
TAG_
PARITY
Table 92. FIFO_DATA_OUT_TAG register description
FIFO tag: identifies the sensor in:
TAG_SENSOR_[4:0]
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah), FIFO_DATA_OUT_Y_L (7Bh) and
FIFO_DATA_OUT_Y_H (7Ch), and FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
For details, refer to Table 93.
TAG_CNT_[1:0]
2-bit counter which identifies sensor time slot
TAG_PARITY
Parity check of TAG content
Table 93. FIFO tag
DS12569 - Rev 6
TAG_SENSOR_[4:0]
Sensor name
0x02
Accelerometer
0x03
Temperature
0x04
Timestamp
page 46/59
IIS3DWB
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
9.40
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
FIFO data output X (r)
Table 94. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 95. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description
D[15:0]
9.41
FIFO X-axis output
FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch)
FIFO data output Y (r)
Table 96. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 97. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description
D[15:0]
9.42
FIFO Y-axis output
FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
FIFO data output Z (r)
Table 98. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 99. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description
D[15:0]
DS12569 - Rev 6
FIFO Z-axis output
page 47/59
IIS3DWB
Soldering information
10
Soldering information
The LGA package is compliant with the ECOPACK, RoHS and "Green" standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Land pattern and soldering recommendations are available at www.st.com/mems.
DS12569 - Rev 6
page 48/59
IIS3DWB
Package information
11
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
11.1
LGA-14L package information
Figure 22. LGA-14L 2.5 x 3.0 x 0.83 mm³ (typ) package outline and mechanical data
Pin1 indicator
Pin1 indicator
H
0.5
4x
1
TOP VIEW
(0.1)
14x
0.5
L
1.5
W
14x
0.25±0.05
0.475±0.05
BOTTOM VIEW
Dimensions are in millimeter unless otherwise specified
General tolerance is +/-0.1mm unless otherwise specified
OUTER DIMENSIONS
ITEM
Length [L]
W idth [W ]
Height [H]
DIMENSION [mm]
2.50
3.00
0.86
TOLERANCE [mm]
±0.1
±0.1
MA X
DM00249496_1
DS12569 - Rev 6
page 49/59
IIS3DWB
LGA-14 packing information
11.2
LGA-14 packing information
Figure 23. Carrier tape information for LGA-14 package
Figure 24. LGA-14 package orientation in carrier tape
DS12569 - Rev 6
page 50/59
IIS3DWB
LGA-14 packing information
Figure 25. Reel information for carrier tape of LGA-14 package
T
40mm min.
Access hole at
slot location
B
C
N
D
A
Full radius
G measured at hub
Tape slot
in core for
tape start
2.5mm min. width
Table 100. Reel dimensions for carrier tape of LGA-14 package
Reel dimensions (mm)
DS12569 - Rev 6
A (max)
330
B (min)
1.5
C
13 ±0.25
D (min)
20.2
N (min)
60
G
12.4 +2/-0
T (max)
18.4
page 51/59
IIS3DWB
Revision history
Table 101. Document revision history
Date
Version
29-Jan-2020
3
Changes
First public release
Updated CTRL8_XL (17h)
Updated SLOPE_EN (56h)
20-Feb-2020
4
Added INTERRUPTS_EN (58h)
Updated Table 92. FIFO tag
Minor textual changes
Updated Section 3.3.7 FIFO reading procedure
21-Jul-2020
5
Updated description of dataready_pulsed bit in COUNTER_BDR_REG1 (0Bh)
Updated TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and
TIMESTAMP3 (43h)
13-Aug-2020
DS12569 - Rev 6
6
Added Section 3 Digital interface
page 52/59
IIS3DWB
Contents
Contents
1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1
2
Default pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.1
3
4
5
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.2
Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Digital interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3
SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.1
Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.2
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.3
Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.4
Continuous-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.5
Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.6
Bypass-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.7
FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DS12569 - Rev 6
page 53/59
IIS3DWB
Contents
6
7
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.1
Frequency response measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
Sensitivity change versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3
ODR change versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
7.1
IIS3DWB electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2
Measuring the actual ODR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Register mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
9
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9.1
PIN_CTRL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2
FIFO_CTRL1 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3
FIFO_CTRL2 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.4
FIFO_CTRL3 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.5
FIFO_CTRL4 (0Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.6
COUNTER_BDR_REG1 (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.7
COUNTER_BDR_REG2 (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.8
INT1_CTRL (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.9
INT2_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.10
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.11
CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.12
CTRL3_C (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.13
CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.14
CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.15
CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.16
CTRL7_C (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.17
CTRL8_XL (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.18
CTRL10_C (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.19
ALL_INT_SRC (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.20
WAKE_UP_SRC (1Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.21
STATUS_REG (1Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DS12569 - Rev 6
page 54/59
IIS3DWB
Contents
9.22
OUT_TEMP_L (20h), OUT_TEMP_H (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.23
OUTX_L_A (28h) and OUTX_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.24
OUTY_L_A (2Ah) and OUTY_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.25
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.26
FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.27
FIFO_STATUS2 (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.28
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 42
9.29
SLOPE_EN (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.30
INTERRUPTS_EN (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.31
WAKE_UP_THS (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.32
WAKE_UP_DUR (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.33
MD1_CFG (5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.34
MD2_CFG (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.35
INTERNAL_FREQ_FINE (63h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.36
X_OFS_USR (73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.37
Y_OFS_USR (74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.38
Z_OFS_USR (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.39
FIFO_DATA_OUT_TAG (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.40
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) . . . . . . . . . . . . . . . . . . . . . 47
9.41
FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) . . . . . . . . . . . . . . . . . . . . . 47
9.42
FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) . . . . . . . . . . . . . . . . . . . . . 47
10
Soldering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
11
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
11.1
LGA-14L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.2
LGA-14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
DS12569 - Rev 6
page 55/59
IIS3DWB
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Pin desription . . . . . . . . . . . . . . . . . . . . . . . . . .
Default pin status . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical characteristics . . . . . . . . . . . . . . . . .
Electrical characteristics . . . . . . . . . . . . . . . . . . .
SPI slave timing values. . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . .
Serial interface pin description . . . . . . . . . . . . . . .
Register address map . . . . . . . . . . . . . . . . . . . .
PIN_CTRL register. . . . . . . . . . . . . . . . . . . . . . .
PIN_CTRL register description . . . . . . . . . . . . . .
FIFO_CTRL1 register . . . . . . . . . . . . . . . . . . . . .
FIFO_CTRL1 register description. . . . . . . . . . . . .
FIFO_CTRL2 register . . . . . . . . . . . . . . . . . . . . .
FIFO_CTRL2 register description. . . . . . . . . . . . .
FIFO_CTRL3 register . . . . . . . . . . . . . . . . . . . . .
FIFO_CTRL3 register description. . . . . . . . . . . . .
FIFO_CTRL4 register . . . . . . . . . . . . . . . . . . . . .
FIFO_CTRL4 register description. . . . . . . . . . . . .
COUNTER_BDR_REG1 register . . . . . . . . . . . . .
COUNTER_BDR_REG1 register description . . . . .
COUNTER_BDR_REG2 register . . . . . . . . . . . . .
COUNTER_BDR_REG2 register description . . . . .
INT1_CTRL register . . . . . . . . . . . . . . . . . . . . . .
INT1_CTRL register description . . . . . . . . . . . . . .
INT2_CTRL register . . . . . . . . . . . . . . . . . . . . . .
INT2_CTRL register description . . . . . . . . . . . . . .
WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . .
CTRL1_XL register . . . . . . . . . . . . . . . . . . . . . .
CTRL1_XL register description . . . . . . . . . . . . . .
Accelerometer full-scale selection . . . . . . . . . . . .
CTRL3_C register . . . . . . . . . . . . . . . . . . . . . . .
CTRL3_C register description . . . . . . . . . . . . . . .
CTRL4_C register . . . . . . . . . . . . . . . . . . . . . . .
CTRL4_C register description . . . . . . . . . . . . . . .
CTRL5_C register . . . . . . . . . . . . . . . . . . . . . . .
CTRL5_C register description . . . . . . . . . . . . . . .
Linear acceleration sensor self-test mode selection
CTRL6_C register . . . . . . . . . . . . . . . . . . . . . . .
CTRL6_C register description . . . . . . . . . . . . . . .
Accelerometer active axis . . . . . . . . . . . . . . . . . .
CTRL7_C register . . . . . . . . . . . . . . . . . . . . . . .
CTRL7_C register description . . . . . . . . . . . . . . .
CTRL8_XL register . . . . . . . . . . . . . . . . . . . . . .
CTRL8_XL register description . . . . . . . . . . . . . .
Accelerometer bandwidth configurations . . . . . . . .
CTRL10_C register . . . . . . . . . . . . . . . . . . . . . .
CTRL10_C register description . . . . . . . . . . . . . .
ALL_INT_SRC register . . . . . . . . . . . . . . . . . . . .
ALL_INT_SRC register description. . . . . . . . . . . .
WAKE_UP_SRC register . . . . . . . . . . . . . . . . . .
WAKE_UP_SRC register description . . . . . . . . . .
STATUS_REG register . . . . . . . . . . . . . . . . . . . .
DS12569 - Rev 6
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. 3
. 4
. 5
. 6
. 8
. 9
11
26
28
28
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31
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38
page 56/59
IIS3DWB
List of tables
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
STATUS_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUT_TEMP register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_L_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_H_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_L_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_H_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_L_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_H_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_STATUS1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_STATUS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_STATUS2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_STATUS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMESTAMP output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMESTAMP output register description . . . . . . . . . . . . . . . . . . . . . . .
SLOPE_EN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SLOPE_EN register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERRUPTS_EN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERRUPTS_EN register description . . . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_THS register description . . . . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . .
MD1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MD1_CFG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MD2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERNAL_FREQ_FINE register. . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERNAL_FREQ_FINE register description. . . . . . . . . . . . . . . . . . . .
X_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
X_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Y_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Y_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_TAG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_TAG register description . . . . . . . . . . . . . . . . . . . .
FIFO tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers . . . . . . . .
FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description
FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers . . . . . . . .
FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description
FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers . . . . . . . .
FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description.
Reel dimensions for carrier tape of LGA-14 package . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS12569 - Rev 6
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page 57/59
IIS3DWB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
DS12569 - Rev 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read and write protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI read protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple byte SPI read protocol (2-byte example) (in mode 3) . . . . . . . . . .
SPI write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple byte SPI write protocol (2-byte example) (in mode 3) . . . . . . . . . .
SPI read protocol in 3-wire mode (in mode 3) . . . . . . . . . . . . . . . . . . . . .
Accelerometer architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accelerometer composite filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filtering chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency response at the output of LPF1 filter . . . . . . . . . . . . . . . . . . .
Frequency response with LPF2 enabled . . . . . . . . . . . . . . . . . . . . . . . .
Frequency response with HPF enabled . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency response - X-axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency response - Y-axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency response - Z-axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sensitivity change versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . .
ODR change versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IIS3DWB electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accurately measuring ODR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LGA-14L 2.5 x 3.0 x 0.83 mm³ (typ) package outline and mechanical data .
Carrier tape information for LGA-14 package . . . . . . . . . . . . . . . . . . . . .
LGA-14 package orientation in carrier tape. . . . . . . . . . . . . . . . . . . . . . .
Reel information for carrier tape of LGA-14 package . . . . . . . . . . . . . . . .
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page 58/59
IIS3DWB
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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