IPS160H

IPS160H, IPS161H Datasheet 60 V, 60 mΩ single high-side switches Features • • • • • • • 8 V to 60 V operating voltage range Minimum output current limitation: 0.7 A (IPS161H) or 2.5 A (IPS160H) Fast demagnetization of inductive load Non-dissipative short-circuit protection (cut-off) Programmable cut-off delay time using external capacitor Ground disconnection protection VCC disconnection protection • • • Thermal shutdown protection Undervoltage lock-out Diagnostic signalization for: open load in off-state, cut-off and junction thermal shutdown Designed to meet IEC 61131-2 PowerSSO12 package • • Applications • • • • • Product status IPS160H Description IPS161H The IPS160H (IOUT < 2.5 A) and IPS161H (IOUT < 0.7 A) are monolithic devices which can drive capacitive, resistive or inductive loads with one side connected to ground. Product label Product summary Order code Package Packing IPS160H IPS160HTR IPS161H IPS161HTR PowerSSO12 Tube Programmable logic control Industrial PC peripheral input/output Numerical control machines Domotics Generic power supply switch The 60 V operating range and Ron = 60 mΩ, combined with the extended diagnostic (Open Load, Over Load, Overtemperature) make the IC suitable for applications implementing the proper architectures to address higher SIL levels. The built-in overload and thermal shutdown protections guarantee the ICs, the application and the load against electrical and thermal overstress. Furthermore, in order to minimize the power dissipation when the output is shorted, a low-dissipative short-circuit protection (cut-off) is implemented to limit the output average current value and consequent device overheating.Cut-off delay time can be set by soldering an external capacitor or disabled by a resistor on pin 4 (CoD). The DIAG common diagnostic open drain pin reports the open load in off-state, cutoff (overload) and thermal shutdown. Tape and reel DS10907 - Rev 11 - December 2022 For further information contact your local STMicroelectronics sales office. www.st.com IPS160H, IPS161H Block diagram 1 Block diagram Figure 1. Block diagram IN DIAG Logic interface Undervoltage detection Vcc Vcc clamp Output clamp Current limitation cut -off Open load in off-state OUT CoD Junction Overtemperature GND DS10907 - Rev 11 GIPG1702151307LM page 2/24 IPS160H, IPS161H Pin description 2 Pin description Figure 2. Pin connection (top view) VCC 1 12 VCC IN 2 11 OUT DIAG 3 10 OUT CoD 4 9 OUT NC 5 8 OUT NC 6 7 GND TAB=Vcc GIPG1702151321LM Table 1. Pin configuration Number Name Type 1, 12, TAB VCC Device supply voltage Supply 2 IN Channel input Input 3 DIAG Common diagnostic pin both for thermal shutdown, cut-off and open load Output open drain 4 CoD Cut-off delay pin, cannot be left floating. Connected to GND by 1 kΩ resistor to disable the cut-off function. Connect to a CCoD capacitor to set the cut-off delay see Table 8. Protection and diagnostic Input 5, 6 NC Not connected 7 GND Device ground Ground Channel power stage output Output 8, 9, 10, 11 OUT 2.1 Function IN This pin drives the output stage to pin OUT. IN pin has internal weak pull-down resistors, see Table 7. Logic inputs. 2.2 OUT Output power transistor is in high-side configuration, with active clamp for fast demagnetization. 2.3 DIAG This pin is used for diagnostic purpose and it is internally wired to an open drain transistor. The open drain transistor is turned on in case of junction thermal shutdown, cut-off, or open load in off-state. DS10907 - Rev 11 page 3/24 IPS160H, IPS161H CoD 2.4 CoD This pin cannot be left floating and can be used to program the cut-off delay time tcoff, see Table 8. Protection and diagnostic through an external capacitor (CCoD). The cut-off function can be completely disabled connecting the CoD pin to GND through 1 kΩ resistor: in this condition the output channel remains in limitation condition, supplying the current to the load until the input is forced LOW or the thermal shutdown threshold is triggered. 2.5 GND IC ground. 2.6 VCC IC supply voltage. DS10907 - Rev 11 page 4/24 IPS160H, IPS161H Reverse polarity 3 Reverse polarity Reverse polarity The IC can be protected against reverse polarity using two different solutions: 1. Placing a resistor RGND between IC GND pin and load connection point to GND (RGND > VCC/Icc, see Table 1. Absolute maximum rating). Note that power dissipated by RGND during reverse polarity condition is Vcc^2/RGND. 2. Placing a diode in parallel to RGND The diode must be selected such that its VRRM > |VCC| and power dissipation capability is higher than VF*IS (see Table 1). In normal operation (no reverse polarity), there is a voltage drop (ΔV) between GND of the device and GND of the module. Using option 1, ΔV = RGND * ICC. Using option 2, ΔV = VF@(IS). Figure 3. Reverse polarity protection schematic DS10907 - Rev 11 page 5/24 IPS160H, IPS161H Absolute maximum ratings 4 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Parameter VCC Supply voltage VOUT Output channel voltage Value Unit -0.3 to 65 V Vcc-Vclamp to Vcc+0.3 V -10 to +10 mA IIN Input current VIN IN voltage VCC V VCOD Output cut-off voltage pin 5.5 V ICOD Input current on cut-off pin -1 to +10 mA VDIAG Fault voltage VCC V IDIAG Fault current -5 to +10 mA ICC (1) Maximum DC reverse current flowing through the IC from GND to VCC -250 mA IOUT Output stage current -IOUT (1) EAS (1) Internally limited A Maximum DC reverse current flowing through the IC from OUT to VCC 5 Single pulse avalanche energy (TAMB = 125 °C, VCC = 24 V, Iload = 0.5 A) 3000 mJ Single pulse avalanche energy (TAMB = 125 °C, VCC = 24 V, Iload = 1.0 A) 1000 mJ Internally limited W PTOT Power dissipation at TC = 25 °C (2) TSTG Storage temperature range -55 to 150 Junction temperature -40 to 150 TJ °C 1. Verified on STEVAL-IFP028V1 and STEVAL-IFP034V1 application board 2. (TJSD(MAX)-TC)/ Rth(JA) Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referenced to GND. Table 3. Thermal data Value Symbol Note: Parameter 1s 2s2p 2s2p (with 4 thermal vias) Rth(JC) Thermal resistance junction-case 0.4 0.9 0.5 Rth(JA) Thermal resistance junction-ambient 117 57 29 Unit °C/W Rth(JC) is intended between the die and the bottom case surface measured by cold plate as per JESD51. Rth(JA) according JESD51-3 (1s) JESD51-5 (2s2p) and JESD51-7 (2s2p and thermal vias). DS10907 - Rev 11 page 6/24 IPS160H, IPS161H Electrical characteristics 5 Electrical characteristics (8 V < VCC < 60 V; -40 °C < TJ < 125 °C, unless otherwise specified) Table 4. Supply Symbol Parameter Test conditions Min. Typ. Max. Unit VUVON 60 V VCC Supply voltage VUVON Undervoltage on threshold 6.9 8 V VUVOFF Undervoltage off threshold 6.5 7.8 V VUVH Undervoltage hysteresis 0.15 Supply current in off-state IS Supply current in on-state ILGND GND disconnection output current 0.5 V VCC = 24 V 300 500 VCC = 60 V 350 600 VCC = 24 V 1 1.4 VCC = 60 V 1.4 2.1 VGND = VIN = VCC, VOUT = 0 V; TJ = 25oC 0.5 VGND = VIN = VCC, VOUT = 0 V; TJ = 125oC 0.55 μA mA mA Table 5. Output stage Symbol Parameter Test conditions Min. Typ. Max. Unit VCC = 24 V RDS(on) On-state resistance 60 IOUT =0.5 A (IPS161H), 1 A (IPS160H) @ TJ = 25 °C mΩ VCC = 24 V 120 IOUT =0.5 A (IPS161H), 1 A (IPS160H) @ TJ = 125 °C DS10907 - Rev 11 VOUT(OFF) Off-state output voltage IOUT(OFF) Off-state output current IOUT(OFF-min) Off-state output current 80 VIN = 0 V and IOUT = 0 A 2 VCC = 24 V, VIN = 0 V, VOUT = 0 V 3 VCC = 60 V, VIN = 0 V, VOUT = 0 V 10 VIN = 0 V, VOUT = 4 V -35 V μA 0 page 7/24 IPS160H, IPS161H Electrical characteristics Table 6. Switching (VCC = 24 V; -40 °C < TJ < 125 °C, RLOAD = 48 Ω) Symbol Parameter Test conditions tr Rise time tf Fall time tPD(H-L) Propagation delay time off tPD(L-H) Propagation delay time on tD(VCC-ON) Power-on delay time from VCC rising edge Min. Typ. Max. IOUT = 0.5 A, Figure 4. Timing in normal operation IOUT = 0.5 A, (see Figure 5. Propagation delay at startup) 10 20 10 20 20 35 20 35 Unit μs 600 1200 Figure 4. Timing in normal operation Figure 5. Propagation delay at start-up VIN t VCC VUVON t td(Vcc-on) VOUT 10% t DS10907 - Rev 11 page 8/24 IPS160H, IPS161H Electrical characteristics Table 7. Logic inputs Symbol Parameter VIL Input low level voltage VIH Input high level voltage VI(HYST) Input hysteresis voltage IIN Input current Test conditions Min. Typ. Max. Unit 0.8 V 2.2 0.4 VCC = VIN = 36 V 200 VCC = VIN = 60 V 550 μA Table 8. Protection and diagnostic Symbol Parameter Test conditions Vclamp VCC active clamp ICC = 10 mA Vdemag Demagnetization voltage IOUT = 0.5 A; load =1 mH VOLoff Open load (off-state) or short to VCC detection threshold tBKT Open load blanking time VDIAG Voltage drop on DIAG IDIAG DIAG pin leakage current IPK IPS161H Output current limitation activation threshold tcoff Typ. Max. 65.5 68.5 71.5 2 200 μs 1 V VCC ≤ 36 V 110 36 V ˂ VCC ≤ 60 V 180 2.1 3.0 4.6 IPS161H Output current limitation 0.7 1.7 IPS160H Output current limitation 2.5 4.2 Cut-off current delay time Programmable by the external capacitor on CoD pin. Cut-off is disabled when CoD pin is connected to GND through 1 kΩ resistor. V 4 IDIAG = 4 mA VCC ≤ 24 V, RLOAD ≤ 10 mΩ Unit VCC-71.5 VCC-68.5 VCC-65.5 1.3 IPS160H Output current limitation activation threshold ILIM Min. 50xCCOD[nf] ± 35%(1) μA A μs TJ˂ TJSD tres Output stage restart delay time TJSD Junction temperature shutdown TJHYST Junction temperature thermal hysteresis TJ˂ TJSD 32xtcoff [μs]± 40% 150 170 15 190 °C 1. The formula is guaranteed in the range 10 nF ≤ CCOD ≤ 100 nF. DS10907 - Rev 11 page 9/24 IPS160H, IPS161H Output logic 6 Output logic Table 9. Output stage truth table Operation Normal Cut-off Overtemperature Open load UVLO DS10907 - Rev 11 IN OUT DIAG L L H H H H L L L H L L L L L H L L L H (external pull-up resistor is used) L (external pull-up resistor is used) H H X L X X L X H page 10/24 IPS160H, IPS161H Protection and diagnostic 7 Protection and diagnostic The IC integrates several protections to ease the design of a robust application. 7.1 Undervoltage lock-out The device turns off if the supply voltage falls below the turn-off threshold (VUV(off)). Normal operation restarts after VCC exceeds the turn-on threshold (VUV(on)). Turn-on and turn-off thresholds are defined in Table 4. Supply. 7.2 Overtemperature The output stage turns off when its internal junction temperature (TJ) exceeds the shutdown threshold TJSD. Normal operation restarts when TJ comes back below the reset threshold (TJSD - TJHYST), see Table 8. Protection and diagnostic. The internal fault signal is set when the channel is off due to thermal protection and it is reset when the junction triggers the reset threshold. This same behavior is reported on DIAG pin. 7.3 Cut-off The IC can limit the output current at the power stage by its embedded output current limitation circuit. This circuit continuously monitor the output current and, when load is increasing, at the triggering of its activation threshold (3.8A TYP) it starts limiting to ILIM limitation level (See Protection and diagnostic): while current limitation is active the IC enters an high dissipation status. The IC implements the cut-off feature which limits the duration of the current limitation condition. The duration of the current limitation condition (Tcoff) can be set by a capacitor (CCoD) placed between CoD and GND pins. The design rule for CCoD is: tcoff[us] +/- 35% = 50 x Ccod[nF] The drift of +/-35% is guaranteed in the range of 10 nF < Ccod < 100 nF; lower capacitance than 10 nF can be used. If ILIM threshold is triggered, the output stage remains in the current limitation condition (IOUT = ILIM) no longer than tcoff. If tcoff elapses, the output stage turns off and restarts after the tres restart time. Thermal shutdown protection has higher priority than cut-off: • IC is forced off if TJSD is triggered before tcoff elapses • if TJSD is triggered, IC is maintained off even after the tres has elapsed and until the TJ decreases below TJSD-TJHYST Figure 6. Current limitation and cut-off I OUT t COFF t res ILIM TJ 36 V) the cut-off function needs activating in order to avoid IC permanent damages. The following table reports the suggested cut-off delay for the different operating voltage. Table 10. Minimum cut-off delay for TAMB less than -20 °C DS10907 - Rev 11 VCC [V] Cut-off delay [μs] Cut-off capacitance [nF] 36-48 100 2.2 48-60 50 1 page 12/24 IPS160H, IPS161H Open load in off-state 7.4 Open load in off-state The IC provides the open load detection feature which detects if the load is disconnected from the OUT pin. This feature can be activated by a resistor (RPU) between OUT and VCC pins. Figure 7. Open load off-state Application board VCC SUPPLY RAIL IC VCC EXPOSED PAD Open load detection signal R PU + - OUT VOLOFF RI R LED R LOAD PGND GROUND PLANE In case of wire break and during the OFF state (IN = low), the output voltage VOUT rises according to the the partitioning between the external pull-up resistor and the internal impedence of the IC (130 kΩ < RI < 360 kΩ). The effect of the LED (if any) on the output pin has to be considered as well. In case of wire break and during the ON state (IN = high), the output voltage VOUT is pulled up to VCC by the low resistive integrated switch. If the load is not connected, in order to guarantee the correct open load signalization it must result: VOUT > VOLoff(max.) Referring to the circuit in figure 6: therefore: VOUT = VCC − RPU × IPU = VCC − RPU × IRI + ILED + IRL VCC min − VOLoff max RPU < V VOLoff max − VLED OLoff max + RLED RI min (1) (2) If the load is connected, in order to avoid any false signalization of the open load, it must result as follows: VOUT < VOLoff(min) By taking into account the circuit in figure 6: so: VOUT = VCC − RPU × IPU = VCC − RPU × VOUT VOUT − VLED VOUT + R RI + RLED L VCC max − VOLoff min RPU > V VOLoff min − VLED VOLoff min OLoff min + + RLED RL RI max (3) (4) The fault condition is reported on the DIAG pin and the fault reset occurs when load is reconnected. If the channel is switched on by IN pin, the fault condition is no longer detected. When inductive load is driven, some ringing of the output voltage may be observed at the end of the demagnetization. In fact, the load is completely demagnetized when ILOAD = 0 A and the OUT pin remains floating until next turn-on. In order to avoid a fake signalization of the open load event driving inductive loads, the open load signal is masked for tBKT. So, the open load is reported on the DIAG pin with a delay of tBKT and if the open load event is triggered for more than tBKT. DS10907 - Rev 11 page 13/24 IPS160H, IPS161H VCC disconnection protection 7.5 VCC disconnection protection The IC is protected despite the VCC disconnection event. This event is intended as the disconnection of the VCC wire from the application board, see figure below. When this condition happens, the IC continues working normally until the voltage on the VCC pin is ≥ VUVOFF. Once the VUVOFF is triggered, the output channel is turned off independently on the input status. In case of inductive load, if the VCC is disconnected while the output channel is still active, the IC allows the discharge of the energy still stored in the inductor through the integrated power switch. Figure 8. VCC disconnection APPLICATION BOARD VCC >VUVOFF VCC EXPOSED PAD CVCC SUPPLY RAIL ON DRIVING CIRCUITRY OUT IC GND GROUND PLANE 7.6 GND disconnection protection GND disconnection is intended as the disconnection event of the application ground, see figure below. When this event happens, the IC continues working normally until the voltage between VCC and GND pins of the IC results ≥ VUVOFF. The voltage on GND pin of the IC rises up to the supply rail voltage level. In case of GND disconnection event, a current (ILGND) flows through OUT pin. Table 7. Logic inputs reports IOUT = ILGND for the worst case of GND disconnection event in case of output shorted to ground. Figure 9. GND disconnection APPLICATION BOARD SUPPLY RAIL VCC VCC EXPOSED PAD CVCC DRIVING CIRCUITRY ON OUT IC LOAD GROUND PLANE DS10907 - Rev 11 GND page 14/24 IPS160H, IPS161H Active VDS clamp 8 Active VDS clamp Active clamp is also known as fast demagnetization of inductive loads or fast current decay. When a high-side driver turns off an inductance, an undervoltage is detected on output. The OUT pin is pulled down to Vdemag. The conduction state is modulated by an internal circuitry in order to keep the OUT pin voltage at about Vdemag until the load energy has been dissipated. The energy is dissipated both in IC internal switch and in load resistance. Figure 10. Active clamp equivalent principle schematic APPLICATION BOARD SUPPLY RAIL IC VCC EXPOSED PAD Clamp circuitry OUT L LOAD GROUND PLANE GND Figure 11. Fast demag waveforms IOUT tON tDEMAG ~ ILOAD t VOUT ~ VCC t VCC-VDEMAG VIN ~ t The demagnetization of inductive load causes a huge electrical and thermal stress to the IC. The curve plotted below shows the maximum demagnetization energy that the IC can support in a single demagnetization pulse with VCC = 24 V and TAMB = 125 °C. If higher demagnetization energy is required then an external free-wheeling Schottky diode has to be connected between OUT (cathode) and GND (anode) pins. Note that in this case the fast demagnetization is inhibited. DS10907 - Rev 11 page 15/24 IPS160H, IPS161H Active VDS clamp Figure 12. Typical demagnetization energy (single pulse) at VCC = 24 V and TAMB = 125 °C 4000 3500 EDEMAG [mJ] 3000 2500 2000 1500 1000 500 0 500 700 900 1100 1300 ILOAD DS10907 - Rev 11 1500 1700 1900 2100 2300 2500 [mA] page 16/24 IPS160H, IPS161H Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 PowerSSO12 package information Figure 13. PowerSSO12 package outline 7392413 rev. D Table 11. PowerSSO12 package mechanical data Dim. mm Min. Max. A 1.250 1.700 A1 0.000 0.100 A2 1.100 1.600 B 0.230 0.410 C 0.190 0.250 D 4.800 5.000 E 3.800 4.000 e 0.800 H 5.800 6.200 h 0.250 0.55 L 0.400 1.270 k 0d 8d X 1.900 2.500 Y 3.600 4.200 ddd DS10907 - Rev 11 Typ. 0.100 page 17/24 IPS160H, IPS161H PowerSSO12 package information Note: Dimension D doesn't include mold flash protrusions or gate burrs. Mold flash protrusions or gate burrs don't exceed 0.15 mm in total both side. Figure 14. PowerSSO12 recommended footprint Figure 15. PowerSSO12 tape packing information [mm] DS10907 - Rev 11 page 18/24 IPS160H, IPS161H PowerSSO12 package information Figure 16. PowerSS012 reel packing information [mm] DS10907 - Rev 11 page 19/24 IPS160H, IPS161H Revision history Table 12. Document revision history Date Revision 19-Mar-2015 1 Changes Initial release. Minor text changes throughout the document. 04-Nov-2015 Added figure 7 titled "VCC disconnection", figure 10 titled: "Fast demag waveforms" and figure 11 titled "Typical demagnetization energy (single pulse) at VCC = 24 V and TAMB = 125 °C. Updated tables titled: "Supply", "Switching (VCC = 24 V; 125 °C > TJ > -40 °C, RLOAD = 48 Ω)" and "Protection diagnostic". 11-May-2016 3 20-May-2016 4 Document status promoted from preliminary to production data. 08-Mar-2018 5 Updated EAS value in Table 2. Absolute maximum ratings 14-Dec-2018 6 Added reel packaging information in Section 9.1 PowerSSO12 package information 02-Dec-2019 7 Updated value in Table 4. Supply. Text change in Section 2.4 CoD. Change to Figure 16 title. 03-Mar-2021 8 Merged IPS160H and IPS161H datasheets. Updated Section Description and Section Applications target. 29-Mar-2021 9 Updated ILGND max value in Table 4 30-Jul-2021 10 Reviewed the feature list order in front page. Updated thermal data in Table 3 according to Jedec conditions 11 Updated Table Table 6. Switching (VCC = 24 V; -40 °C < TJ < 125 °C, RLOAD = 48 Ω): filled column Max, added tD(VCC-ON) parameter. Added figure Figure 5. Propagation delay at start-up. Added parameter IPK (activation threshold of current activation feature) in table Table 8. Protection and diagnostic. Reduced minimum and maximum values of ILIM for IPS160H in table Table 8. Protection and diagnostic. 06-Dec-2022 DS10907 - Rev 11 2 Changed figures titled: "tPD(L-H) and tPD(H-L)" and "Current limitation and cutoff". page 20/24 IPS160H, IPS161H Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2.1 IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 DIAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 CoD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.6 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Reverse polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Output logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 7 Protection and diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7.1 Undervoltage lock-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.2 Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.3 Cut-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.4 Open load in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.5 VCC disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 GND disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 Active clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 9.1 PowerSSO12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 DS10907 - Rev 11 page 21/24 IPS160H, IPS161H List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching (VCC = 24 V; -40 °C < TJ < 125 °C, RLOAD = 48 Ω). Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . Output stage truth table . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum cut-off delay for TAMB less than -20 °C . . . . . . . . . PowerSSO12 package mechanical data . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . DS10907 - Rev 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 6 . 6 . 7 . 7 . 8 . 9 . 9 10 12 17 20 page 22/24 IPS160H, IPS161H List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse polarity protection schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing in normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Propagation delay at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current limitation and cut-off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open load off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active clamp equivalent principle schematic . . . . . . . . . . . . . . . . . . . . . . . . . . Fast demag waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical demagnetization energy (single pulse) at VCC = 24 V and TAMB = 125 °C PowerSSO12 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO12 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO12 tape packing information [mm] . . . . . . . . . . . . . . . . . . . . . . . . . PowerSS012 reel packing information [mm] . . . . . . . . . . . . . . . . . . . . . . . . . . DS10907 - Rev 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 5 . 8 . 8 11 13 14 14 15 15 16 17 18 18 19 page 23/24 IPS160H, IPS161H IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS10907 - Rev 11 page 24/24