L3G4200D

L3G4200D MEMS motion sensor: ultra-stable three-axis digital output gyroscope Preliminary data Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Three selectable full scales (250/500/2000 dps) I2C/SPI digital output interface 16 bit-rate value data output 8-bit temperature data output Two digital output lines (interrupt and data ready) Integrated low- and high-pass filters with userselectable bandwidth Ultra-stable over temperature and time Wide supply voltage: 2.4 V to 3.6 V Low voltage-compatible IOs (1.8 V) Embedded power-down and sleep mode Embedded temperature sensor Embedded FIFO High shock survivability Extended operating temperature range (-40 °C to +85 °C) ECOPACK® RoHS and “Green” compliant LGA-16 (4x4x1.1 mm) Description The L3G4200D is a low-power three-axis angular rate sensor able to provide unprecedented stablility of zero rate level and sensitivity over temperature and time. It includes a sensing element and an IC interface capable of providing the measured angular rate to the external world through a digital interface (I2C/SPI). The sensing element is manufactured using a dedicated micro-machining process developed by STMicroelectronics to produce inertial sensors and actuators on silicon wafers. The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The L3G4200D has a full scale of ±250/±500/ ±2000 dps and is capable of measuring rates with a user-selectable bandwidth. The L3G4200D is available in a plastic land grid array (LGA) package and can operate within a temperature range of -40 °C to +85 °C. Applications ■ ■ ■ ■ Gaming and virtual reality input devices Motion control with MMI (man-machine interface) GPS navigation systems Appliances and robotics Table 1. Device summary Temperature range (°C) -40 to +85 -40 to +85 Package LGA-16 (4x4x1.1 mm) LGA-16 (4x4x1.1 mm) Packing Tray Tape and reel Order code L3G4200D L3G4200DTR December 2010 Doc ID 17116 Rev 3 1/42 www.st.com 42 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L3G4200D Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Mechanical and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2.2 2.3 2.4 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.1 2.4.2 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 2.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.1 2.6.2 2.6.3 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Main digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 3.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 5 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 5.2 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/42 Doc ID 17116 Rev 3 L3G4200D 5.2.2 5.2.3 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 7 Output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 REFERENCE/DATACAPTURE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OUT_TEMP (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_THS_XH (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_XL (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_YH (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_YL (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_THS_ZH (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_THS_ZL (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_DURATION (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 17116 Rev 3 3/42 List of tables L3G4200D List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mechanical characteristics @ Vdd = 3.0 V, T = 25 °C, unless otherwise noted . . . . . . . . . . . . 10 Electrical characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted . . . . . . . . . . . . . . . . 11 Temp. sensor characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted . . . . . . . . . . . 11 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLL low-pass filter component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 23 Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 23 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 High pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 High pass filter cut off frecuency configuration [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Self test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Out_Sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 INT_SEL configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OUT_TEMP register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4/42 Doc ID 17116 Rev 3 L3G4200D Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. List of tables INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_XH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_XH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_XL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_YH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_YH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_THS_YL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_THS_YL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_THS_ZH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_THS_ZH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_THS_ZL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_THS_ZL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 17116 Rev 3 5/42 List of figures L3G4200D List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 L3G4200D external low-pass filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 L3G4200D electrical connections and external component values . . . . . . . . . . . . . . . . . . 20 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 INT1_Sel and Out_Sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6/42 Doc ID 17116 Rev 3 L3G4200D Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram +Ω x,y,z X+ Y+ Z+ M U X CHARGE AMP MIXER LOW-PASS FILTER A D C 1 ZYX- D I G I T A L F I L T E R I N G I2C SPI CS SCL/SPC SDA/SDO/SDI SDO DRIVING MASS Feedback loop T E M P E R A T U R E S E N S O R A D C 2 REFERENCE TRIMMING CIRCUITS FIFO CLOCK & PHASE GENERATOR CONTROL LOGIC & INTERRUPT GEN. INT1 DRDY/INT2 AM07225v1 The vibration of the structure is maintained by drive circuitry in a feedback loop. The sensing signal is filtered and appears as a digital signal at the output. 1.1 Pin description Figure 2. Pin connection PLLFILT +Ω 1 Z GND RES Vdd X +Ω Y 13 16 1 RES RES RES 12 Vdd_IO SCL/SPC SDA/SDI/SDO BOTTOM VIEW 9 8 5 4 +Ω (TOP VIEW) DIRECTIONS OF THE DETECTABLE ANGULAR RATES X RES SDO/SA0 RES INT DRDY/INT2 CS AM07226v1 Doc ID 17116 Rev 3 7/42 Block diagram and pin description L3G4200D Table 2. Pin# 1 2 Pin description Name Vdd_IO SCL SPC SDA SDI SDO SDO SA0 CS DRDY/INT2 INT1 Reserved Reserved Reserved Reserved Reserved GND PLLFILT Reserved Vdd Power supply for I/O pins I2C serial clock (SCL) SPI serial port clock (SPC) I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) SPI serial data output (SDO) I2C least significant bit of the device address (SA0) SPI enable I2C/SPI mode selection (1:SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) Data ready/FIFO interrupt Programmable interrupt Connect to GND Connect to GND Connect to GND Connect to GND Connect to GND 0 V supply Phase-locked loop filter (see Figure 3) Connect to Vdd Power supply Function 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 3. L3G4200D external low-pass filter values (a) a. Pin 14 PLLFILT maximum voltage level is equal to Vdd. 8/42 Doc ID 17116 Rev 3 L3G4200D Block diagram and pin description Table 3. Filter values Parameter C1 C2 R2 Typical value 10 nF 470 nF 10 kΩ Doc ID 17116 Rev 3 9/42 Mechanical and electrical characteristics L3G4200D 2 2.1 Table 4. Symbol Mechanical and electrical characteristics Mechanical characteristics Mechanical characteristics @ Vdd = 3.0 V, T = 25 °C, unless otherwise noted(1) Parameter Test condition Min. Typ.(2) ±250 FS Measurement range User-selectable ±500 ±2000 FS = 250 dps So Sensitivity FS = 500 dps FS = 2000 dps SoDr Sensitivity change vs. temperature From -40 °C to +85 °C FS = 250 dps DVoff Digital zero-rate level FS = 500 dps FS = 2000 dps OffDr NL Zero-rate level change vs. temperature(3) Non linearity (4) Max. Unit dps 8.75 17.50 70 ±2 ±10 ±15 ±75 ±0.03 ±0.04 0.2 130 200 530 0.03 100/200/ 400/800 -40 +85 dps/ sqrt(Hz) Hz °C dps dps/°C dps/°C % FS dps % mdps/digit FS = 250 dps FS = 2000 dps Best fit straight line FS = 250 dps DST Self-test output change FS = 500 dps FS = 2000 dps Rn ODR Top Rate noise density Digital output data rate Operating temperature range BW = 50 Hz 1. The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table 5. 2. Typical specifications are not guaranteed. 3. Min/max values have been estimated based on the measurements of the current gyros in production. 4. Guaranteed by design. 10/42 Doc ID 17116 Rev 3 L3G4200D Mechanical and electrical characteristics 2.2 Table 5. Symbol Vdd Vdd_IO Idd IddSL IddPdn Top Electrical characteristics Electrical characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted(1) Parameter Supply voltage I/O pins supply voltage Supply current Supply current in sleep mode(4) Supply current in power-down mode Operating temperature range Selectable by digital interface Selectable by digital interface -40 (3) Test condition Min. 2.4 1.71 Typ.(2) 3.0 Max. 3.6 Vdd+0.1 Unit V V mA mA µA 6.1 1.5 5 +85 °C 1. The product is factory calibrated at 3.0 V. 2. Typical specifications are not guaranteed. 3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. 4. Sleep mode introduces a faster turn-on time compared to power-down mode. 2.3 Table 6. Symbol TSDr TODR Top Temperature sensor characteristics Temp. sensor characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted(1) Parameter Temperature sensor output change vs. temperature Temperature refresh rate Operating temperature range -40 Test condition Min. Typ.(2) -1 1 +85 Max. Unit °C/digit Hz °C 1. The product is factory calibrated at 3.0 V. 2. Typical specifications are not guaranteed. Doc ID 17116 Rev 3 11/42 Mechanical and electrical characteristics L3G4200D 2.4 2.4.1 Communication interface characteristics SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 7. SPI slave timing values Value(1) Parameter Min. Max. ns 10 5 8 5 15 50 6 50 ns MHz SPI clock cycle SPI clock frequency CS setup time CS hold time SDI input setup time SDI input hold time SDO valid output time SDO output hold time SDO output disable time 100 Unit Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO) 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results; not tested in production. Figure 4. SPI slave timing diagram(b) b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports. 12/42 Doc ID 17116 Rev 3 L3G4200D Mechanical and electrical characteristics 2.4.2 I2C - inter IC control interface Subject to general operating conditions for Vdd and Top. Table 8. Symbol f(SCL) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) I2C slave timing values I2C standard mode(1) Parameter Min SCL clock frequency SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Bus free time between STOP and START condition 4 4.7 4 4.7 0 4.7 4.0 250 0 3.45 1000 300 Max 100 Min 0 1.3 µs 0.6 100 0 20 + 0.1Cb (2) 20 + 0.1Cb (2) 0.6 0.6 µs 0.6 1.3 0.9 300 ns 300 ns µs Max 400 kHz I2C fast mode (1) Unit tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(ST) tsu(SR) tsu(SP) tw(SP:SR) 1. Data based on standard I2C protocol requirement; not tested in production. 2. Cb = total capacitance of one bus line, in pF. Figure 5. I2C slave timing diagram (c) c. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Doc ID 17116 Rev 3 13/42 Mechanical and electrical characteristics L3G4200D 2.5 Absolute maximum ratings Any stress above that listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9. Symbol Vdd TSTG Sg ESD Supply voltage Storage temperature range Acceleration g for 0.1 ms Electrostatic discharge protection Absolute maximum ratings Ratings Maximum value -0.3 to 4.8 -40 to +125 10,000 2 (HBM) Unit V °C g kV This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part This is an ESD sensitive device, improper handling can cause permanent damage to the part 14/42 Doc ID 17116 Rev 3 L3G4200D Mechanical and electrical characteristics 2.6 2.6.1 Terminology Sensitivity An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the sensitive axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time. 2.6.2 Zero-rate level Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and, therefore, the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time. 2.6.3 Stability over temperature and time Thanks to the unique single driving mass approach and optimized design, ST gyroscopes are able to guarantee a perfect match of the MEMS mechanical mass and the ASIC interface, and deliver unprecedented levels of stability over temperature and time. With Zero rate level and sensitivity performances, up to ten times better than equivalent products now available on the market, L3G4200D allows the user to avoid any further compensation and calibration during production for faster time to market, easy application implementation, higher performances and cost saving. 2.7 Soldering information The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/. Doc ID 17116 Rev 3 15/42 Main digital blocks L3G4200D 3 3.1 Main digital blocks Block diagram Figure 6. Block diagram 3.2 FIFO The L3G4200D embeds a 32-slot, 16-bit data FIFO for each of the three output channels: yaw, pitch, and roll. This allows consistent power saving for the system, as the host processor does not need to continuously poll data from the sensor. Instead, it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work in five different modes. Each mode is selected by the FIFO_MODE bits in the FIFO_CTRL_REG. Programmable watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3), and event detection information is available in FIFO_SRC_REG. The watermark level can be configured to WTM4:0 in FIFO_CTRL_REG. 3.2.1 Bypass mode In bypass mode, the FIFO is not operational and for this reason it remains empty. As illustrated in Figure 7, only the first address is used for each channel. The remaining FIFO slots are empty. When new data is available, the old data is overwritten. 16/42 Doc ID 17116 Rev 3 L3G4200D Figure 7. Bypass mode Main digital blocks 3.2.2 FIFO mode In FIFO mode, data from the yaw, pitch, and roll channels are stored in the FIFO. A watermark interrupt can be enabled (I2_WMK bit in CTRL_REG3), which is triggered when the FIFO is filled to the level specified in the WTM 4:0 bits of FIFO_CTRL_REG. The FIFO continues filling until it is full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the FIFO stops collecting data from the input channels. To restart data collection, it is necessary to write FIFO_CTRL_REG back to bypass mode. FIFO mode is represented in Figure 8. Figure 8. FIFO mode 3.2.3 Stream mode In stream mode, data from yaw, pitch, and roll measurements are stored in the FIFO. A watermark interrupt can be enabled and set as in FIFO mode. The FIFO continues filling until full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the FIFO discards the Doc ID 17116 Rev 3 17/42 Main digital blocks L3G4200D older data as the new data arrives. Programmable watermark level events can be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3). Stream mode is represented in Figure 9. Figure 9. Stream mode 3.2.4 Bypass-to-stream mode In bypass-to-stream mode, the FIFO starts operating in bypass mode, and once a trigger event occurs (related to INT1_CFG register events), the FIFO starts operating in stream mode (see Figure 10). Figure 10. Bypass-to-stream mode 18/42 Doc ID 17116 Rev 3 L3G4200D Main digital blocks 3.2.5 Stream-to-FIFO mode In stream-to-FIFO mode, data from yaw, pitch, and roll measurements are stored in the FIFO. A watermark interrupt can be enabled on pin DRDY/INT2, setting the I2_WTM bit in CTRL_REG3, which is triggered when the FIFO is filled to the level specified in the WTM4:0 bits of FIFO_CTRL_REG. The FIFO continues filling until full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the FIFO discards the older data as the new data arrives. Once a trigger event occurs (related to INT1_CFG register events), the FIFO starts operating in FIFO mode (see Figure 11). Figure 11. Trigger stream mode 3.2.6 Retrieve data from FIFO FIFO data is read through the OUT_X, OUT_Y and OUT_Z registers. When the FIFO is in stream, trigger or FIFO mode, a read operation to the OUT_X, OUT_Y or OUT_Z registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest pitch, roll, and yaw data are placed in the OUT_X, OUT_Y and OUT_Z registers and both single read and read_burst (X,Y & Z with auto-incremental address) operations can be used. In read_burst mode, when data included in OUT_Z_H is read, the system again starts to read information from addr OUT_X_L. Doc ID 17116 Rev 3 19/42 Application hints L3G4200D 4 Application hints Figure 12. L3G4200D electrical connections and external component values +Ω 1 Vdd GND GND Z 100 nF X 10 µF PLLFILT 13 12 +Ω Y Vdd 16 +Ω (TOP VIEW) DIRECTIONS OF THE DETECTABLE ANGULAR RATES X Vdd_IO SCL/SPC SDA_SDI_SDO SDO/SA0 1 TOP VIEW 4 5 8 9 10nF C1 GND CS DR INT Vdd I2C bus Rpu SCL/SPC SDA_SDI_SDO Pull-up to be added when I2C interface is used Rpu = 10kOhm PLLFILT 10kOhm 470nF R2 C2 AM07949V1 Power supply decoupling capacitors (100 nF ceramic or polyester +10 µF) should be placed as near as possible to the device (common design practice). If Vdd and Vdd_IO are not connected together, power supply decoupling capacitors (100 nF and 10 µF between Vdd and common ground, 100 nF between Vdd_IO and common ground) should be placed as near as possible to the device (common design practice). The L3G4200D IC includes a PLL (phase locked loop) circuit to synchronize driving and sensing interfaces. Capacitors and resistors must be added at the PLLFILT pin (as shown in Figure 12) to implement a second-order low-pass filter. Table 10 summarizes the PLL lowpass filter component values. Table 10. PLL low-pass filter component values Component C1 C2 R2 Value 10 nF ± 10 % 470 nF ± 10 % 10 kΩ ± 10 % 20/42 GND Doc ID 17116 Rev 3 L3G4200D Digital interfaces 5 Digital interfaces The registers embedded in the L3G4200D may be accessed through both the I2C and SPI serial interfaces. The latter may be software-configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the CS line must be tied high (i.e., connected to Vdd_IO). Table 11. Serial interface pin description Pin description SPI enable I2C/SPI mode selection (1:SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) I2C serial clock (SCL) SPI serial port clock (SPC) I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) SPI serial data output (SDO) I2C least significant bit of the device address Pin name CS SCL/SPC SDA/SDI/SDO SDO 5.1 I2C serial interface The L3G4200D I2C is a bus slave. The I2C is employed to write data to registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 12. Term Transmitter Receiver Master Slave I2C terminology Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with normal mode. Doc ID 17116 Rev 3 21/42 Digital interfaces L3G4200D 5.1.1 I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first 7 bits after a start condition with its address. If they match, the device considers itself addressed by the master. The slave address (SAD) associated with the L3G4200D is 110100xb. The SDO pin can be used to modify the least significant bit (LSb) of the device address. If the SDO pin is connected to the voltage supply, LSb is ‘1’ (address 1101001b). Otherwise, if the SDO pin is connected to ground, the LSb value is ‘0’ (address 1101000b). This solution permits the connection and addressing of two different gyroscopes to the same I2C bus. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded in the L3G4200D behaves like a slave device, and the following protocol must be adhered to. After the START (ST) condition, a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address is transmitted. The 7 LSb represent the actual register address while the MSB enables address auto-increment. If the MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow multiple data read/write. The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a REPEATED START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write) the master transmits to the slave with the direction unchanged. Table 13 describes how the SAD+read/write bit pattern is composed, listing all the possible configurations. Table 13. SAD+read/write patterns SAD[6:1] 110100 110100 110100 110100 SAD[0] = SDO 0 0 1 1 R/W 1 0 1 0 SAD+R/W 11010001 (D1h) 11010000 (D0h) 11010011 (D3h) 11010010 (D2h) Command Read Write Read Write Table 14. Master Slave Transfer when master is writing one byte to slave ST SAD + W SAK SUB SAK DATA SAK SP 22/42 Doc ID 17116 Rev 3 L3G4200D Digital interfaces Table 15. Master Slave Transfer when master is writing multiple bytes to slave ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP Table 16. Master Slave ST Transfer when master is receiving (reading) one byte of data from slave SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP Table 17. Slave Transfer when master is receiving (reading) multiple bytes of data from slave SUB SAK SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP Master ST SAD+W Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e., it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1, while SUB(6-0) represents the address of the first register to be read. In the presented communication format, MAK is “master acknowledge” and NMAK is “no master acknowledge”. 5.2 SPI bus interface The SPI is a bus slave. The SPI allows writing and reading of the device registers. The serial interface interacts with the external world through 4 wires: CS, SPC, SDI, and SDO. Doc ID 17116 Rev 3 23/42 Digital interfaces Figure 13. Read and write protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 L3G4200D SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. SPC is the serial port clock and is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. These lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the read register and write register commands are completed in 16 clock pulses, or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, etc.) starts at the last falling edge of SPC just before the rising edge of CS. Bit 0: RW bit. When 0, the data DI(7:0) is written to the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip drives SDO at the start of bit 8. Bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands. When 1, the address is auto-incremented in multiple read/write commands. Bit 2-7: address AD(5:0). This is the address field of the indexed register. Bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first). Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands, further blocks of 8 clock periods are added. When the MS bit is 0, the address used to read/write data remains the same for every block. When the MS bit is 1, the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged. 5.2.1 SPI read Figure 14. SPI read protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 24/42 Doc ID 17116 Rev 3 L3G4200D Digital interfaces The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. Bit 0: READ bit. The value is 1. Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple reading. Bit 2-7: address AD(5:0). This is the address field of the indexed register. Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). Bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 15. Multiple byte SPI read protocol (2-byte example) CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 5.2.2 SPI write Figure 16. SPI write protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. Bit 0: WRITE bit. The value is 0. Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple writing. Bit 2 -7: address AD(5:0). This is the address field of the indexed register. Bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first). Bit 16-... : data DI(...-8). Further data in multiple byte writing. Doc ID 17116 Rev 3 25/42 Digital interfaces Figure 17. Multiple byte SPI write protocol (2-byte example) CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 L3G4200D DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 5.2.3 SPI read in 3-wire mode 3-wire mode is entered by setting the SIM (SPI serial interface mode selection) bit to 1 in CTRL_REG2. Figure 18. SPI read protocol in 3-wire mode CS SPC SDI/O RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI read command is performed with 16 clock pulses: Bit 0: READ bit. The value is 1. Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple reading. Bit 2-7: address AD(5:0). This is the address field of the indexed register. Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). The multiple read command is also available in 3-wire mode. 26/42 Doc ID 17116 Rev 3 L3G4200D Output register mapping 6 Output register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 18. Register address map Register address Name Reserved WHO_AM_I Reserved CTRL_REG1 CTRL_REG2 CTRL_REG3 CTRL_REG4 CTRL_REG5 REFERENCE OUT_TEMP STATUS_REG OUT_X_L OUT_X_H OUT_Y_L OUT_Y_H OUT_Z_L OUT_Z_H FIFO_CTRL_REG FIFO_SRC_REG INT1_CFG INT1_SRC INT1_TSH_XH INT1_TSH_XL INT1_TSH_YH INT1_TSH_YL INT1_TSH_ZH INT1_TSH_ZL INT1_DURATION Type Hex r rw rw rw rw rw rw r r r r r r r r rw r rw r rw rw rw rw rw rw rw 00-0E 0F 10-1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 Binary Default Comment 000 1111 11010011 - 010 0000 00000111 010 0001 00000000 010 0010 00000000 010 0011 00000000 010 0100 00000000 010 0101 00000000 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 output output output output output output output output 010 1110 00000000 010 1111 output 011 0000 00000000 011 0001 output 011 0010 00000000 011 0011 00000000 011 0100 00000000 011 0101 00000000 011 0110 00000000 011 0111 00000000 011 1000 00000000 Doc ID 17116 Rev 3 27/42 Output register mapping L3G4200D Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up. 28/42 Doc ID 17116 Rev 3 L3G4200D Register description 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 WHO_AM_I (0Fh) Table 19. 1 WHO_AM_I register 1 0 1 0 0 1 1 Device identification register. 7.2 CTRL_REG1 (20h) Table 20. DR1 CTRL_REG1 register DR0 BW1 BW0 PD Zen Yen Xen Table 21. DR1-DR0 BW1-BW0 PD Zen Yen Xen CTRL_REG1 description Output Data Rate selection. Refer to Table 22 Bandwidth selection. Refer to Table 22 Power down mode enable. Default value: 0 (0: power down mode, 1: normal mode or sleep mode) Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled) Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled) DR is used to set ODR selection. BW is used to set Bandwidth selection. In the following table are reported all frequency resulting in combination of DR / BW bits. Table 22. DR and BW configuration setting BW 00 01 10 11 100 100 100 100 ODR [Hz] 12.5 25 25 25 Cut-Off DR 00 00 00 00 Doc ID 17116 Rev 3 29/42 Register description Table 22. DR and BW configuration setting (continued) BW 00 01 10 11 00 01 10 11 00 01 10 11 200 200 200 200 400 400 400 400 800 800 800 800 ODR [Hz] 12.5 25 50 70 20 25 50 110 30 35 50 110 L3G4200D DR 01 01 01 01 10 10 10 10 11 11 11 11 Cut-Off Combination of PD, Zen, Yen, Xen are used to set device in different modes (power down / normal / sleep mode) according with the following table. Table 23. Mode Power down Sleep Normal 0 1 1 Power mode selection configuration PD 0 Zen 0 Yen 0 Xen 7.3 CTRL_REG2 (21h) Table 24. 0 (1) CTRL_REG2 register 0(1) HPM1 HPM1 HPCF3 HPCF2 HPCF1 HPCF0 1. Value loaded at boot. This value must not be changed Table 25. HPM1HPM0 HPCF3HPCF0 CTRL_REG2 description High Pass filter Mode Selection. Default value: 00 Refer to Table 26 High Pass filter Cut Off frequency selection Refer to Table 28 30/42 Doc ID 17116 Rev 3 L3G4200D Register description Table 26. HPM1 0 0 1 1 High pass filter mode configuration HPM0 0 1 0 1 High Pass filter Mode Normal mode (reset reading HP_RESET_FILTER) Reference signal for filtering Normal mode Autoreset on interrupt event Table 27. HPCF3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 High pass filter cut off frecuency configuration [Hz] ODR= 100 Hz 8 4 2 1 0.5 0.2 0.1 0.05 0.02 0.01 ODR= 200 Hz 15 8 4 2 1 0.5 0.2 0.1 0.05 0.02 ODR= 400 Hz 30 15 8 4 2 1 0.5 0.2 0.1 0.05 ODR= 800 Hz 56 30 15 8 4 2 1 0.5 0.2 0.1 7.4 CTRL_REG3 (22h) Table 28. I1_Int1 CTRL_REG1 register I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty Table 29. I1_Int1 I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty CTRL_REG3 description Interrupt enable on INT1 pin. Default value 0. (0: Disable; 1: Enable) Boot status available on INT1. Default value 0. (0: Disable; 1: Enable) Interrupt active configuration on INT1. Default value 0. (0: High; 1:Low) Push- Pull / Open drain. Default value: 0. (0: Push- Pull; 1: Open drain) Date Ready on DRDY/INT2. Default value 0. (0: Disable; 1: Enable) FIFO Watermark interrupt on DRDY/INT2. Default value: 0. (0: Disable; 1: Enable) FIFO Overrun interrupt on DRDY/INT2 Default value: 0. (0: Disable; 1: Enable) FIFO Empty interrupt on DRDY/INT2. Default value: 0. (0: Disable; 1: Enable) Doc ID 17116 Rev 3 31/42 Register description L3G4200D 7.5 CTRL_REG4 (23h) Table 30. BDU CTRL_REG4 register BLE FS1 FS0 ST1 ST0 SIM Table 31. BDU CTRL_REG4 description Block Data Update. Default value: 0 (0: continous update; 1: output registers not updated until MSB and LSB reading) Big/Little Endian Data Selection. Default value 0. (0: Data LSB @ lower address; 1: Data MSB @ lower address) Full Scale selection. Default value: 00 (00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps) Self Test Enable. Default value: 00 (00: Self Test Disabled; Other: See Table ) SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface). BLE FS1-FS0 ST1-ST0 SIM Table 32. Self test mode configuration ST1 ST0 0 1 0 1 Normal mode Self test 0 (+)(1) -Self test 1 (-)(1) Self test mode 0 0 1 1 1. DST sign (absolute value in Table 4) 7.6 CTRL_REG5 (24h) Table 33. BOOT CTRL_REG5 register FIFO_EN -HPen INT1_Sel1 INT1_Sel0 Out_Sel1 Out_Sel0 Table 34. BOOT FIFO_EN HPen INT1_Sel1INT1_Sel0 Out_Sel1Out_Sel1 32/42 CTRL_REG5 description Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) FIFO enable. Default value: 0 (0: FIFO disable; 1: FIFO Enable) High Pass filter Enable. Default value: 0 (0: HPF disabled; 1: HPF enabled. See Figure 20) INT1 selection configuration. Default value: 0 (See Figure 20) Out selection configuration. Default value: 0 (See Figure 20 Doc ID 17116 Rev 3 L3G4200D Figure 19. INT1_Sel and Out_Sel configuration block diagram Register description Out_Sel 00 01 0 LPF2 ADC DataReg FIFO 32x16x3 10 11 LPF1 HPF 1 HPen 10 11 01 00 AM07949V2 INT1_Sel Interrupt generator Table 35. Hpen x x 0 1 Out_Sel configuration setting OUT_SEL1 0 0 1 1 OUT_SEL0 0 1 x x Description Data in DataReg and FIFO are non-highpass-filtered Data in DataReg and FIFO are high-passfiltered Data in DataReg and FIFO are low-passfiltered by LPF2 Data in DataReg and FIFO are high-pass and low-pass-filtered by LPF2 Table 36. Hpen x x 0 1 INT_SEL configuration setting INT_SEL1 0 0 1 1 INT_SEL2 0 1 x x Description Non-high-pass-filtered data are used for interrupt generation High-pass-filtered data are used for interrupt generation Low-pass-filtered data are used for interrupt generation High-pass and low-pass-filtered data are used for interrupt generation Doc ID 17116 Rev 3 33/42 Register description L3G4200D 7.7 REFERENCE/DATACAPTURE (25h) Table 37. Ref7 REFERENCE register Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Table 38. Ref 7-Ref0 REFERENCE register description Reference value for Interrupt generation. Default value: 0 7.8 OUT_TEMP (26h) Table 39. Temp7 OUT_TEMP register Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0 Table 40. OUT_TEMP register description Temperature data. Temp7-Temp0 7.9 STATUS_REG (27h) Table 41. ZYXOR STATUS_REG register ZOR YOR XOR ZYXDA ZDA YDA XDA Table 42. STATUS_REG description X, Y, Z -axis data overrun. Default value: 0 ZYXOR (0: no overrun has occurred; 1: new data has overwritten the previous one before it was read) ZOR YOR XOR Z axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one) Y axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one) X axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one) ZYXDA X, Y, Z -axis new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) ZDA YDA XDA Z axis new data available. Default value: 0 (0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available) Y axis new data available. Default value: 0 (0: a new data for the Y-axis is not yet available;1: a new data for the Y-axis is available) X axis new data available. Default value: 0 (0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available) 34/42 Doc ID 17116 Rev 3 L3G4200D Register description 7.10 OUT_X_L (28h), OUT_X_H (29h) X-axis angular rate data. The value is expressed as two’s complement. 7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh) Y-axis angular rate data. The value is expressed as two’s complement. 7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh) Z-axis angular rate data. The value is expressed as two’s complement. 7.13 FIFO_CTRL_REG (2Eh) Table 43. FM2 REFERENCE register FM1 FM0 WTM4 WTM3 WTM2 WTM1 WTM0 Table 44. FM2-FM0 REFERENCE register description FIFO mode selection. Default value: 00 (see Table ) FIFO threshold. Watermark level setting WTM4-WTM0 Table 45. FM2 0 0 0 0 1 0 0 1 1 0 FIFO mode configuration FM1 0 1 0 1 0 FM0 Bypass mode FIFO mode Stream mode Stream-to-FIFO mode Bypass-to-Stream mode FIFO mode 7.14 FIFO_SRC_REG (2Fh) Table 46. WTM FIFO_SRC register OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 Table 47. WTM OVRN FIFO_SRC register description Watermark status. (0: FIFO filling is lower than WTM level; 1: FIFO filling is equal or higher than WTM level) Overrun bit status. (0: FIFO is not completely filled; 1:FIFO is completely filled) Doc ID 17116 Rev 3 35/42 Register description Table 47. EMPTY FSS4-FSS1 L3G4200D FIFO_SRC register description (continued) FIFO empty bit. ( 0: FIFO not empty; 1: FIFO empty) FIFO stored data level 7.15 INT1_CFG (30h) Table 48. AND/OR INT1_CFG register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Table 49. AND/OR INT1_CFG description AND/OR combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events 1: AND combination of interrupt events Latch Interrupt Request. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Cleared by reading INT1_SRC reg. Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Configuration register for Interrupt source. 7.16 INT1_SRC (31h) Table 50. 0 INT1_SRC register IA ZH ZL YH YL XH XL 36/42 Doc ID 17116 Rev 3 L3G4200D Register description Table 51. IA ZH ZL YH YL XH XL INT1_SRC description Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value: 0 (0: no interrupt, 1: Z High event has occurred) Z low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) Y high. Default value: 0 (0: no interrupt, 1: Y High event has occurred) Y low. Default value: 0 (0: no interrupt, 1: Y Low event has occurred) X high. Default value: 0 (0: no interrupt, 1: X High event has occurred) X low. Default value: 0 (0: no interrupt, 1: X Low event has occurred) Interrupt source register. Read only register. Reading at this address clears INT1_SRC IA bit (and eventually the interrupt signal on INT1 pin) and allows the refreshment of data in the INT1_SRC register if the latched option was chosen. 7.17 INT1_THS_XH (32h) Table 52. - INT1_THS_XH register THSX14 THSX13 THSX12 THSX11 THSX10 THSX9 THSX8 Table 53. INT1_THS_XH description Interrupt threshold. Default value: 0000 0000 THSX14 - THSX9 7.18 INT1_THS_XL (33h) Table 54. THSX7 INT1_THS_XL register THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0 Table 55. INT1_THS_XL description Interrupt threshold. Default value: 0000 0000 THSX7 - THSX0 7.19 INT1_THS_YH (34h) Table 56. - INT1_THS_YH register THSY14 THSY13 THSY12 THSY11 THSY10 THSY9 THSY8 Table 57. INT1_THS_YH description Interrupt threshold. Default value: 0000 0000 THSY14 - THSY9 Doc ID 17116 Rev 3 37/42 Register description L3G4200D 7.20 INT1_THS_YL (35h) Table 58. THSR7 INT1_THS_YL register THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0 Table 59. INT1_THS_YL description Interrupt threshold. Default value: 0000 0000 THSY7 - THSY0 7.21 INT1_THS_ZH (36h) Table 60. - INT1_THS_ZH register THSZ14 THSZ13 THSZ12 THSZ11 THSZ10 THSZ9 THSZ8 Table 61. INT1_THS_ZH description Interrupt threshold. Default value: 0000 0000 THSZ14 - THSZ9 7.22 INT1_THS_ZL (37h) Table 62. THSZ7 INT1_THS_ZL register THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0 Table 63. INT1_THS_ZL description Interrupt threshold. Default value: 0000 0000 THSZ7 - THSZ0 7.23 INT1_DURATION (38h) Table 64. WAIT INT1_DURATION register D6 D5 D4 D3 D2 D1 D0 Table 65. WAIT D6 - D0 INT1_DURATION description WAIT enable. Default value: 0 (0: disable; 1: enable) Duration value. Default value: 000 0000 D6 - D0 bits set the minimum duration of the Interrupt event to be recognized. Duration steps and maximum values depend on the ODR chosen. WAIT bit has the following meaning: Wait =’0’: the interrupt falls immediately if signal crosses the selected threshold 38/42 Doc ID 17116 Rev 3 L3G4200D Register description Wait =’1’: if signal crosses the selected threshold, the interrupt falls only after the duration has counted number of samples at the selected data rate, written into the duration counter register. Figure 20. Wait disabled Figure 21. Wait enabled Doc ID 17116 Rev 3 39/42 Package information L3G4200D 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark. Figure 22. LGA-16: mechanical data and package dimensions 40/42 Doc ID 17116 Rev 3 L3G4200D Revision history 9 Revision history Table 66. Date 01-Apr-2010 03-Sep-2010 22-Dec-2010 Document revision history Revision 1 2 3 Initial release. Complete datasheet review. Inserted Section 6: Output register mapping and Section 7: Register description. Changes Doc ID 17116 Rev 3 41/42 L3G4200D Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 42/42 Doc ID 17116 Rev 3