L3GD20TR

L3GD20 MEMS motion sensor: three-axis digital output gyroscope Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Three selectable full scales (250/500/2000 dps) I2C/SPI digital output interface 16 bit-rate value data output 8-bit temperature data output Two digital output lines (interrupt and data ready) Integrated low- and high-pass filters with userselectable bandwidth Wide supply voltage: 2.4 V to 3.6 V Low voltage-compatible IOs (1.8 V) Embedded power-down and sleep mode Embedded temperature sensor Embedded FIFO High shock survivability Extended operating temperature range (-40 °C to +85 °C) ECOPACK® RoHS and “Green” compliant LGA-16 (4x4x1 mm) Description The L3GD20 is a low-power three-axis angular rate sensor. It includes a sensing element and an IC interface capable of providing the measured angular rate to the external world through a digital interface (I2C/SPI). The sensing element is manufactured using a dedicated micro-machining process developed by STMicroelectronics to produce inertial sensors and actuators on silicon wafers. The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The L3GD20 has a full scale of ±250/±500/ ±2000 dps and is capable of measuring rates with a user-selectable bandwidth. The L3GD20 is available in a plastic land grid array (LGA) package and can operate within a temperature range of -40 °C to +85 °C. Applications ■ ■ ■ ■ Gaming and virtual reality input devices Motion control with MMI (man-machine interface) GPS navigation systems Appliances and robotics Table 1. Device summary Order code L3GD20 L3GD20TR Temperature range (°C) -40 to +85 -40 to +85 Package LGA-16 (4x4x1 mm) LGA-16 (4x4x1 mm) Packing Tray Tape and reel August 2011 Doc ID 022116 Rev 1 1/44 www.st.com 44 Contents L3GD20 Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 2.3 2.4 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 2.4.2 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 2.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.1 2.6.2 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 4.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 5.2 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/44 Doc ID 022116 Rev 1 L3GD20 5.2.2 5.2.3 Contents SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 7 Output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 REFERENCE/DATACAPTURE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OUT_TEMP (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_THS_XH (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_XL (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_YH (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_YL (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_ZH (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 INT1_THS_ZL (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 INT1_DURATION (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Doc ID 022116 Rev 1 3/44 List of tables L3GD20 List of tables Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C slave timing values (TBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 24 Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 24 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 High-pass filter cut off frequency configuration [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OUT_TEMP register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT1_THS_XH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_XH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/44 Doc ID 022116 Rev 1 L3GD20 Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. List of tables INT1_THS_XL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_YH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_YH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_YL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_YL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INT1_THS_ZH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 INT1_THS_ZH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 INT1_THS_ZL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 INT1_THS_ZL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Doc ID 022116 Rev 1 5/44 List of figures L3GD20 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 L3GD20 electrical connections and external component values . . . . . . . . . . . . . . . . . . . . 15 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 INT1_Sel and Out_Sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6/44 Doc ID 022116 Rev 1 L3GD20 Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram +Ω x,y,z X+ Y+ Z+ M U X CHARGE AMP MIXER LOW-PASS FILTER A D C 1 ZYX- D I G I T A L F I L T E R I N G I2C SPI CS SCL/SPC SDA/SDO/SDI SDO DRIVING MASS Feedback loop T E M P E R A T U R E S E N S O R A D C 2 REFERENCE TRIMMING CIRCUITS FIFO CLOCK & PHASE GENERATOR CONTROL LOGIC & INTERRUPT GEN. INT1 DRDY/INT2 AM10126V1 Note: The vibration of the structure is maintained by drive circuitry in a feedback loop. The sensing signal is filtered and appears as a digital signal at the output. 1.1 Pin description Figure 2. Pin connection +Ω GND RES RES Z X +Ω 13 16 1 Y RES RES RES Vdd Vdd_IO SCL/SPC SDA/SDI/SDO 4 12 BOTTOM VIEW 9 8 5 +Ω X (TOP VIEW) DIRECTIONS OF THE DETECTABLE ANGULAR RATES RES SDO/SA0 DRDY/INT2 RES INT1 CS AM10127V1 Doc ID 022116 Rev 1 7/44 Block diagram and pin description Table 2. Pin# 1 2 L3GD20 Pin description Name Vdd_IO(1) SCL SPC SDA SDI SDO SDO SA0 CS DRDY/INT2 INT1 Reserved Reserved Reserved Reserved Reserved GND Reserved Reserved Vdd(3) Power supply for I/O pins I2C serial clock (SCL) SPI serial port clock (SPC) I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) SPI serial data output (SDO) I2C less significant bit of the device address (SA0) I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) Data ready/FIFO interrupt (Watermark/Overrun/Empty) Programmable interrupt Connect to GND Connect to GND Connect to GND Connect to GND Connect to GND 0 V supply Connect to GND with ceramic capacitor(2) Connect to Vdd Power supply Function 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1. 100 nF filter capacitor recommended. 2. 1 nF min value must be guaranteed under 11 V bias condition. 3. 100 nF plus 10 µF capacitors recommended. 8/44 Doc ID 022116 Rev 1 L3GD20 Mechanical and electrical specifications 2 2.1 Table 3. Symbol Mechanical and electrical specifications Mechanical characteristics @ Vdd = 3.0 V, T = 25 °C unless otherwise noted. Mechanical characteristics(1) Parameter Test condition Min. Typ.(2) ±250 FS Measurement range User-selectable ±500 ±2000 FS = 250 dps So Sensitivity FS = 500 dps FS = 2000 dps SoDr Sensitivity change vs. temperature From -40 °C to +85 °C FS = 250 dps DVoff Digital zero-rate level FS = 500 dps FS = 2000 dps OffDr NL Rn ODR Top Zero-rate level change vs. temperature Non linearity Rate noise density Digital output data rate Operating temperature range -40 FS = 250 dps FS = 2000 dps Best fit straight line 8.75 17.50 70 ±2 ±10 ±15 ±75 ±0.03 ±0.04 0.2 0.03 95/190/ 380/760 +85 dps/°C dps/°C % FS dps ⁄ ( H z Hz °C dps % mdps/digit dps Max. Unit 1. The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table 4. 2. Typical specifications are not guaranteed. Doc ID 022116 Rev 1 9/44 Mechanical and electrical specifications L3GD20 2.2 Electrical characteristics @ Vdd =3.0 V, T=25 °C unless otherwise noted. Table 4. Symbol Vdd Vdd_IO Idd IddSL IddPdn VIH VIL Top Electrical characteristics (1) Parameter Supply voltage I/O pins supply voltage Supply current Supply current in sleep mode(4) Supply current in power-down mode Digital high level input voltage Digital low level input voltage Operating temperature range -40 Selectable by digital interface Selectable by digital interface 0.8*Vdd_I O 0.2*Vdd_I O +85 (3) Test condition Min. 2.4 1.71 Typ.(2) 3.0 Max. 3.6 Vdd+0.1 Unit V V mA mA µA V V °C 6.1 2 5 1. The product is factory calibrated at 3.0 V. 2. Typical specifications are not guaranteed. 3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses; in this condition the measurement chain is powered off. 4. Sleep mode introduces a faster turn-on time relative to power-down mode. 2.3 Temperature sensor characteristics @ Vdd =3.0 V, T=25 °C unless otherwise noted. Table 5. Symbol TSDr TODR Top Electrical characteristics (1) Parameter Temperature sensor output change vs. temperature Temperature refresh rate Operating temperature range -40 Test condition Min. Typ.(2) -1 1 +85 Max. Unit °C/digit Hz °C 1. The product is factory calibrated at 3.0 V. 2. Typical specifications are not guaranteed. 10/44 Doc ID 022116 Rev 1 L3GD20 Mechanical and electrical specifications 2.4 2.4.1 Communication interface characteristics SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 6. SPI slave timing values Value(1) Parameter Min Max ns 10 5 8 5 15 50 6 50 ns MHz SPI clock cycle SPI clock frequency CS setup time CS hold time SDI input setup time SDI input hold time SDO valid output time SDO output hold time SDO output disable time 100 Unit Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO) 1. Values are guaranteed at a 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results; not tested in production. Figure 3. SPI slave timing diagram (a) a. Measurement points are at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output port. Doc ID 022116 Rev 1 11/44 Mechanical and electrical specifications L3GD20 2.4.2 I2C - Inter IC control interface Subject to general operating conditions for Vdd and Top. Table 7. Symbol f(SCL) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) I2C slave timing values (TBC) I2C standard mode(1) Parameter Min SCL clock frequency SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Bus free time between STOP and START condition 4 4.7 4 4.7 0 4.7 4.0 250 0 3.45 1000 300 Max 100 Min 0 1.3 µs 0.6 100 0 20 + 0.1Cb (2) 20 + 0.1Cb (2) 0.6 0.6 µs 0.6 1.3 0.9 300 ns 300 ns µs Max 400 kHz I2C fast mode (1) Unit tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(ST) tsu(SR) tsu(SP) tw(SP:SR) 1. Data based on standard I2C protocol requirement; not tested in production. 2. Cb = total capacitance of one bus line, in pF. Figure 4. I2C slave timing diagram (b) b. Measurement points are at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. 12/44 Doc ID 022116 Rev 1 L3GD20 Mechanical and electrical specifications 2.5 Absolute maximum ratings Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 8. Symbol Vdd TSTG Sg Supply voltage Storage temperature range Acceleration g for 0.1 ms Absolute maximum ratings Ratings Maximum value -0.3 to 4.8 -40 to +125 10,000 2 (HBM) Unit V °C g kV kV V V ESD Electrostatic discharge protection 1.5 (CDM) 200 (MM) Vin Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0) -0.3 to Vdd_IO +0.3 Note: Supply voltage on any pin should never exceed 4.8 V This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part This is an ESD sensitive device, improper handling can cause permanent damage to the part Doc ID 022116 Rev 1 13/44 Mechanical and electrical specifications L3GD20 2.6 2.6.1 Terminology Sensitivity An angular rate gyroscope is a device that produces a positive-going digital output for counter-clockwise rotation around the sensitive axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time. 2.6.2 Zero-rate level Zero-rate level describes the actual output signal if there is no angular rate present. Zerorate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time. 2.7 Soldering information The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/mems. 14/44 Doc ID 022116 Rev 1 L3GD20 Application hints 3 Application hints Figure 5. L3GD20 electrical 9nF connections and external component values +Ω Vdd GND GND 10nF(25V)* 100 nF 10 µF X Z C1 +Ω Y Vdd GND 14 13 12 16 +Ω (TOP VIEW) DIRECTIONS OF THE DETECTABLE ANGULA RATES X Vdd_IO SCL/SPC SDA_SDI_SDO SDO/SA0 1 TOP VIEW 4 5 8 9 CS DR INT Vdd I2C bus Rpu = 10kOhm Rpu SCL/SPC * C1 must guarantee 1 nF value under 11 V bias condition SDA_SDI_SDO Pull-up to be added when I2C interface is used AM10128V1 Power supply decoupling capacitors (100 nF + 10 µF) should be placed as near as possible to the device (common design practice). If Vdd and Vdd_IO are not connected together, 100 nF and 10 µF decoupling capacitors must be placed between Vdd and common ground, and 100 nF between Vdd_IO and common ground. Capacitors should be placed as near as possible to the device (common design practice). Doc ID 022116 Rev 1 GND 15/44 Digital main blocks L3GD20 4 4.1 Digital main blocks Block diagram Figure 6. Block diagram Out_Sel 00 01 0 LPF2 ADC DataReg FIFO 32x16x3 I2C SPI 10 11 INT_Sel 10 11 01 00 LPF1 HPF 1 HPen Interrupt generator SCR REG CONF REG INT1 AM07230v1 4.2 FIFO The L3GD20 embeds 32 slots of 16-bit data FIFO for each of the three output channels: yaw, pitch and roll. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but can wake up only when needed and burst the significant data out from the FIFO. This buffer can work accordingly in five different modes: Bypass mode, FIFO mode, Stream mode, Bypass-toStream mode and Stream-to-FIFO mode. Each mode is selected by the FIFO_MODE bits in the FIFO_CTRL_REG (2Eh). Programmable Watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3 (22h) and event detection information is available in FIFO_SRC_REG (2Fh). Watermark level can be configured to WTM4:0 in FIFO_CTRL_REG (2Eh). 16/44 Doc ID 022116 Rev 1 L3GD20 Digital main blocks 4.2.1 Bypass mode In Bypass mode, the FIFO is not operational and for this reason it remains empty. As described in Figure 7 below, for each channel only the first address is used. The remaining FIFO slots are empty. When new data is available, the old data is overwritten. Figure 7. Bypass mode xi,yi,zi x0 x1 y i0 y1 y2 z0 z1 empty x 31 y 31 l x2 z2 z31 AM07231v1 4.2.2 FIFO mode In FIFO mode, data from the yaw, pitch and roll channels is stored in the FIFO. A watermark interrupt can be enabled (I2_WMK bit into CTRL_REG3 (22h)) in order to be raised when the FIFO is filled to the level specified in the WTM 4:0 bits of FIFO_CTRL_REG (2Eh). The FIFO continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). When full, the FIFO stops collecting data from the input channels. To restart data collection, the FIFO_CTRL_REG (2Eh) must be written back to Bypass mode. FIFO mode is represented in Figure 8: FIFO mode. Doc ID 022116 Rev 1 17/44 Digital main blocks Figure 8. FIFO mode L3GD20 xi,yi,zi x0 x1 x2 y i0 y1 y2 z0 z1 z2 x 31 y 31 z31 AM07232v1 4.2.3 Stream mode In Stream mode, data from yaw, pitch and roll measurement are stored in the FIFO. A watermark interrupt can be enabled and set as in the FIFO mode.The FIFO continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). When full, the FIFO discards the older data as the new data arrives. Programmable watermark level events can be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3 (22h). Stream mode is represented in Figure 9: Stream mode. 18/44 Doc ID 022116 Rev 1 L3GD20 Figure 9. Stream mode Digital main blocks xi,yi,zi x0 x1 x2 y0 y1 y2 z0 z1 z2 x 30 x 31 y 30 y 31 z30 z31 AM07234v1 Doc ID 022116 Rev 1 19/44 Digital main blocks L3GD20 4.2.4 Bypass-to-stream mode In Bypass-to-stream mode, the FIFO begins operating in Bypass mode and once a trigger event occurs (related to INT1_CFG (30h) register events), the FIFO starts operating in Stream mode. Refer to Figure 10 below. Figure 10. Bypass-to-stream mode xi,yi,zi x0 x1 Empty x2 y i0 y1 y2 z0 z1 z2 x 30 x 31 y 30 y 31 z30 z31 xi,yi,zi x0 x1 x2 y0 y1 y2 z0 z1 z2 x 31 y 31 z31 Bypass mode Trigger event Stream mode AM07235v1 4.2.5 Stream-to-FIFO mode In Stream-to-FIFO mode, data from yaw, pitch and roll measurement is stored in the FIFO. A watermark interrupt can be enabled on pin DRDY/INT2 by setting the I2_WTM bit in CTRL_REG3 (22h) in order to be raised when the FIFO is filled to the level specified in the WTM4:0 bits of FIFO_CTRL_REG (2Eh). The FIFO continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). When full, the FIFO discards the older data as the new data arrives. Once a trigger event occurs (related to INT1_CFG (30h) register events), the FIFO starts operating in FIFO mode. Refer to Figure 11 below. Figure 11. Trigger stream mode xi,yi,zi x0 x1 x2 x 30 x 31 y0 y1 y2 y 30 y 31 z0 z1 z2 xi,yi,zi x0 x1 x2 y i0 y1 y2 z0 z1 z2 z30 z31 x 31 y 31 z31 Stream Mode Trigger event FIFO Mode AM07236v1 20/44 Doc ID 022116 Rev 1 L3GD20 Digital main blocks 4.2.6 Retrieve data from FIFO FIFO data is read through OUT_X (Addr reg 28h,29h), OUT_Y (Addr reg 2Ah,2Bh) and OUT_Z (Addr reg 2Ch,2Dh). When the FIFO is in Stream, Trigger or FIFO mode, a read operation of the OUT_X, OUT_Y or OUT_Z registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest pitch, roll and yaw data is placed in the OUT_X, OUT_Y and OUT_Z registers and both single read and read_burst (X,Y & Z with auto-incrementing address) operations can be used. When data included in OUT_Z_H (2Dh) is read, the system restarts to read information from addr OUT_X_L (28h). Doc ID 022116 Rev 1 21/44 Digital interfaces L3GD20 5 Digital interfaces The registers embedded in the L3GD20 may be accessed through both the I2C and SPI serial interfaces. The latter may be SW-configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the CS line must be tied high (i.e connected to Vdd_IO). Table 9. Serial interface pin description Pin description I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) I2C serial clock (SCL) SPI serial port clock (SPC) I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) SPI serial data output (SDO) I2C less significant bit of the device address Pin name CS SCL/SPC SDA/SDI/SDO SDO 5.1 I2C serial interface The L3GD20 I2C is a bus slave. The I2C is employed to write data into registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 10. Term Transmitter Receiver Master Slave I2C terminology Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through external pull-up resistors. When the bus is free, both lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with normal mode. 22/44 Doc ID 022116 Rev 1 L3GD20 Digital interfaces 5.1.1 I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated with the L3GD20 is 110101xb. The SDO pin can be used to modify the less significant bit of the device address. If the SDO pin is connected to voltage supply, LSb is ‘1’ (address 1101011b). Otherwise, if the SDO pin is connected to ground, the LSb value is ‘0’ (address 1101010b). This solution allows to connect and address two different gyroscopes to the same I2C bus. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obligated to generate an acknowledge after each byte of data received. The I2C embedded in the L3GD20 behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address is transmitted: the 7 LSb represent the actual register address while the MSb enables address auto-increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged. Table 11 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 11. SAD+read/write patterns SAD[6:1] 110101 110101 110101 110101 SAD[0] = SDO 0 0 1 1 R/W 1 0 1 0 SAD+R/W 11010101 (D1h) 11010100 (D0h) 11010111 (D3h) 11010110 (D2h) Command Read Write Read Write Table 12. Master Slave Transfer when master is writing one byte to slave ST SAD + W SAK SUB SAK DATA SAK SP Doc ID 022116 Rev 1 23/44 Digital interfaces L3GD20 Table 13. Master Slave Transfer when master is writing multiple bytes to slave ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP Table 14. Master Slave ST Transfer when master is receiving (reading) one byte of data from slave SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP Table 15. Slave Transfer when master is receiving (reading) multiple bytes of data from slave SUB SAK SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP Master ST SAD+W Data is transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes sent per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL, LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to ‘1’ while SUB(6-0) represents the address of the first register to be read. In the communication format presented, MAK is Master Acknowledge and NMAK is No Master Acknowledge. 5.2 SPI bus interface The SPI is a bus slave. The SPI allows writing and reading the registers of the device. The serial interface interacts with the outside world through 4 wires: CS, SPC, SDI and SDO. 24/44 Doc ID 022116 Rev 1 L3GD20 Figure 12. Read and write protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 Digital interfaces DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 AM10129V1 CS is the Serial Port Enable and is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written to the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands. When 1, the address will be auto-incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written to the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands, further blocks of 8 clock periods will be added. When the MS bit is 0, the address used to read/write data remains the same for every block. When the MS bit is 1, the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged. Doc ID 022116 Rev 1 25/44 Digital interfaces L3GD20 5.2.1 SPI read Figure 13. SPI read protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 AM10130V1 The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address; when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 14. Multiple byte SPI read protocol (2-byte example) CS SPC S DI RW M S A D5 A D4 AD 3 A D2 A D1 A D0 SD O DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0 DO 15 DO 14 DO 1 3 D O 12 DO 11 DO 10 D O9 D O8 AM10131V1 26/44 Doc ID 022116 Rev 1 L3GD20 Digital interfaces 5.2.2 SPI write Figure 15. SPI write protocol CS SPC SDI RW MS AD5 AD 4 AD 3 AD2 AD 1 AD0 D I7 D I6 D I5 D I4 DI 3 DI2 DI1 DI0 AM10132V1 The SPI Write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written to the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 16. Multiple byte SPI write protocol (2-byte example) CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD 0 DI7 D I6 DI5 D I4 DI 3 DI2 DI1 DI0 DI15 D I1 4DI13 D I1 2DI11 DI10 DI9 DI 8 AM10133V1 5.2.3 SPI read in 3-wire mode 3-wire mode is entered by setting the bit SIM (SPI serial interface mode selection) to ‘1’ in CTRL_REG2. Doc ID 022116 Rev 1 27/44 Digital interfaces Figure 17. SPI read protocol in 3-wire mode L3GD20 CS SPC SDI/O RW MS AD5 AD 4 AD 3 AD2 AD1 AD 0 D O7 D O6 D O5 DO4 DO 3 DO2 DO1 DO0 AM10134V1 The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). Multiple read command is also available in 3-wire mode. 28/44 Doc ID 022116 Rev 1 L3GD20 Output register mapping 6 Output register mapping The table below provides a listing of the 8-bit registers embedded in the device, and the related addresses: Table 16. Register address map Register address Name Reserved WHO_AM_I Reserved CTRL_REG1 CTRL_REG2 CTRL_REG3 CTRL_REG4 CTRL_REG5 REFERENCE OUT_TEMP STATUS_REG OUT_X_L OUT_X_H OUT_Y_L OUT_Y_H OUT_Z_L OUT_Z_H FIFO_CTRL_REG FIFO_SRC_REG INT1_CFG INT1_SRC INT1_TSH_XH INT1_TSH_XL INT1_TSH_YH INT1_TSH_YL INT1_TSH_ZH INT1_TSH_ZL INT1_DURATION Type Hex r rw rw rw rw rw rw r r r r r r r r rw r rw r rw rw rw rw rw rw rw 00-0E 0F 10-1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 Binary 000 1111 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 010 1110 010 1111 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 11010100 00000111 00000000 00000000 00000000 00000000 00000000 output output output output output output output output 00000000 output 00000000 output 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Default Doc ID 022116 Rev 1 29/44 Output register mapping L3GD20 Registers marked as Reserved must not be changed. Writing to these registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. 30/44 Doc ID 022116 Rev 1 L3GD20 Register description 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve angular rate data. The register address, consisting of 7 bits, is used to identify them and to write the data through the serial interface. 7.1 WHO_AM_I (0Fh) Table 17. 1 WHO_AM_I register 1 0 1 0 1 0 0 Device identification register. 7.2 CTRL_REG1 (20h) Table 18. DR1 CTRL_REG1 register DR0 BW1 BW0 PD Zen Xen Yen Table 19. DR1-DR0 BW1-BW0 PD Zen Yen Xen CTRL_REG1 description Output data rate selection. Refer to Table 20 Bandwidth selection. Refer to Table 20 Power-down mode enable. Default value: 0 (0: power-down mode, 1: normal mode or sleep mode) Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled) Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled) DR is used for ODR selection. BW is used for Bandwidth selection. In the Table 20 all frequencies resulting in combinations of DR / BW bits are reported. Table 20. DR and BW configuration setting BW 00 01 10 95 95 95 ODR [Hz] 12.5 25 25 Cut-Off DR 00 00 00 Doc ID 022116 Rev 1 31/44 Register description Table 20. DR and BW configuration setting (continued) BW 11 00 01 10 11 00 01 10 11 00 01 10 11 95 190 190 190 190 380 380 380 380 760 760 760 760 ODR [Hz] 25 12.5 25 50 70 20 25 50 100 30 35 50 100 L3GD20 DR 00 01 01 01 01 10 10 10 10 11 11 11 11 Cut-Off A combination of PD, Zen, Yen, Xen is used to set device to different modes (power-down / normal / sleep mode) in accordance with Table 21 below. Table 21. Mode Power-down Sleep Normal 0 1 1 Power mode selection configuration PD 0 Zen 0 Yen 0 Xen 7.3 CTRL_REG2 (21h) Table 22. 0 (1) CTRL_REG2 register 0(1) HPM1 HPM1 HPCF3 HPCF2 HPCF1 HPCF0 1. These bits must be set to ‘0’ to ensure proper operation of the device Table 23. HPM1HPM0 HPCF3HPCF0 CTRL_REG2 description High-pass filter mode selection. Default value: 00 Refer to Table 24 High-pass filter cutoff frequency selection Refer to Table 25 32/44 Doc ID 022116 Rev 1 L3GD20 Register description Table 24. HPM1 0 0 1 1 High-pass filter mode configuration HPM0 0 1 0 1 High-pass filter mode Normal mode (reset reading HP_RESET_FILTER) Reference signal for filtering Normal mode Autoreset on interrupt event Table 25. HPCF3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 High-pass filter cut off frequency configuration [Hz] ODR=95 Hz 7.2 3.5 1.8 0.9 0.45 0.18 0.09 0.045 0.018 0.009 ODR=190 Hz 13.5 7.2 3.5 1.8 0.9 0.45 0.18 0.09 0.045 0.018 27 13.5 7.2 3.5 1.8 0.9 0.45 0.18 0.09 0.045 ODR=380 Hz ODR=760 Hz 51.4 27 13.5 7.2 3.5 1.8 0.9 0.45 0.18 0.09 7.4 CTRL_REG3 (22h) Table 26. I1_Int1 CTRL_REG1 register I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty Table 27. I1_Int1 I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty CTRL_REG3 description Interrupt enable on INT1 pin. Default value 0. (0: disable; 1: enable) Boot status available on INT1. Default value 0. (0: disable; 1: enable) Interrupt active configuration on INT1. Default value 0. (0: high; 1:low) Push-pull / Open drain. Default value: 0. (0: push- pull; 1: open drain) Date-ready on DRDY/INT2. Default value 0. (0: disable; 1: enable) FIFO watermark interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable) FIFO overrun interrupt on DRDY/INT2 Default value: 0. (0: disable; 1: enable) FIFO empty interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable) Doc ID 022116 Rev 1 33/44 Register description L3GD20 7.5 CTRL_REG4 (23h) Table 28. BDU CTRL_REG4 register BLE FS1 FS0 0(1) 0(1) SIM 1. This value must not be changed. Table 29. BDU CTRL_REG4 description Block data update. Default value: 0 (0: continuos update; 1: output registers not updated until MSb and LSb reading) Big/little endian data selection. Default value 0. (0: Data LSb @ lower address; 1: Data MSb @ lower address) Full scale selection. Default value: 00 (00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps) SPI serial interface mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface). BLE FS1-FS0 SIM 7.6 CTRL_REG5 (24h) Table 30. BOOT CTRL_REG5 register FIFO_EN -HPen INT1_Sel1 INT1_Sel0 Out_Sel1 Out_Sel0 Table 31. BOOT FIFO_EN HPen INT1_Sel1INT1_Sel0 Out_Sel1Out_Sel1 CTRL_REG5 description Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) FIFO enable. Default value: 0 (0: FIFO disable; 1: FIFO Enable) High-pass filter enable. Default value: 0 (0: HPF disabled; 1: HPF enabled See Figure 20) INT1 selection configuration. Default value: 0 (See Figure 20) Out selection configuration. Default value: 0 (See Figure 20) 34/44 Doc ID 022116 Rev 1 L3GD20 Figure 18. INT1_Sel and Out_Sel configuration block diagram Register description Out_Sel 00 01 0 LPF2 ADC DataReg FIFO 32x16x3 10 11 LPF1 HPF 1 HPen 10 11 01 00 AM07949V2 INT1_Sel Interrupt generator 7.7 REFERENCE/DATACAPTURE (25h) Table 32. Ref7 REFERENCE register Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Table 33. Ref 7-Ref0 REFERENCE register description Reference value for interrupt generation. Default value: 0 7.8 OUT_TEMP (26h) Table 34. Temp7 OUT_TEMP register Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0 Table 35. OUT_TEMP register description Temperature data Temp7-Temp0 Temperature data (1LSB/deg - 8-bit resolution). The value is expressed as two's complement. Doc ID 022116 Rev 1 35/44 Register description L3GD20 7.9 STATUS_REG (27h) Table 36. ZYXOR STATUS_REG register ZOR YOR XOR ZYXDA ZDA YDA XDA Table 37. STATUS_REG description X, Y, Z -axis data overrun. Default value: 0 ZYXOR (0: no overrun has occurred; 1: new data has overwritten the previous data before it was read) ZOR YOR XOR Z axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data) Y axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data) X axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data) ZYXDA X, Y, Z -axis new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) ZDA YDA XDA Z axis new data available. Default value: 0 (0: new data for the Z-axis is not yet available; 1: new data for the Z-axis is available) Y axis new data available. Default value: 0 (0: new data for the Y-axis is not yet available;1: new data for the Y-axis is available) X axis new data available. Default value: 0 (0: new data for the X-axis is not yet available; 1: new data for the X-axis is available) 7.10 OUT_X_L (28h), OUT_X_H (29h) X-axis angular rate data. The value is expressed as two’s complement. 7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh) Y-axis angular rate data. The value is expressed as two’s complement. 7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh) Z-axis angular rate data. The value is expressed as two’s complement. 7.13 FIFO_CTRL_REG (2Eh) Table 38. FM2 REFERENCE register FM1 FM0 WTM4 WTM3 WTM2 WTM1 WTM0 36/44 Doc ID 022116 Rev 1 L3GD20 Register description Table 39. FM2-FM0 REFERENCE register description FIFO mode selection. Default value: 00 (see Table 40) FIFO threshold. Watermark level setting WTM4-WTM0 Table 40. FM2 0 0 0 0 1 0 0 1 1 0 FIFO mode configuration FM1 0 1 0 1 0 FM0 Bypass mode FIFO mode Stream mode Stream-to-FIFO mode Bypass-to-Stream mode FIFO mode 7.14 FIFO_SRC_REG (2Fh) Table 41. WTM FIFO_SRC register OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 Table 42. WTM OVRN EMPTY FSS4-FSS1 FIFO_SRC register description Watermark status. (0: FIFO filling is lower than WTM level; 1: FIFO filling is equal or higher than WTM level) Overrun bit status. (0: FIFO is not completely filled; 1:FIFO is completely filled) FIFO empty bit. (0: FIFO not empty; 1: FIFO empty) FIFO stored data level 7.15 INT1_CFG (30h) Table 43. AND/OR INT1_CFG register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Doc ID 022116 Rev 1 37/44 Register description L3GD20 Table 44. AND/OR INT1_CFG description AND/OR combination of interrupt events. Default value: 0 (0: OR combination of interrupt events 1: AND combination of interrupt events Latch interrupt request. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Cleared by reading INT1_SRC reg. Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value lower than preset threshold) LIR ZHIE ZLIE YHIE YLIE XHIE XLIE 7.16 INT1_SRC (31h) Interrupt source register. Read only register. Table 45. 0 INT1_SRC register IA ZH ZL YH YL XH XL Table 46. IA ZH ZL YH YL XH XL INT1_SRC description Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred) Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred) Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) X high. Default value: 0 (0: no interrupt, 1: X High event has occurred) X low. Default value: 0 (0: no interrupt, 1: X Low event has occurred) 38/44 Doc ID 022116 Rev 1 L3GD20 Register description Reading at this address clears INT1_SRC IA bit (and eventually the interrupt signal on the INT1 pin) and allows the refresh of data in the INT1_SRC register if the latched option was chosen. 7.17 INT1_THS_XH (32h) Table 47. - INT1_THS_XH register THSX14 THSX13 THSX12 THSX11 THSX10 THSX9 THSX8 Table 48. INT1_THS_XH description Interrupt threshold. Default value: 0000 0000 THSX14 - THSX9 7.18 INT1_THS_XL (33h) Table 49. THSX7 INT1_THS_XL register THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0 Table 50. INT1_THS_XL description Interrupt threshold. Default value: 0000 0000 THSX7 - THSX0 7.19 INT1_THS_YH (34h) Table 51. - INT1_THS_YH register THSY14 THSY13 THSY12 THSY11 THSY10 THSY9 THSY8 Table 52. INT1_THS_YH description Interrupt threshold. Default value: 0000 0000 THSY14 - THSY9 7.20 INT1_THS_YL (35h) Table 53. THSR7 INT1_THS_YL register THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0 Table 54. INT1_THS_YL description Interrupt threshold. Default value: 0000 0000 THSY7 - THSY0 Doc ID 022116 Rev 1 39/44 Register description L3GD20 7.21 INT1_THS_ZH (36h) Table 55. - INT1_THS_ZH register THSZ14 THSZ13 THSZ12 THSZ11 THSZ10 THSZ9 THSZ8 Table 56. INT1_THS_ZH description Interrupt threshold. Default value: 0000 0000 THSZ14 - THSZ9 7.22 INT1_THS_ZL (37h) Table 57. THSZ7 INT1_THS_ZL register THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0 Table 58. INT1_THS_ZL description Interrupt threshold. Default value: 0000 0000 THSZ7 - THSZ0 7.23 INT1_DURATION (38h) Table 59. WAIT INT1_DURATION register D6 D5 D4 D3 D2 D1 D0 Table 60. WAIT D6 - D0 INT1_DURATION description WAIT enable. Default value: 0 (0: disable; 1: enable) Duration value. Default value: 000 0000 The D6 - D0 bits set the minimum duration of the interrupt event to be recognized. Duration steps and maximum values depend on the ODR chosen. The WAIT bit has the following definitions: Wait = ‘0’: the interrupt falls immediately if the signal crosses the selected threshold Wait = ‘1’: if the signal crosses the selected threshold, the interrupt falls only after the duration has counted the number of samples at the selected data rate, written into the duration counter register. 40/44 Doc ID 022116 Rev 1 L3GD20 Figure 19. Wait disabled Register description Figure 20. Wait enabled Doc ID 022116 Rev 1 41/44 Package information L3GD20 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 21. LGA-16: mechanical data and package dimensions Dimensions Ref. A1 A2 A3 d D1 E1 L2 M N1 N2 P1 P2 T1 T2 k 3.850 3.850 0.785 0.200 0.300 4.000 4.000 1.950 0.100 0.650 0.975 1.750 1.525 0.400 0.300 0.050 mm Min. Typ. Max. 1.000 inch Min. Typ. 0.0309 0.0079 0.0118 4.150 0.1516 0.1575 0.1634 4.150 0.1516 0.1575 0.1634 0.0768 0.0039 0.0256 0.0384 0.0689 0.0600 0.0157 0.0118 0.0020 Max. 0.0394 Outline and mechanical data LGA-16 (4x4x1mm) Land Grid Array Package 8125097_A 42/44 Doc ID 022116 Rev 1 L3GD20 Revision history 9 Revision history Table 61. Date 18-Aug-2011 Document revision history Revision 1 Initial release. Changes Doc ID 022116 Rev 1 43/44 L3GD20 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 44/44 Doc ID 022116 Rev 1