L4902A

L4902A ® DUAL 5V REGULATOR WITH RESET AND DISABLE .. . . . . . .. .. .. DOUBLE BATTERY OPERATING OUTPUT CURRENTS : I01 = 300 mA I02 = 300 mA FIXED PRECISION OUTPUT VOLTAGE 5V± 2% RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING RESET OUTPUT LEVEL RELATED TO OUTPUT 2 OUTPUT 2 INTERNALLY SWITCHED WITH ACTIVE DISCHARGING OUTPUT 2 DISABLE LOGICAL INPUT LOW LEAKAGE CURRENT, LESS THAN 1µA AT OUTPUT 1 RESET OUTPUT NORMALLY HIGH INPUT OVERVOLTAGE PROTECTION UP TO 60V OUTPUT TRANSISTORS SOA PROTECTION SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION ) s ( ct DESCRIPTION c u d e t le ) s t( o r P HEPTAWATT (Vertical) so ORDERING NUMBER : L4902A b O - u d o The L4902A is a monolithic low drop dual 5V regulator designed mainly for supplying microprocessor systems. Reset and data save functions and remote switch on/off control can be realized. r P e t e l o PIN CONNECTION s b O June 2000 1/9 L4902A PIN FUNCTIONS 3 4 5 Name Input 1 Timing Capacitor Disable Input GND Reset Output 6 Output 2 7 Output 1 N° 1 2 Function Regulators Common Input If Reg. 2 is switched-ON the delay capacitor is charged with a 5µA constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged. A high level (> VDT) disable output Reg. 2. Common Ground When pin 2 reaches 5V the reset output is switched high. 5V Therefore tRD = Ct ( ) ; tRD (ms) = Ct (nF) 10µA 5V – 300mA Regulator Output. Enabled if Vo 1 > VRT. DISABLE INPUT < VDT and VIN > VIT. If Reg. 2 is switched-OFF the C02 capacitor is discharged. 5V – 300mA. Low leakage (in switch-OFF condition) output BLOCK DIAGRAM c u d e t le ) s ( ct SCHEMATIC DIAGRAM u d o r P e t e l o s b O 2/9 o s b O - o r P ) s t( L4902A ABSOLUTE MAXIMUM RATINGS Symbol VIN Parameter Value Unit 28 60 V V DC Input Voltage Transient Input Overvoltage (t = 40ms) Output Current Io Tstg, Tj Internally Limited Storage and Junction Temperature – 40 to 150 °C Value Unit 4 °C/W THERMAL DATA Symbol Rth j-case Parameter Thermal Resistance Junction-case Max ELECTRICAL CHARACTERISTICS (VIN = 14.4V, Tamb = 25oC unless otherwise specified)) Symbol Vi V01 V02 H V02 L I01 IL01 Parameter DC Operating Input Voltage Output Voltage 1 Test Conditions Output Voltage 2 LOW Output Current 1 max. ∆V02 = – 100mV I01 = 10mA I01 = 100mA I01 = 300mA 300 c u d 0.1 300 ) s t( V V mA 50 5 40 50 80 mV mV 5mA < I02 < 300mA 50 80 mV I01 = I02 ≤ 5mA 0 < VIN < 13V 7V < VIN < 13V V02 LOW 7V < VIN < 13V V02 HIGH 4.5 2.7 1.6 6.5 4.5 3.5 4.9 50 4.12 0.25 5 V02 – 0.05 80 V02 0.4 11 20 2.4 VD ≤ 0.4V VD ≥ 2.4V 1.25 – 150 – 30 Thermal Drift – 20°C ≤ Tamb ≤ 125°C 0.3 – 0.8 mV/°C Thermal Drift – 20°C ≤ Tamb ≤ 125°C 0.3 – 0.8 mV/°C Supply Voltage Rejection f = 100Hz VR = 0.5V Io = 100mA 50 84 dB 50 80 dB Line Regulation 2 Load Regulation 1 ∆V02 IQ Load Regulation 2 Quiescent Current Reset Threshold Voltage Reset Threshold Hysteresis Reset Output Voltage HIGH Reset Output Voltage LOW Reset Pulse Delay Timing Capacitor Discharge Time r P e t e l o V02 Disable Threshold Voltage V02 Disable Input Current Supply Voltage Rejection (s) ct u d o SVR2 V01 7V < VIN < 24V, I02 = 5mA 5mA < I01 < 300mA ∆V02 ∆V01 ∆V02 ∆T SVR1 5 7V < VIN < 24V, I01 = 5mA Input Threshold Voltage Input Threshold Voltage Hyst. Line Regulation 1 ∆V01 ∆T V01 –0.1 0.8 1 1.4 V01 + 1.7 VIT ViTH ∆V01 s b O 5.05 R Load 1kΩ I02 = – 5mA ∆V01 = – 100mV VIN = 0, V01 ≤ 3V Unit V V 0.7 0.8 1.1 6.4 250 5 Leakage Output 1 Current Output Current 2 max. Output 1 Dropout Voltage (*) VDT ID Typ. µA mA V V V V mV mV I02 Vi01 VRT VRTH VRH VRL tRD td 4.95 Max. 24 5.15 R Load 1kΩ Output Voltage 2 HIGH Min. e t le o s b O - IR = 500µA IR = – 1mA Ct = 10nF Ct = 10nF o r P V01 + 1.2 1 mA V02 – 0.15 30 V02 – 1 3 V mV V V ms µs V µA µA * The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25 mV under constant output current condition. 3/9 L4902A TEST CIRCUIT APPLICATION INFORMATION In power supplies for µP systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to save data when the primary supply is removed. The L4902A makes it very easy to supply such equipments ; it provides two voltage regulators (both 5V high precision) with common inputs plus a reset output for the data save function and a Reg. 2 disable input. CIRCUIT OPERATION (see Figure 1) ) s ( ct u d o r P e t e l o s b O 4/9 c u d e t le o s b O - After switch on Reg. 1 saturates until V01 rises to the nominal value. When the input reaches VIT and the output 1 is higher than VRT the output 2 (V02) switches on and the reset output (VR) also goes high after a proFigure 1 grammable time TRD (timing capacitor). V02 and VR are switched together at low level when one of the following conditions occurs : - a high level ( VDT) is applied on pin 3 ; - an input overvoltage ; - an overload on the output 1 (V01 VRT) ; - a switch off (VIN VIT - VITH) ; and they start again as before when the condition is removed. An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The V01 output features : - 5V internal reference without voltage divider between the output and the error comparator - very low drop series regulator element utilizing current mirrors permit high output impedance and then very low leakage current even in power down condition. o r P ) s t( L4902A This output may therefore be used to supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. The V02 output can supply other non essential 5 V circuits which may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value. The reset output can be used as a "POWER DOWN INTERRUPT", permitting RAM access only in correct power conditions, or as a "BACK-UP ENABLE" to transfer data into in a NV SHADOW MEMORY when the supply is interrupted. The disable function can be used for remote on/off control of circuits connected to the V02 output. APPLICATION SUGGESTIONS Figure 2 illustrate how the L4902A’s disable input may be used in a CMOS µComputer application. The V01 regulator (low consumption) supply permanently a CMOS time of day clock and a CMOS µcomputer chip with volatile memory. V02 output, supplying non-essential circuits, is turned OFF under control of a µP unit. Figure 2 c u d e t le ) s ( ct ) s t( o r P o s b O - Figure 3 : P.C. Board Component Layout of Figure 2 u d o r P e t e l o s b O 5/9 L4902A Configurations of this type are used in products where the OFF switch is part of a keyboard scanned by a micro which operates continuously even in the OFF state. Another application for the L4902A is supplying a shadow-ram microcomputer chip (SGS M38SH72 for example) where a fast NV memory is backed up on chip by a EEPROM when a low level on the reset output occurs. By adding two CMOS-SCHMIDT-TRIGGER and few external components, also a watch dog func- tion may be realized (see Figure 5). During normal operation the microsystem supplies a periodical pulse waveform ; if an anomalous condition occours (in the program or in the system), the pulses will be absent and the disable input will be activated after a settling time determined by R1 C1. In this condition all the circuitry connected to V02 will be disabled, the system will be restarted with a new reset front. The disable of V02 prevent spurious operation during microprocessor malfunctioning. Figure 4 c u d e t le Figure 5 ) s ( ct u d o r P e t e l o s b O 6/9 o s b O - o r P ) s t( L4902A Figure 6 : Figure 8 : Figure 7 : Quiescent Current versus Output ICurrent Quiescent Current versus Input Voltage Supply Voltage Rejection Regulators 1 and 2 versus Input Ripple Frequence c u d ) s ( ct e t le ) s t( o r P o s b O - u d o r P e t e l o s b O 7/9 L4902A DIM. A C D D1 E E1 F F1 G G1 G2 H2 H3 L L1 L2 L3 L4 L5 L6 L7 L9 M M1 V4 Dia MIN. mm TYP. 2.4 1.2 0.35 0.7 0.6 2.34 4.88 7.42 10.05 16.7 21.24 22.27 2.6 15.1 6 2.55 4.83 2.54 5.08 7.62 16.9 14.92 21.54 22.52 2.8 15.5 6.35 0.2 2.8 5.08 3.65 MAX. 4.8 1.37 2.8 1.35 0.55 0.97 0.8 0.9 2.74 5.28 7.82 10.4 10.4 17.1 21.84 22.77 1.29 3 15.8 6.6 inch TYP. MIN. 0.094 0.047 0.014 0.028 0.024 0.095 0.193 0.295 0.100 0.200 0.300 0.396 0.657 0.668 0.587 0.848 0.891 0.386 0.877 0.102 0.594 0.236 0.110 0.610 0.250 0.008 0.110 0.200 3.05 0.100 5.33 0.190 40˚ (typ.) 3.85 0.144 0.860 0.896 0.051 0.118 0.622 0.260 ) s ( ct u d o t e l o r P e bs O H3 o r P e t le o s b O - V V E M1 M D D1 L5 H2 L2 L3 F E E1 V4 L9 G H1 G1 G2 Dia. F L4 L7 L6 8/9 ) s t( Heptawatt V 0.152 L1 C c u d 0.120 0.210 L A OUTLINE AND MECHANICAL DATA MAX. 0.189 0.054 0.110 0.053 0.022 0.038 0.031 0.035 0.105 0.205 0.307 0.409 0.409 0.673 H2 F1 HEPTAMEC L4902A c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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