L4938N

® L4938N/ND L4938NPD DUAL MULTIFUNCTION VOLTAGE REGULATOR . . . . . . . . . . . . STANDBYOUTPUT VOLTAGEPRECISION 5V ± 2% OUTPUT 2 TRACKED TO THE STANDBY OUTPUT OUTPUT 2 DISABLE FUNCTION FOR STANDBY MODE VERY LOW QUIESCENT CURRENT, LESS THAN 250µA, IN STANDBY MODE OUTPUT 2 VOLTAGE SETTABLE FROM 5 TO 20V OUTPUT CURRENTS : I01 = 50mA, I02 = 500mA VERY LOW DROPOUT (max 0.4V/0.6V) OPERATING TRANSIENT SUPPLY VOLTAGE UP TO 40V POWER-ON RESET CIRCUIT SENSING THE STANDBY OUTPUT VOLTAGE POWER-ON RESET DELAY PULSE DEFINED BY THE EXTERNAL CAPACITOR EARLY WARNING OUTPUT FOR SUPPLY UNDERVOLTAGE THERMAL SHUTDOWN AND SHORTCIRCUIT PROTECTIONS PowerDIP (12+2+2) SO20 (12+4+4) PowerSO20 ORDERING NUMBERS: L4938N (PDIP) L4938ND (SO) L4938NPD (PSO20) DESCRIPTION The L4938N is a monolithic integrated dual voltage regulatorswith two very low dropout outputsand additional functions such as power-on reset and input voltage sense. They are designedfor supplying microcomputer controlled systems specially in automotive applications. PIN CONNECTION (top view) POWERDIP SO20 PowerSO20 N.C. 1 2 3 4 5 6 7 8 9 10 D93AT004 20 19 18 17 16 15 14 13 12 11 SI VS1 VS2 GND GND GND GND VO2 VO2 ADJ N.C. CT EN GND GND RES SO VO1 1 2 3 4 5 6 7 8 D95AT156 16 15 14 13 12 11 10 9 SI VS1 VS2 GND GND VO2 VO2 ADJ GND N.C. VS2 VS1 SI N.C. CT EN N.C. GND 1 2 3 4 5 6 7 8 9 10 D95AT169A 20 19 18 17 16 15 14 13 12 11 GND N.C. VO2 ADJ VO1 SO RESET N.C. N.C. GND C7 EN GND GND GND GND RES SO VO1 April 1999 1/12 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L4938N - L4938ND - L4938NPD B LOCK DIAGRAM VS1 VO1 REFERENCE 1.23V REG1 VO2 VS2 EN REG2 ADJ 1.23V 2µ CT RES RESET 2.0V SI SENSE (optional) 1.23V SO GND D94AT143A THERMAL DATA Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-Case Thermal Resistance Junction-Ambient Max. Max. Powerdip 14 90 PowerSO20 VS) Enable Input Current (VEN ≤0.3V) Enable Input Voltage Reset and Sense Output Voltage Reset and Sense Output Current Power Dissipation Parameter Value 28 40 –55 to 150 ±1 ±1 VS 20 5 875 V mA mW Unit V V °C mA mA Note : The circuit is ESD protected according to MIL–STD–883C. APPLICATION CIRCUIT VS1 CS V O1 CO1 REFERENCE 1.23V REG1 V O2 VS2 EN REG2 ADJ CO2 1.23V 2µ CT RES CT RRES RESET SI 2.0V RSO SO SENSE (optional) 1.23V GND VO1 D94AT144A CS ≥ 1µF ; C01 ≥ 6µF ; C02 ≥ 10µF, ESR < 10Ω at 10KHz 3/12 L4938N - L4938ND - L4938NPD ELECTRICAL CHARACTERISTICS (VS = 14V; –40°C ≤ TJ ≤ 125°C unless otherwise specified) Symbol VS V O1 VO2 - VO1 Parameter Operating Supply Voltage Standby Output Voltage Output Voltage 2 Tracking Error (note 1) ADJ Input Current Dropout Voltage 1 Input to Output Voltage Difference in Undervoltage Condition Dropout Voltage 2 Input to Output Voltage Difference in Undervoltage Condition Line Regulation Load Regulation 1 Load Regulation 2 Current Limit 1 Current Limit 2 6V ≤ VS ≤ 25V 1mA ≤ IO1 ≤ 50mA 6V ≤ VS ≤ 25V 5mA ≤ IO2 ≤ 500mA Enable = LOW IO1 = 1mA; IO2 = 5mA IO1 = 10mA IO1 = 50mA VS = 4V, I O1 = 35mA 4.90 –25 5.00 Test Conditions Min. Typ. Max. 25 5.10 +25 Unit V V mV IADJ VDP1 V IO1 –1 0.1 0.1 0.2 1 0.25 0.4 0.4 µA V V V VDP2 V IO2 IO1 = 100mA IO1 = 500mA VS = 4.6V, IO1 = 350mA 0.2 0.3 0.3 0.6 0.6 V V V VOL 1.2 VOLO1 VOLO2 ILIM1 ILIM2 IQSB 6V ≤ VS ≤ 25V IO1 = 1mA; IO2 = 5mA 1mA ≤ IO1 ≤ 50mA 5mA ≤ IO2 ≤ 500mA VO1 = 4.5V VO1 = 0V (note 2) VO2 = 0V 55 25 550 100 50 1000 20 25 50 200 100 1700 mV mV mV mA mA mA Quiescent Current Standby Mode IO1 = 0.3mA; T J < 100°C (output 2 disabled) VEN ≥ 2.4V VS = 14V VS = 3.5V Quiescent Current IO1 = 50mA IO1 = 500mA 210 340 290 850 30 µA µA mA IQ ENABLE VENL VENH VENhyst IEN Enable Input LOW Voltage (output 2 active) Enable Input HIGH Voltage Enable Hysteresis Enable Input Current 0V < VEN < 1.2V 2.5V < VEN < 7V –0.3 2.4 30 –10 –1 75 –1.5 0 1.5 7 200 –0.5 +1 V V mV µA µA 4/12 L4938N - L4938ND - L4938NPD ELECTRICAL CHARACTERISTICS (continued) RESET Symbol VRt VRth tRD tRR VRL ILRES VCTh VCTh, hyst Parameter Reset Low Threshold Voltage Reset Threshold Hysteresis Reset Pulse Delay Reset Reaction Time Reset Output LOW Voltage Reset Output HIGH Leakage Delay Comparator Threshold Delay Comparator Threshold Hysteresis CT = 100nF; tR > 100µs CT = 100nF RRES = 10KΩ to V01 VS = 1.5V VRES = 5V 2.0 100 Test Conditions Min. Vo1 -0.4 50 55 1 Typ. 4.7 100 100 10 Max. Vo1 -0.1 200 180 50 0.4 1 Unit V mV mV µs V µA V mV SENSE VSlth VSlth, hyst VSOL ILSO Sense Threshold Voltage Sense Threshold Hysteresis Sense Output LOW Voltage Sense Output Leakage VSI = 1,16V; V S ≥ 3V RSO = 10KΩ to V01 VSO = 5V; VSI ≥ 1.5V 1.16 40 1.23 100 1.35 200 0.4 1 V mV V µA Note : 1 : VO2 connected to ADJ.VO2 can be set to higher values by inserting an external resistor divider. 2 : Foldback characteristic FUNCTIONAL DESCRIPTION The L4938N is based on the STMicroelectronics modular voltage regulator approach. Several outstanding features and auxiliary functions are provided to meet the requirements of supplying the microprocessor systems used in automotive applications. Furthermore the device is suitable also in other applications requiring two stabilized voltages. The modular approach allows other features and functions to be realized easily when required. STANDBY REGULATOR The standby regulator uses an Isolated Collector Vertical PNP transistor as the regulating element. This structure allows a very low dropout voltage at currents up to 50mA. The dropout operation of the standby regulator is maintained down to 2V input supply voltage. The output voltage is regulated up to the transientinput supplyvoltageof 40V.This feature avoids functional interruptions which could be generated by overvoltage pulses. The typical curve of the standby output voltage as a functionof theinput supply voltage is shown in fig. 1. The current consumption of the device (quiescent current) is less than 250µA when output 2 is disabled (standby mode). The dropout voltage is controlled to reduce the quiescent current peak in the undervoltage region and to improve the transient response in this region. The quiescentcurrent isshown in fig. 2 as a function of the supply input voltage 2. OUTPUT 2 VOLTAGE The output 2 regulator uses the same output structure as the standbyregulator, but rated for anoutput current of 500mA. The output 2 regulatorworks in tracking mode with the standby output voltage as a reference voltage when the output 2 programming pin ADJ is connected to VO2. By connecting a resistor divider R1, R2 to the pin ADJ as shown in fig. 3, the output voltage 2 can be programmed to the value : VO2 = VO1 (1 + R1/R2) The output 2 regulator can be switched off via the Enable input. If a fixed 5 regulation is required ADJ Pin has to be connectedto V02 Pin. 5/12 L4938N - L4938ND - L4938NPD Figure 1 : Output Voltage vs. Input Voltage. Figure 2 : QuiescentCurrent vs. Supply Voltage. 400µ 200µ Figure 3 : Programmable Output 2 Voltage with External Resistors. 6/12 L4938N - L4938ND - L4938NPD RESET CIRCUIT Theblockcircuit diagramof theresetcircuit isshown in fig.4. The resetcircuit supervisesthe standbyoutput voltage. The reset threshold of 4.7V is defined by the internal reference voltage and the standby output divider. The reset pulse delay time tRD, is defined by the charge time of an external capacitor CT : CT x 2V tRD = 2µA occurs. The nominal reset delay is generated for standby output voltage drops longer than the time necessary for the complete discharging of the capacitor CT. This time is typically equal to 50µs if CT = 100nF.The typical reset outputwaveformsare shown in fig. 5. SENSE COMPARATOR This circuit comparesan input signal withan internal voltage reference of typically 1.23V. The use of an externalvoltage divider makes the comparatorvery flexible in the application. This function can be used to supervisethe input voltage - eitherbefore or after the protectiondiode - and togive additionalinformationtothe microprocessorsuch aslow voltagewarnings. If this feature is not used SI and SO have to connected to GND. In this case the St-by quiescent current (14V) increases from 290µA to 300µA. Thereaction time of the reset circuit dependson the discharge time limitation of the reset capacitor CT and is proportional to the value of CT. The reaction time of the reset circuit increases the noise immunity. In fact,if the standbyoutputvoltage drops below the reset threshold for a time shorter than the reaction time tRR, no reset output variation Figure 4: Block Diagram of the Reset Circuit. 7/12 L4938N - L4938ND - L4938NPD Figure 5 : Typical Reset Output Waveforms. 1.5V 8/12 L4938N - L4938ND - L4938NPD DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.38 0.51 0.85 mm TYP. MAX. MIN. 0.020 1.40 0.50 0.50 20.0 8.80 2.54 17.78 7.10 5.10 3.30 1.27 0.015 0.033 inch TYP. MAX. OUTLINE AND MECHANICAL DATA 0.055 0.020 0.020 0.787 0.346 0.100 0.700 0.280 0.201 0.130 0.050 Powerdip 16 9/12 L4938N - L4938ND - L4938NPD DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T mm TYP. inch TYP. MIN. 0.1 0 0.4 0.23 15.8 9.4 13.9 MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 MIN. 0.004 0.000 0.016 0.009 0.622 0.370 0.547 MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570 OUTLINE AND MECHANICAL DATA 1.27 11.43 10.9 5.8 0 15.5 0.8 11.1 0.429 2.9 6.2 0.228 0.1 0.000 15.9 0.610 1.1 1.1 0.031 10° (max.) 8° (max.) 10 0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.394 (1) ”D and F” do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006”). - Critical dimensions: ”E”, ”G” and ”a3” PowerSO20 N N a2 b e A R c DETAIL B a1 E DETAIL A DETAIL A e3 H lead D a3 DETAIL B 20 11 Gage Plane 0.35 slug - C- S E2 T E1 BOTTOM VIEW L SEATING PLANE G C (COPLANARITY) E3 1 10 h x 45 PSO20MEC D1 10/12 L4938N - L4938ND - L4938NPD DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 mm TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 1.27 10.65 0.75 1.27 0.394 0.010 0.016 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050 OUTLINE AND MECHANICAL DATA 0° (min.)8° (max.) SO20 L h x 45° A B e K H D A1 C 20 11 E 1 1 0 SO20MEC 11/12 L4938N - L4938ND - L4938NPD Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 12/12