L4949ED013TR

L4949E Multifunction very low drop voltage regulator Features ■ Operating DC supply voltage range 5 V - 28 V ■ Transient supply voltage up to 40V ■ Extremely low quiescent current in standby mode ■ High precision standby output voltage 5V±1% ■ Output current capability up to 100mA ■ Very low dropout voltage less than 0.5V ■ Reset circuit sensing the output voltage ■ Programmable reset pulse delay with external capacitor ■ Voltage sense comparator ■ Thermal shutdown and short circuit protections ) (s Description ) s ( ct SO-8 SO-20W (12+4+4) u d o r P e t e l o s b O t c u The L4949E is a monolithic integrated 5V voltage regulator with a very low dropout output and additional functions as power-on reset and input voltage sense. It is designed for supplying the microcomputer controlled systems especially in automotive applications. d o r P e t e l o s b O Table 1. Device summary Order codes Package November 2009 Tube Tape and reel SO-8 L4949ED L4949ED013TR SO-20W L4949EP L4949EP013TR Doc ID 4275 Rev 6 1/19 www.st.com 1 Contents L4949E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ) s ( ct 4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 u d o 3.1 Supply voltage transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Preregulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Sense comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 r P e t e l o ) (s s b O 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 SO-8 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 SO-20 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 t c u d o r P e Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 t e l o s b O 2/19 Doc ID 4275 Rev 6 L4949E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Preregulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SO-8 TP mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO-20 TP mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 4275 Rev 6 3/19 List of figures L4949E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Foldback characteristic of VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output voltage vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Quiescent current vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block circuit of reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SO-8 TP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SO20 TP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 4/19 Doc ID 4275 Rev 6 L4949E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram ) s ( ct u d o r P e t e l o ) (s s b O Note: The block diagram illustrates only a major internal device functionality and it is not intended to mimic any details of hardware design Figure 2. Configuration diagram (top view) t c u d o r P e t e l o s b O SO-8 SO-20 Doc ID 4275 Rev 6 5/19 Block diagram and pin description Table 2. L4949E Pin definitions and functions Pin N° Symbol Function SO-8 SO-20 1 19 VS Input supply voltage. Block to GND via an external capacitor (see Figure 3). 2 20 SI Sense input pin to supervise input voltage. Connect via an external voltage divider connected to VS and to GND. 3 1 VZ Preregulator output voltage. For details, see Section 3.4: Preregulator. 4 2 CT Reset pulse delay adjustment. Connecting this pin via a capacitor to GND 5 4, 5, 6, 7, 14, 15, 16, 17 GND Ground reference 6 10 RES Reset output. It is pulled down when the output voltage goes below VRT. 7 11 u d o r P e SO Sense output. This open collector pin must be connected to VOUT via an external resistor. It is pulled down whenever the SI voltage becomes lower than an internal voltage. Output voltage. Block to GND via an external capacitor (see Figure 3) 8 12 VOUT - 3, 8, 9, 13, 18 NC ) (s t e l o s b O Not connected pins t c u d o r P e t e l o s b O 6/19 ) s ( ct Doc ID 4275 Rev 6 L4949E Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Table 3. Absolute maximum ratings(1) Symbol Parameter Value Unit VSDC DC operating supply voltage 28 V VSTR Transient supply voltage (T < 1s) 40 V IO Output current Internally limited VO Output voltage 20 VRES, VSO Output voltage 20 IRES, ISO VCT Reset delay voltage VSIDC Sense input voltage 5 ro VZ Preregulator output voltage IZ Preregulator output current TJ Junction temperature Tstg Storage temperature range P e t e l o bs O ) V ct du Output current (s) V mA 7 V 28 V 7 V 5 mA -40 to +150 °C -55 to +150 °C 1. The circuit is ESD protected according to MIL-STD-883C. 2.2 Thermal data Table 4. u d o Thermal data r P e Symbol t e l o bs s ( t c Description Rth j-amb Thermal Resistance Junction-ambient (max) Rth j-pins Thermal Resistance Junction-pins (max) TJSD Thermal Shutdown Junction temperature SO-8 SO20L Unit 200 50 °C/W 15 °C/W 165 °C O Doc ID 4275 Rev 6 7/19 Electrical specifications 2.3 L4949E Electrical characteristics VS = 14 V; -40 °C < Tj < 125 °C unless otherwise specified Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit VO Output voltage TJ = 25 °C; IO = 1 mA 4.95 5 5.05 V VO Output voltage 6 V < VIN < 28 V, 1 mA < IO < 50 mA 4.90 5 5.10 V VO Output voltage VIN = 40 V; T < 1 s; 5 mA < IO < 100 mA 4.75 5.25 V VDP Dropout voltage IO = 10 mA IO = 50 mA IO = 100 mA 0.25 0.4 0.5 V V V VIO Input to output voltage difference in undervoltage VIN = 4 V, IO = 35 mA condition 0.4 V 80 µA 20 mV 30 mV 400 400 mA mA mA 300 µA 5 mA Max. Unit Iouth(1) 0.1 0.2 0.3 Max output leakage VIN = 25 V, VO = 5.5 V VOL Line regulation 6 V < VIN < 28 V; IO = 1 mA VOLO Load regulation 1 mA < IO < 100 mA Current limit VO = 4.5 V VO = 4.5 V; TJ = 25 °C VO = 0 V(2) ILIM r P e 20 t e l o bs IQSE Quiescent current IQ Quiescent current 105 120 -O 50 200 100 IO = 0.3 mA; TJ < 100 °C ) s ( ct u d o ) s ( ct 200 IO = 100 mA 1. With this test we guarantee that with no output current the output voltage will not exceed 5.5V 2. u d o Foldback characteristic Table 6. r P e Reset let Symbol Parameter Test condition Reset threshold hysteresis tRD Reset pulse delay CT = 100 nF; TR ≥ 100 µs VRL Reset output low voltage RRES = 10 KΩ to VO VS ≥ 1.5V IRH Reset output high leakage current VRES = 5 V b O VRTH Typ. VO 0.5V so VRT Min. Reset threshold voltage V 50 100 200 mV 55 100 180 ms 0.4 V 1 µA VCTth Delay comparator threshold 2 V VCTth, hy Delay comparator threshold hysteresis 100 mV 8/19 Doc ID 4275 Rev 6 L4949E Table 7. Electrical specifications Sense Symbol Parameter Test condition Min. Typ. Max. Unit 1.16 1.23 1.35 V 20 100 200 mV Vst Sense low threshold Vsth Sense threshold hysteresis VSL Sense output low voltage VSI ≤ 1.16 V; VS ≥ 3 V RSO = 10 KΩ to VO 0.4 V ISH Sense output leakage VSO = 5 V; VSI ≥ 1.5 V 1 µA ISI Sense input current VSI = 0 -3 µA Table 8. -20 -8 Min. Typ. ) s ( ct Preregulator Symbol Parameter VZ Preregulator output voltage IZ Preregulator output current Test condition IZ = 10 µA du 4.5 5 ro P e Max. Unit 6 V 10 µA t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 4275 Rev 6 9/19 Application information L4949E 3 Application information Figure 3. Application circuit(1) ) s ( ct u d o r P e t e l o ) (s s b O t c u 1. For stability: CS ≥ 1µF, CO ≥ 4.7µF, ESR < 10Ω at 10KHz Recommended for application: CS = CO = 10 µF to 100 µF 3.1 d o r P e Supply voltage transient s b O t e l o High supply voltage transients can cause a reset output signal disturbance. For supply voltages greater than 8V the circuit shows a high immunity of the reset output against supply transients of more than 100V/µs. For supply voltages less than 8V supply transients of more than 0.4V/µs can cause a reset signal disturbance. To improve the transient behaviour for supply voltages less than 8V a capacitor at pin VZ can be used. This capacitor (C3 ≤ 1 µF) reduces also the output noise. 3.2 Functional description The L4949E is a monolithic integrated voltage regulator, based on the STM modular voltage regulator approach. Several outstanding features and auxiliary functions are implemented to meet the requirements of supplying microprocessor systems in automotive applications. Nevertheless, it is suitable also in other applications where the present functions are 10/19 Doc ID 4275 Rev 6 L4949E Application information required. The modular approach of this device allows to get easily also other features and functions when required. 3.3 Voltage regulator The voltage regulator uses an Isolated Collector Vertical PNP transistor as a regulating element. Figure 4. Foldback characteristic of VO ) s ( ct u d o r P e t e l o ) (s s b O t c u With this structure very low dropout voltage at currents up to 100mA is obtained. The dropout operation of the standby regulator is maintained down to 3V input supply voltage. The output voltage is regulated up to the transient input supply voltage of 40V. With this feature no functional interruption due to overvoltage pulses is generated. The typical curve showing the standby output voltage as a function of the input supply voltage is shown in Figure 5. The current consumption of the device (quiescent current) is less than 300 µA. d o r P e s b O t e l o To reduce the quiescent current peak in the undervoltage region and to improve the transient response in this region, the dropout voltage is controlled, the quiescent current as a function of the supply input voltage is shown in Figure 6. Doc ID 4275 Rev 6 11/19 Application information Figure 5. L4949E Output voltage vs input voltage ) s ( ct u d o r P e t e l o Figure 6. Quiescent current vs supply voltage ) (s s b O t c u d o r P e t e l o s b O 3.4 Preregulator To improve the transient immunity a preregulator stabilizes the internal supply voltage to 5 V. This internal voltage is present at Pin 3 (VZ). This voltage should not be used as an output because the output capability is very small (≤ 10 µA). This output may be used as an option when a better transient behaviour for supply voltages less than 8 V is required (see also application note). In this case a capacitor (100 nF - 1 µF) must be connected between pin VZ and GND. If this feature is not used pin VZ must be left open. 12/19 Doc ID 4275 Rev 6 L4949E 3.5 Application information Reset circuit The block circuit diagram of the reset circuit is shown in Figure 7. The reset circuit supervises the output voltage. The reset threshold of 4.5 V is defined with the internal reference voltage and standby output drivider. The reset pulse delay time tRD, is defined with the charge time of an external capacitor CT: C T • 2V t RD = -------------------2μA The reaction time of the reset circuit originates from the discharge time limitation of the reset capacitor CT and is proportional to the value of CT. ) s ( ct The reaction time of the reset circuit increases the noise immunity. Standby output voltage drops below the reset threshold only a bit longer than the reaction time results in a shorter reset delay time. u d o The nominal reset delay time is generated for standby output voltage drops longer than approximately 50ms. r P e The typical reset output waveforms are shown in Figure 8. 3.6 t e l o Sense comparator s b O The sense comparator compares an input signal with an internal voltage reference of typical 1.23V. The use of an external voltage divider makes this comparator very flexible in the application. ) (s t c u It can be used to supervise the input voltage either before or after the protection diode and to give additional informations to the microprocessor like low voltage warnings. d o r Figure 7. Block circuit of reset circuit P e t e l o s b O Doc ID 4275 Rev 6 13/19 Application information Figure 8. L4949E Waveforms ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 14/19 Doc ID 4275 Rev 6 L4949E Package and packing information 4 Package and packing information 4.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.2 SO-8 TP package information Table 9. u d o mm Dim. Min. Typ. r P e A a1 a3 t(s C uc c1 D(1) O o s b od Pr Max. 1.75 0.25 1.65 0.85 O ) 0.35 b1 e o s b 0.65 b E let 0.1 a2 e t e l ) s ( ct SO-8 TP mechanical data 0.48 0.19 0.25 0.25 0.5 45° (typ.) 4.8 5.0 5.8 6.2 1.27 e3 3.81 (1) 3.8 4.0 L 0.4 1.27 F M 0.6 S 8° (max.) 1. D and F do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm (.006inch). Doc ID 4275 Rev 6 15/19 Package and packing information Figure 9. L4949E SO-8 TP package dimensions ) s ( ct u d o r P e t e l o 4.3 ) (s t c u SO-20 TP package information d o r Table 10. SO-20 TP mechanical data P e t e l o bs O s b O mm Dim. Min. Max. A 2.35 2.65 A1 0.1 0.3 B 0.33 0.51 C 0.23 0.32 D 12.6 13 E 7.4 7.6 e H 16/19 Typ. 1.27 10 Doc ID 4275 Rev 6 10.65 L4949E Package and packing information Table 10. SO-20 TP mechanical data (continued) mm Dim. Min. Typ. Max. h 0.25 0.75 L 0.4 1.27 K 0 (min.)8 (max.) ) s ( ct Figure 10. SO20 TP package dimensions u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 4275 Rev 6 17/19 Revision history 5 L4949E Revision history Table 11. Document revision history Date Revision 01-Jun-2000 1 Initial release. 6 Reformatted entire document. Removed Minidip package. Added Table 2: Pin definitions and functions. Updated Table 3: Absolute maximum ratings Updated Figure 1: Block diagram and Figure 3: Application circuit(1) 25-Nov-2009 Description of changes ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 18/19 Doc ID 4275 Rev 6 L4949E ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. r P e All ST products are sold pursuant to ST’s terms and conditions of sale. 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All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 4275 Rev 6 19/19