L5150GJTR

L5150GJ Automotive 5 V low dropout voltage regulator Datasheet - production data  Early warning  Very wide stability range with low value output capacitor  Thermal shutdown and short-circuit protection  Wide temperature range (Tj = -40 °C to 150 °C) PowerSSO-12 GAPGP01380 Features  Enable input for enabling / disabling the voltage regulator Description Max DC supply voltage VS 40 V Max output voltage tolerance ΔVo ±2% Max dropout voltage Vdp 500 mV Output current Io 150 mA Quiescent current Iqn 5 µA(1) 55 µA(2) L5150GJ is a low dropout linear regulator with microprocessor control functions such as power on reset, low voltage reset, early warning, on/off control. Typical quiescent current is 55 µA in very low output current mode and enabled regulator. It drops to 5 µA with not enabled regulator. On chip trimming results in high output voltage accuracy (+/-2%). Accuracy is kept over wide temperature range, line and load variation. Early warning circuit monitors the input voltage and compares it with an internal voltage reference. 1. Typical value with regulator disabled. 2. Typical value with regulator enabled.  AEC-Q100 qualified  Operating DC supply voltage range 5.6 V to 40 V Output voltage reset threshold can be adjusted down to 3.5 V by means of an external voltage divider.  Low dropout voltage  Low quiescent current consumption  Precision output voltage 5 V ± 2%  Reset circuit sensing the output voltage  Programmable reset pulse delay with external capacitor The maximum input voltage is 40 V. The max output current is internally limited. Internal temperature protection disables the voltage regulator output. In addition, only low-value ceramic capacitor on output is required for stability.  Adjustable reset threshold Table 1. Device summary Order codes Package PowerSSO-12 July 2021 This is information on a product in full production. Tube Tape & reel L5150GJ L5150GJTR DS6182 Rev 15 1/29 www.st.com Contents L5150GJ Contents 1 Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 5 6 2/29 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 PowerSSO-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DS6182 Rev 15 L5150GJ List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Early warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PowerSSO-12 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PowerSSO-12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DS6182 Rev 15 3/29 3 List of figures L5150GJ List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. 4/29 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Output voltage vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output voltage vs. VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output voltage vs. VEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Drop voltage vs. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current consumption vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current consumption vs. output current (at light load condition). . . . . . . . . . . . . . . . . . . . . 11 Current consumption vs. input voltage (Io = 0.1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current consumption vs. input voltage (Io = 75 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current limitation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Current limitation vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Short-circuit current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Short-circuit current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VEn_high vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VEn_low vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VRhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VRlth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VEWi_thh vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VEWi_thl vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Icr vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Idr vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Stability region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Early warning time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 20 PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 21 Thermal fitting model of Vreg in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PowerSSO-12 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DS6182 Rev 15 L5150GJ 1 Block diagram and pins description Block diagram and pins description Figure 1. Block diagram Vo Vs START - UP Reset Ad j ust able Thr eshol d Pow er En VOLTAGE Res-Adj Dr iv er REFERENCE Ther m al Curr ent Shut dow n lim it er Res Low Voltage Reset Vcr EWo EWi GND GAPGPS01381 Figure 2. Configuration diagram (top view) TAB = Substrate 12 11 10 9 8 7 1 2 3 4 5 6 GAPGPS01382 DS6182 Rev 15 5/29 28 Block diagram and pins description L5150GJ Table 2. Pins description 6/29 Pin Name Function 1 Res_Adj Reset adjustable threshold. Connected to an appropriate external voltage divider, it allows to properly set the reset threshold down to 3.5 V. Connect to GND if not needed. 2 Res Reset output. Internally connected to Vo through a 20 K pull-up resistor. This pin is pulled low when Vo < Vo_th. Keep open if not needed. 3 Vcr Reset delay. Connect an external capacitor between Vcr pin and ground to adjust the reset delay time. Keep open if not needed. 4 GND 5 NC Not connected. 6 Vo 5 V regulated output. Block to GND with a ceramic capacitor (Co  220 nF for regulator stability). 7 VS Supply voltage, block directly to GND on the IC with a capacitor. 8 NC Not connected. 9 En Enable input. A high signal switches the regulator on. Connect to VS if not needed. 10 EWi Early warning input. This pin monitors the VS voltage level through a resistor divider. Connect to VS if not needed. 11 NC Not connected. 12 EWo Early warning output. Internally connected to Vo through 20 K pull up resistor. This pin is pulled low when EWi is below bandgap reference voltage. Keep open if not needed. - TAB TAB is connected to the substrate of the chip: connect to GND or leave open (see Figure 2). Ground reference. DS6182 Rev 15 L5150GJ Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in the Table 3: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Value Unit -0.3 to 40 V Vsdc DC supply voltage Isdc Input current Vodc DC output voltage -0.3 to 6 Iodc DC output current Internally limited Vod Res Open drain output voltage Res -0.3 to Vodc + 0.3 Iod Res Open drain output current Res Internally limited VRes_adj VRes_adj voltage -0.3 to Vodc + 0.3 V Vod EWo Open drain output voltage EWo -0.3 to Vodc + 0.3 V Iod EWo Open drain output current EWo Internally limited Vcr voltage -0.3 to Vo + 0.3 V Vcr Internally limited V V VEWi Early warning input voltage -0.3 to 40 V VEn Enable input -0.3 to 40 V Junction temperature -40 to 150 °C ±2 kV ± 750 V Tj 2.2 Parameter VESD HBM ESD HBM voltage level (HBM-MIL STD 883C) VESD CDM ESD CDM voltage level (CDM- ) Thermal data Table 4. Thermal data Symbol Parameter Value(1) Unit Rthj-case Thermal resistance junction to case: PowerSSO-12 20 °K/W Rthj-amb Thermal resistance junction to ambient: PowerSSO-12 52 °K/W 1. The values quoted are for PCB 77 mm x 86 mm x 1.6 mm, FR4, double copper layer with single heatsink layer, copper thickness 70 µm, thermal vias, copper area 2 cm2. DS6182 Rev 15 7/29 28 Electrical specifications 2.3 L5150GJ Electrical characteristics Values specified in this section are for VS = 5.6 V to 31 V, Tj = -40 °C to +150 °C unless otherwise stated. Table 5. General Pin Symbol Vo Vo_ref Output voltage VS = 8 V to 18 V, Io = 8 mA to 150 mA 4.9 5.0 5.1 V Vo Vo_ref Output voltage VS = 5.6 V to 31 V, Io = 8 mA to 150 mA 4.85 5.0 5.15 V Vo Vo_ref Output voltage VS = 5.6 V to 31 V, Io = 0.1 mA to 8 mA 4.75 5.0 5.25 V Vo Ishort Short-circuit current VS = 13.5 V 0.65 0.95 1.25 A Vo Ilim Output current capability (1) VS = 13.5 V 280 470 660 mA VS, Vo Vline Line regulation voltage VS = 6 V to 28 V, Io = 30 mA – – 40 mV VS = 8 V to 18 V, Io = 8 mA to 150 mA – – 55 VS = 13.5 V, Tj = 25 °C, Io = 8 mA to 150 mA – – 40 Io = 150 mA – – 500 mV – 48 – dB Vo VS, Vo Vdp Load regulation voltage Drop voltage (2) Test condition (3) Min. Typ. Max. Unit mV VS, Vo SVR Ripple rejection fr = 100 Hz Vo Ioth_H Normal consumption mode output current VS = 8 V to 18 V 8 – – mA Vo Ioth_L Very low consumption mode VS = 8 V to 18 V output current – – 1.1 mA Vo Ioth_Hyst VS, Vo VS, Vo VS, Vo 8/29 Vload Parameter Iqs Iqn_1 Iqn_150 Output current switching threshold hysteresis VS = 13.5 V, Tj = 25 °C – 0.8 – mA Current consumption with regulator disabled Iqs = IVs – Io VS = 13.5 V, En = low – 5 10 µA VS = 13.5 V, Io = 0.1 mA to 1 mA, En = high Tj = 25 °C – 55 80 VS = 13.5 V, Io = 0.1 mA to 1 mA, En = high – VS = 13.5 V, Io = 150 mA, En = high – Current consumption with regulator enabled Iqn_1 = IVs – Io Current consumption with regulator enabled Iqn_150 = IVs – Io DS6182 Rev 15 µA 95 3.2 4.2 mA L5150GJ Electrical specifications Table 5. General (continued) Pin Symbol – Tw – Tw_hy Parameter Test condition Min. Typ. Max. Unit Thermal protection temperature – 150 – 190 °C Thermal protection temperature hysteresis – – 10 – °C 1. Measured output current when the output voltage has dropped 100 mV from its nominal value obtained at 13.5 V and Io = 75 mA. 2. Vs - Vo measured dropout when the output voltage has dropped 100 mV from its nominal value obtained at 13.5 V and Io = 75 mA. 3. Guaranteed by design. Table 6. Reset Pin Symbol Parameter Res Vres_l Reset output low voltage Res IRes_lkg Res Test condition Min. Typ. Max. Unit Rext = 5 kW, Vo > 1 V – – 0.4 V Reset output high leakage current VRes = 5 V – – 1 µA RRes Pull up internal resistance Versus Vo 10 20 40 kΩ Res Vo_th Vo out of regulation threshold VRes_adj < 0.2 V, Vo decreasing 6 8 10 % Below Vo_ref Res_adj VRes_adj Reset adjustable switching threshold – 2.35 2.5 2.65 V Res_adj VRes_adjl Reset adjustable low – voltage 0.4 0.9 1.3 V Res_adj IRes_adj_lkg Reset adjustable leakage current VRes_adj = 2.5 V -1 1 µA Vcr VRlth Reset timing low threshold VS = 13.5 V 15 18 22 % Vo_ref Vcr VRhth Reset timing high threshold VS = 13.5 V 47 50 53 % Vo_ref Vcr Icr Charge current VS = 13.5 V 10 20 30 µA Vcr Idr Discharge current VS = 13.5 V 10 20 30 µA Res Trr Reset reaction time – – – 2 µs Res Trd Reset delay time VS = 13.5 V, Ctr = 1000 pF 2 4 11 ms DS6182 Rev 15 9/29 28 Electrical specifications L5150GJ Table 7. Early warning Pin Symbol Parameter Test condition Min. Typ. Max. Unit EWi VEWi_thl EW input low threshold voltage – 2.35 2.50 2.65 V EWi VEWi_thh EW input high threshold voltage – 2.42 2.57 2.72 V EWi VEWi_thhyst EW input threshold hysteresis – – 70 – mV EWi IEWi_lkg EW input leakage current VEWi = 2.5 V, VS > 4 V -1 – 1 µA EWo REWo Pull up internal resistance Versus Vo 10 20 40 kΩ EWo VEWo_lv EW output low voltage (with external pull up) VEWi < 2.35 V, VS > 4 V, Rext = 5 kΩ – – 0.4 V EWo IEWo_lkg EW output leakage current VEWo = 5 V – – 1 µA Test condition Min. Typ. Max. Unit Table 8. Enable 2.4 Pin Symbol Parameter En VEn_low En input low voltage – – – 1 V En VEn_high En input high voltage – 3 – – V En VEn_hyst En input hysteresis – – 500 – mV En I_leak Pull-down current VEn = 5 V – 1.8 10 µA Electrical characteristics curves Figure 3. Output voltage vs. Tj Figure 4. Output voltage vs. VS Vo_ref(V) Vo-ref (V) 8 5.5 7 5.4 5.3 5.2 Io= 75mA 6 Vs= 13.5V 5 5.1 4 5 3 4.9 2 4.8 1 4.7 0 4.6 -1 4.5 Io = 75 mA Tc = 25 °C -2 -50 -25 0 25 50 75 100 125 150 175 0 1 Tj(°C) 3 4 5 VS (V) GAPGCFT00136 10/29 2 GAPGCFT00137 DS6182 Rev 15 6 7 8 9 10 L5150GJ Electrical specifications Figure 5. Output voltage vs. VEn Figure 6. Drop voltage vs. output current Vo_ref(V) Vdp(V) 7.2 6.4 0.5 Vs = 13.5V Tc = 25°C 5.6 0.45 0.4 4.8 0.35 4 Tj=125°C 0.3 3.2 0.25 2.4 0.2 1.6 0.15 0.8 0.1 0 0.05 Tj=25°C 0 -0.8 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 0 5.4 15 30 45 60 75 90 105 120 135 150 165 Io(mA) Ven(V) GAPGPS01383 Figure 7. Current consumption vs. output current GAPGCFT00138 Figure 8. Current consumption vs. output current (at light load condition) Iqn(mA) 3.5 Iqn (mA) 4.5 3.4 4 3.3 Vs = 13.5 V 3.5 3.2 3 3.1 Vs=13.5V Tj=25°C En=High 3 2.9 2.5 2 1.5 2.8 1 2.7 0.5 2.6 0 2.5 -0.5 0 20 40 60 80 100 120 140 0 160 1 2 3 4 5 Io (mA) 6 7 8 Io(mA) 9 10 GAPGCFT00140 GAPGPS01384 Figure 9. Current consumption vs. input voltage (Io = 0.1 mA) Iqn(μA) Figure 10. Current consumption vs. input voltage (Io = 75 mA) Iqn(mA) 200 5 180 4.6 En = High 160 4.2 140 3.8 120 3.4 100 3 80 2.6 60 2.2 40 1.8 20 1.4 0 3 5 7 9 11 13 15 17 19 21 23 1 3 Vs(V) 5 7 9 11 13 15 17 19 21 23 Vs(V) GAPGCFT00141 DS6182 Rev 15 GAPGPS01385 11/29 28 Electrical specifications L5150GJ Figure 11. Current limitation vs. Tj Figure 12. Current limitation vs. input voltage Ilim(mA) Ilim(mA) 800 800 740 740 680 680 Vs=13.5V 620 620 560 560 Tj=25°C 500 500 440 440 Tj=150°C 380 380 320 320 260 260 200 200 -50 -25 0 25 50 75 100 125 150 3 175 5 7 9 11 13 15 17 19 23 GAPGCFT00144 GAPGCFT00143 Figure 13. Short-circuit current vs. Tj Figure 14. Short-circuit current vs. input voltage Ishort(m A) Ishort(mA) 1600 1600 1500 1500 1400 Vs=13.5V 1400 1300 1300 1200 1200 1100 1100 1000 Tj=25°C 1000 900 900 800 Tj=150°C 800 700 700 600 -50 -25 0 25 50 75 100 125 150 175 600 0 Tj(°C) 2 4 6 8 Figure 15. VEn_high vs. Tj 12 14 16 18 20 GAPGCFT00147 Figure 16. VEn_low vs. Tj Ven_low (V) Ven_high(V) 2.2 2.4 2.1 2.3 2 2.2 1.9 2.1 1.8 2 Vs = 5.6V to 31V 1.9 1.7 1.8 1.6 Vs = 5.6V to 31V 1.5 1.7 1.4 1.6 1.3 1.5 1.4 -50 10 Vs(V) GAPGCFT00146 -25 0 25 50 75 100 125 150 175 1.2 -50 -25 0 25 50 75 100 125 150 175 Tj(°C) Tj(°C) GAPGPS01386 12/29 21 Vs(V) Tj(°C) DS6182 Rev 15 GAPGPS01387 L5150GJ Electrical specifications Figure 17. VRhth vs. Tj Figure 18. VRlth vs. Tj Vrhth(% Vo_ref) Vrlth (%Vo_ref) 55 30 54 27 53 24 52 21 Vs = 5.6V to 31V 51 18 50 15 49 12 48 9 47 6 46 3 Vs = 5.6V to 31V 0 45 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 Tj(°C) 75 100 125 150 175 Tj(°C) GAPGCFT00148 GAPGCFT00149 Figure 19. VEWi_thh vs. Tj Figure 20. VEWi_thl vs. Tj Vewi_thh(V) Vewi_thl(V) 5 5 4.5 4.5 Vs = 5.6V to 31V 4 4 3.5 3.5 3 3 2.5 2.5 Vs = 5.6V to 31V 2 2 1.5 1.5 1 1 0.5 0.5 0 0 -50 -50 -25 0 25 50 75 100 125 150 -25 0 25 50 175 75 100 125 150 175 Tj(°C) Tj(°C) GAPGCFT00151 GAPGCFT00150 Figure 21. Icr vs. Tj Figure 22. Idr vs. Tj Idr(μA) Icr(μA) 50 50 45 45 40 40 35 35 30 30 Vs = 5.6V to 31V 25 25 20 20 15 15 10 10 5 Vs = 5.6V to 31V 5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tj(°C) -25 0 25 50 75 100 125 150 175 Tj(°C) GAPGCFT00152 DS6182 Rev 15 GAPGCFT00153 13/29 28 Electrical specifications L5150GJ Figure 23. PSRR PSRR [dB] 70.00 60.00 Co=220nF 50.00 40.00 30.00 20.00 10.00 0.10 1.00 10.00 100.00 1000.00 0.00 10000.00 FREQUENCY [KHz] GAPGCFT00154 14/29 DS6182 Rev 15 L5150GJ Application information 3 Application information 3.1 Voltage regulator The voltage regulator uses a p-channel mos transistor as a regulating element. With this structure a very low dropout voltage at current up to 150 mA is obtained. The output voltage is regulated up to input supply voltage of 40 V. The high-precision of the output voltage (+/2%) is obtained with a pre-trimmed reference voltage. The voltage regulator automatically adapts its own quiescent current to the output current level. In light load conditions the quiescent current goes down to 55 µA only (low consumption mode). This procedure features a certain hysteresis on the output current (see Figure 8). Short-circuit protection to GND and a thermal shutdown are provided. Figure 24. Application schematic VBATT Vo Vs RST C1 C2 En R1EW L5150GJ R1 Co RST_ADJ Vcr EWi EWo R2 R2EW GND GAPGPS01388 The input capacitor C1 ≥ 100 µF is necessary as backup supply for negative pulses which may occur on the line. The second input capacitor C2 ≥ 220 nF is needed when the C1 is too distant from the VS pin and it compensates smooth line disturbances. The Co ceramic capacitor, connected to the output pin, is for bypassing to GND the high-frequency noise and it guarantees stability even during sudden line and load variations. Suggested value is Co = 220 nF with ESR ≥ 100 mΩ. Stability region is reported in Figure 25. DS6182 Rev 15 15/29 28 Application information L5150GJ Figure 25. Stability region 100 ESR (Ohm) 10 STABILITY REGION 1 ESRmin 0.1 0.01 UNTESTED REGION 0.001 0.22 0.47 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 4 4.5 4.7 Co (μF) GAPGPS01392 Note: The curve which describes the minimum ESR is derived from characterization data on the regulator with connected ceramic capacitors which feature low ESR values (at 100 kHz). Any capacitor with further lower ESR than the given plot value must be evaluated in each and every case. Figure 26. Maximum load variation response Vo = 50 mV/div Io = 50 mA/div Io (mA) 0 VS = 13.5 V Io = 8 to 150 mA Tc = 25 °C Co = 220 nF Vo (mV) -500 0 500 1000 1500 2000 Time (μs) GAPG2905151323PS 16/29 DS6182 Rev 15 L5150GJ 3.2 Application information Reset The reset circuit monitors the output voltage Vo. If the output voltage becomes lower than Vo_th then Res goes low with a delay time (trr). When the output voltage becomes higher than Vo_th then Res goes high with a delay time trd. This delay is obtained by 32 periods of oscillator. The oscillator period is given by: Equation 1 Tosc = [(VRhth - VRlth) x Ctr] / Icr + [(VRhth - VRlth) x Ctr] / Idr where: Icr = 20 µA is an internally generated charge current, Idr = 20 µA is an internally generated discharge current, VRhth = 2.5 V (typ) and VRlth = 0.9 V (typ) are two voltage thresholds, Ctr is an external capacitor put between Vcr pin and GND. DS6182 Rev 15 17/29 28 Application information L5150GJ Reset pulse delay Trd is given by: Equation 2 trd = 32 x Tosc The Output Voltage Reset threshold can be adjusted via an external voltage divider R1 + R2 (R1 connected between Res_Adj and V0, R2 connected between Res_Adj and GND) according to the following formula: Equation 3 Vthre = [(R1 + R2) / R2] * VRes_adj The Output Voltage Reset threshold can be decreased down to 3.5 V. If it is needed to maintain it to its default value (8% below Vo_ref typical), it is enough to connect the Res_Adj pin directly to GND. Figure 27. Reset time diagram Vo Vout_th < trr trr TOSC Vcr VRhth VRlth trd = 32 TOSC Res GAPGPS01390 18/29 DS6182 Rev 15 L5150GJ 3.3 Application information Early warning This circuit compares the EWi input signal with the internal voltage reference (typically 2.5 V). The use of an external voltage divider makes the comparator very flexible in the application. This function can be used to supervise the supply input voltage either before or after the protection diode and to give additional information to the microprocessor such as low voltage warnings. Figure 28. Early warning time diagram EWi Ewi_th_high Ewi_th_low t EWo HIGH LOW t GAPGCFT00055 3.4 Enable L5150GJ is also provided with an enable input, an high signal switches the regulator on. When the enable pin is set to low the output is switched-off and the current consumption of the device is 5 µA typical. DS6182 Rev 15 19/29 28 Package and PCB thermal data L5150GJ 4 Package and PCB thermal data 4.1 PowerSSO-12 thermal data Figure 29. PowerSSO-12 PC board . GAPGCFT000120 1. Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias, FR4 area = 77 mm x 86 mm, PCB thickness =1.6 mm, Cu thickness = 70 µm (front and back side) thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 25 µm, footprint dimension 4.1 mm x 6.5 mm ). Figure 30. Rthj-amb vs PCB copper area in open box free air condition RTHj_amb(°K/W) 70 65 60 55 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) GAPGPS01391 20/29 DS6182 Rev 15 L5150GJ Package and PCB thermal data Figure 31. PowerSSO-12 thermal impedance junction ambient single pulse ZTH (°C/W) 100 Cu=8 cm2 Cu=2 cm2 Cu=foot print 10 1 0.001 0.01 0.1 1 Time (s) 10 100 1000 GAPGCFT00156 Equation 4: pulse calculation formula Z TH = R TH   + Z THtp  1 –   where  = tP/T Figure 32. Thermal fitting model of Vreg in PowerSSO-12 GAPGCFT00157 DS6182 Rev 15 21/29 28 Package and PCB thermal data L5150GJ Table 9. PowerSSO-12 thermal parameter 2 22/29 Area (cm ) Footprint 2 8 R1 (°K/W) 1.53 R2 (°K/W) 3.21 R3 (°K/W) 5.2 R4 (°K/W) 7 7 8 R5 (°K/W) 22 15 10 R6 (°K/W) 26 20 15 C1 (W.s/°K) 0.00004 C2 (W.s/°K) 0.0016 C3 (W.s/°K) 0.08 C4 (W.s/°K) 0.2 0.1 0.1 C5 (W.s/°K) 0.27 0.8 1 C6 (W.s/°K) 3 6 9 DS6182 Rev 15 L5150GJ 5 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 5.1 PowerSSO-12 package information Figure 33. PowerSSO-12 package outline GAPGCFT000122 DS6182 Rev 15 23/29 28 Package information L5150GJ Table 10. PowerSSO-12 package mechanical data Millimeters Symbol Min. Max. A 1.250 1.620 A1 0.000 0.100 A2 1.100 1.650 B 0.230 0.410 C 0.190 0.250 D 4.800 5.000 E 3.800 4.000 e 0.800 H 5.800 6.200 h 0.250 0.500 L 0.400 1.270 k 0° 8° X 2.200 2.800 Y 2.900 3.500 ddd 24/29 Typ. 0.100 DS6182 Rev 15 L5150GJ 5.2 Package information PowerSSO-12 packing information Figure 34. PowerSSO-12 tube shipment (no suffix) B Base q.ty Bulk q.ty Tube length (± 0.5) A B C (± 0.1) C A 100 2000 532 1.85 6.75 0.6 All dimensions are in mm. GAPGPS01364 Figure 35. PowerSSO-12 tape and reel shipment (suffix “TR”) Reel dimensions Base q.ty Bulk q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 19 86 Tape width Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing W P0 (± 0.1) P D (± 0.05) D1 (min) F (± 0.1) K (max) P1 (± 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 All dimensions are in mm. End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed GAPGPS01365 DS6182 Rev 15 25/29 28 Revision history 6 L5150GJ Revision history Table 11. Document revision history Date Revision 09-Aug-2007 1 Initial release. 2 Modified Description on cover page. Updated Table 5.: General: – changed Vo_ref, Vline, Vload test conditions – added notes to Ilim and Vdp parameters – added Ioth_H, Ioth_L, Ioth parameters. Updated Table 6.: Reset: – added VRes_adj parameter – changed VRlth values (min./ typ./ max.) from 17/20/23 to 20/23/26 (% Vo_ref). Updated Table 8.: Enable: – changed VEn_hyst typ. value from 800 mV to 500 mV – changed I_leak typ. value from 3 µA to 1.8 µA. Modified Section 3.2: Reset. 3 Updated Table 5.: General : – changed Ilim values (Min./Typ./Max.) from 0.7/1/1.30 A to 280/470/660 mA. – Vo_ref parameter : updated Io test condition Old -> Io= 0.1 mA to I0mA New -> Io= 0.1 mA to 8 mA. 4 Updated Table 5.: General : – Vload parameter : updated Io test condition Old -> Io= 5 mA to I50 mA New -> Io= 8 mA to 150 mA 06-Mar-2008 09-May-2008 13-Oct-2008 26/29 Changes DS6182 Rev 15 L5150GJ Revision history Table 11. Document revision history (continued) Date 15-Apr-2009 Revision Changes 5 Updated corporate template Updated Figure 2: Configuration diagram (top view) Table 2: Pins description – Added new row Table 4: Thermal data – Rthj-amb: changed value – Updated TableFootnote Table 5: General – Vload: changed max value for Vs = 8 V to 18 V, added new row – Iqn_1: changed Test conditions (added Tj = 25 °C), added new row Table 6: Reset – VRlth: changed min/typ/max value – VRes_adjl: replaced with VRlth, changed Parameter Table 7: Early warning – Updated symbols Added Figure 3: Output voltage vs. Tj Added Figure 4: Output voltage vs. VS Added Figure 5: Output voltage vs. VEn Added Figure 6: Drop voltage vs. output current Added Figure 7: Current consumption vs. output current Added Figure 8: Current consumption vs. output current (at light load condition) Added Figure 9: Current consumption vs. input voltage (Io = 0.1 mA) Added Figure 10: Current consumption vs. input voltage (Io = 75 mA) Added Figure 11: Current limitation vs. Tj Added Figure 12: Current limitation vs. input voltage Added Figure 13: Short-circuit current vs. Tj Added Figure 14: Short-circuit current vs. input voltage Added Figure 15: VEn_high vs. Tj Added Figure 16: VEn_low vs. Tj Added Figure 17: VRhth vs. Tj Added Figure 18: VRlth vs. Tj Added Figure 19: VEWi_thh vs. Tj Added Figure 20: VEWi_thl vs. Tj Added Figure 21: Icr vs. Tj Added Figure 22: Idr vs. Tj Added Figure 23: PSRR Section 3.1: Voltage regulator – Updated text – Added Figure 24: Application schematic – Added Figure 26: Maximum load variation response Section 3.2: Reset – VRlth: changed value from 1.15 V to 0.9 V in Equation 1 Updated Section 3.4: Enable Added Section 4: Package and PCB thermal data Changed Section 5.1: ECOPACK® DS6182 Rev 15 27/29 28 Revision history L5150GJ Table 11. Document revision history (continued) Date Changes 6 Changed document title Table 5: General – Ioth_H, Ioth_L: added test condition Updated Figure 4: Output voltage vs. VS Section 3.3: Early warning – changed internal voltage reference typical value from  1.23 V to 2.5 V Updated Figure 31: PowerSSO-12 thermal impedance junction ambient single pulse 7 Updated features list. Updated Table 2: Pins description. Updated Section 3.1: Voltage regulator. Corrected Equation 3 on Section 3.2: Reset. 19-Apr-2010 8 Updated footnote description of Table 4: Thermal data. Updated Figure 30: Rthj-amb vs PCB copper area in open box free air condition. Updated Table 9: PowerSSO-12 thermal parameter. 30-Jan-2012 9 Updated Figure 25: Stability region on page 16. 07-Feb-2012 10 Modified Figure 25: Stability region on page 16. 02-Oct-2012 11 Updated Table 6: Reset: – Trd: updated maximum value 19-Sep-2013 12 Updated disclaimer. 03-Jun-2015 13 Changed in Table 5 the typical value of SVR from 60 dB to 48 dB. 27-Sep-2018 14 Updated title and Features. 07-Jul-2021 15 Updated Table 10: PowerSSO-12 package mechanical data: – X and Y Symbol dimension. 09-Jun-2009 04-Dec-2009 28/29 Revision DS6182 Rev 15 L5150GJ IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS6182 Rev 15 29/29 29