L5986
2.5 A step-down switching regulator
Datasheet - production data
Industrial: chargers, PLD, PLA, FPGA
Networking: XDSL, modems, DC-DC modules
Computer: optical storage, hard disk drive,
printers, audio/graphic cards
VFQFPN8 3 x 3 mm
HSOP8 exposed pad
Description
Features
2.5 A DC output current
2.9 V to 18 V input voltage
Output voltage adjustable from 0.6 V
250 kHz switching frequency, programmable
up to 1 MHz
Internal soft-start and inhibit
Low dropout operation: 100% duty cycle
Voltage feedforward
Zero load current operation
Overcurrent and thermal protection
VFQFPN 3 x 3 mm -8L and HSOP8 package
Applications
LED driving
The L5986 is a step-down switching regulator
with a 3.0 A (min.) current limited embedded
Power MOSFET, so it is able to deliver up to 2.5 A
current to the load depending on the application
conditions.
The input voltage can range from 2.9 V to 18 V,
while the output voltage can be set starting from
0.6 V to VIN. Having a minimum input voltage of
2.9 V, the device is suitable also for a 3.3 V bus.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
The QFN and the HSOP packages with an
exposed pad allow reducing the RthJA down to
60 °C/W and 40 °C/W respectively.
Consumer: STB, DVD, DVD recorder, car
audio, LCD TV and monitors
Figure 1. Application circuit
May 2014
This is information on a product in full production.
DocID14971 Rev 5
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www.st.com
Contents
L5986
Contents
1
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
7
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5.1
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.3
Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5
Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4.1
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.2
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.5
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1
Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2
Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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L5986
Contents
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Pin settings
L5986
1
Pin settings
1.1
Pin connection
Figure 2. Pin connection (top view)
OUT
VCC
SYNCH
GND
INH
FSW
COMP
1.2
FB
Pin description
Table 1. Pin description
4/42
No.
Type
1
OUT
Description
Regulator output
2
SYNCH
Master/slave synchronization. When it is left floating, a signal with
a phase shift of half a period with respect to the power turn-on is present
at the pin. When connected to an external signal at a frequency higher
than the internal one, then the device is synchronized by the external
signal, with zero phase shift.
Connecting together the SYNCH pin of two devices, the one with the
higher frequency works as a master and the other as a slave; so the two
turn-on powers have a phase shift of half a period.
3
INH
A logical signal (active high) disables the device. With INH higher than
1.9 V the device is OFF and with INH lower than 0.6 V the device is ON.
4
COMP
5
FB
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from the Vout to the FB pin.
6
FSW
The switching frequency can be increased connecting an external
resistor from the FSW pin and ground. If this pin is left floating, the device
works at its free-running frequency of 250 kHz.
7
GND
Ground
8
VCC
Unregulated DC input voltage
Error amplifier output to be used for loop frequency compensation
DocID14971 Rev 5
L5986
Maximum ratings
2
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
VCC
Input voltage
OUT
Output DC voltage
Value
20
-0.3 to VCC
FSW, COMP, SYNCH Analog pin
3
-0.3 to 4
INH
Inhibit pin
-0.3 to VCC
FB
Feedback voltage
-0.3 to 1.5
PTOT
Unit
Power dissipation at TA < 60 °C
VFQFPN
1.5.
HSOP
2
V
W
TJ
Junction temperature range
-40 to 150
°C
Tstg
Storage temperature range
-55 to 150
°C
Value
Unit
Thermal data
Table 3. Thermal data
Symbol
RthJA
Parameter
Maximum thermal resistance junction ambient(1)
VFQFPN
60
HSOP
40
°C/W
1. Package mounted on demonstration board.
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42
Electrical characteristics
4
L5986
Electrical characteristics
TJ = 25 °C, VCC = 12 V, unless otherwise specified.
Table 4. Electrical characteristics
Values
Symbol
Parameter
Test condition
Unit
Min.
Operating input voltage range
(1)
Turn-on VCC threshold
(1)
VCCHYS
VCC UVLO hysteresis
(1)
RDS(on)
MOSFET on resistance
VCC
VCCON
ILIM
2.9
Max.
18
2.9
0.175
V
0.3
140
170
140
220
3.0
3.5
3.9
225
250
275
(1)
Maximum limiting current
Typ.
m
A
Oscillator
FSW
Switching frequency
VFSW
FSW pin voltage
D
FADJ
(1)
275
1.262
Duty cycle
Adjustable switching frequency
220
0
RFSW = 33 k
kHz
V
100
1000
%
kHz
Dynamic characteristics
VFB
Feedback voltage
2.9 V < VCC < 18 V(1)
0.593
0.6
0.607
V
2.4
mA
30
A
DC characteristics
IQ
IQST-BY
Quiescent current
Duty cycle = 0, VFB = 0.8 V
Total standby quiescent current
20
Inhibit
INH threshold voltage
INH current
Device ON level
Device OFF level
0.6
1.9
INH = 0
7.5
10
8.2
9.1
V
A
Soft-start
TSS
Soft-start duration
FSW pin floating
7.4
FSW = 1 MHz, RFSW = 33 k
2
ms
Error amplifier
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VCH
High level output voltage
VFB < 0.6 V
VCL
Low level output voltage
VFB > 0.6 V
IFB
Bias source current
VFB = 0 V to 0.8 V
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3
0.1
1
V
A
L5986
Electrical characteristics
Table 4. Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min.
IO SOURCE Source COMP pin
IO SINK
GV
Typ.
Max.
VFB = 0.5 V, VCOMP = 1 V
20
mA
Sink COMP pin
VFB = 0.7 V, VCOMP = 1 V
25
mA
Open loop voltage gain
(2)
100
dB
Synchronization function
High input voltage
2
3.3
Low input voltage
1
Slave sink current
VSYNCH = 2.9 V
Master output amplitude
ISOURCE = 4.5 mA
Output pulse width
SYNCH floating
Input pulse width
0.7
0.9
2.0
V
mA
V
110
70
ns
Protection
IFBDISC
TSHDN
FB disconnection source current
1
Thermal shutdown
150
Hysteresis
30
A
°C
1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by
design, characterization and statistical correlation.
2. Guaranteed by design.
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Functional description
5
L5986
Functional description
The L5986 device is based on a “voltage mode”, constant frequency control. The output
voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V)
providing an error signal that, compared to a fixed frequency sawtooth, controls the ON and
OFF time of the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feedforward are implemented.
The soft-start circuitry to limit inrush current during the startup phase
The voltage mode error amplifier
The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch
The high-side driver for embedded P-channel Power MOSFET switch
The peak current limit sensing block, to handle overload and short-circuit conditions
A voltage regulator and internal reference. It supplies internal circuitry and provides
a fixed internal reference.
A voltage monitor circuitry (UVLO) that checks the input and internal voltages
A thermal shutdown block, to prevent thermal runaway.
Figure 3. Block diagram
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L5986
5.1
Functional description
Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides
a constant frequency clock. Its frequency depends on the resistor externally connected to
the FSW pin. In case the FSW pin is left floating, the frequency is 250 kHz; it can be
increased as shown in Figure 6 by an external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feedforward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feedforward is implemented (Figure 5.b) in order to
keep the PWM gain constant versus the switching frequency (see Section 6.4 on page 18
for PWM gain expression).
The synchronization signal is generated on the SYNCH pin. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pins together. When SYNCH pins are connected, the device with
a higher oscillator frequency works as a master, so the slave device switches at the
frequency of the master but with a delay of half a period. This minimizes the RMS current
flowing through the input capacitor (see the L5988D datasheet: “4 A continuous (more than
5 A pulsed) step-down switching regulator with synchronous rectification”).
Figure 4. Oscillator circuit block diagram
Clock
FSW
Clock
Generator
Synchronization
SYNCH
Ramp
Generator
Sawtooth
The device can be synchronized to work at a higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This change has to be taken into account when the loop stability is studied. To
minimize the change of the PWM gain, the free running frequency should be set (with
a resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency changes the sawtooth slope in order to render the truncation of
sawtooth negligible, due to the external synchronization.
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Functional description
L5986
Figure 5. Sawtooth: voltage and frequency feedforward; external synchronization
Figure 6. Oscillator frequency vs. FSW pin resistor
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L5986
5.2
Functional description
Soft-start
The soft-start is essential to assure a correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increase monotonically.
The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error
amplifier. So the output voltage slew rate is:
Equation 1
R1
SR OUT = SR VREF 1 + --------
R2
where SRVREF is the slew rate of the non-inverting input, while R1 and R2 is the resistor
divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of
64 steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles.
So the soft-start time and then the output voltage slew rate depend on the switching
frequency.
Figure 7. Soft-start scheme
Soft-start time results:
Equation 2
32 64
SS TIME = ----------------Fsw
For example, with a switching frequency of 250 kHz the SSTIME is 8 ms.
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Functional description
5.3
L5986
Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
Table 5. Uncompensated error amplifier characteristics
Parameter
Value
Low frequency gain
100 dB
GBWP
4.5 MHz
Slew rate
7 V/s
Output voltage swing
0 to 3.3 V
Maximum source/sink current
25 mA/40 mA
In continuous conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter, a type II compensation network can be used. Otherwise,
a type III compensation network has to be used (see Section 6.4 on page 18 for details of
the compensation network selection).
However, the methodology to compensate the loop is to introduce zeros to obtain a safe
phase margin.
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L5986
5.4
Functional description
Overcurrent protection
The L5986 device implements the overcurrent protection sensing current flowing through
the Power MOSFET. Due to the noise created by the switching activity of the Power
MOSFET, the current sensing is disabled during the initial phase of the conduction time.
This avoids an erroneous detection of a fault condition. This interval is generally known as
“masking time” or “blanking time”. The masking time is about 200 ns.
When the overcurrent is detected, two different behaviors are possible depending on the
operating condition.
1.
Output voltage in regulation. When the overcurrent is sensed, the Power MOSFET is
switched off and the internal reference (VREF), that biases the non-inverting input of the
error amplifier, is set to zero and kept in this condition for a soft-start time (TSS, 2048
clock cycles). After this time, a new soft-start phase takes place and the internal
reference begins ramping (see Figure 8.a).
2.
Soft-start phase. If the overcurrent limit is reached, the Power MOSFET is turned off
implementing the pulse by pulse overcurrent protection. During the soft-start phase,
under the overcurrent condition, the device can skip pulses in order to keep the output
current constant and equal to the current limit. If, at the end of the “masking time”, the
current is higher than the overcurrent threshold, the Power MOSFET is turned off and it
skips one pulse. If, at the next switching on at the end of the “masking time”, the current
is still higher than the threshold, the device skips two pulses. This mechanism is
repeated and the device can skip up to seven pulses. While, if at the end of the
“masking time” the current is lower than the overcurrent threshold, the number of
skipped cycles is decreased by one unit. At the end of the soft-start phase the output
voltage is in regulation and if the overcurrent persists, the behavior explained above
takes place (see Figure 8.b).
So the overcurrent protection can be summarized as a “hiccup” intervention when the output
is in regulation and a constant current during the soft-start phase.
If the output is shorted to ground when the output voltage is in regulation, the overcurrent is
triggered and the device starts cycling with a period of 2048 clock cycles between the
“hiccup” (Power MOSFET off and no current to the load) and “constant current” with very
short ON time and with reduced switching frequency (up to one eighth of normal switching
frequency). See Figure 31 on page 33 for short-circuit behavior.
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Functional description
L5986
Figure 8. Overcurrent protection strategy
5.5
Inhibit function
The inhibit feature allows the device to be put into standby mode. With the INH pin higher
than 1.9 V, the device is disabled and the power consumption is reduced to less than 30 A.
With the INH pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an
internal pull-up ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also VCC compatible.
5.6
Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, therefore ensuring an accurate and fast temperature detection.
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L5986
Application information
6
Application information
6.1
Input capacitor selection
The capacitor connected to the input must be able to support the maximum input operating
voltage and the maximum RMS input current required by the device. The input capacitor is
a subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting
the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 3
2
2
2D
D
I RMS = I O D – --------------- + ------2
where IO is the maximum DC output current, D is the duty cycle, is the efficiency.
Considering = 1, this function has a maximum at D = 0.5 and it is equal to IO/2.
In a specific application the range of possible duty cycles must be considered in order to find
out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 4
V OUT + V F
D MAX = ------------------------------------V INMIN – V SW
and
Equation 5
V OUT + V F
D MIN = -------------------------------------V INMAX – V SW
where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across
the internal PDMOS.
In Table 6 some multi-layer ceramic capacitors suitable for this device are reported.
Table 6. Input capacitors
Manufacturer
MURATA
TDK
Series
Cap value (F)
Rated voltage (V)
GRM31
10
25
GRM55
10
25
C3225
10
25
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42
Application information
6.2
L5986
Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value, in order to have the expected current ripple, must be selected.
The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.
In the continuous current mode (CCM), the inductance value can be calculated by the
following equation:
Equation 6
V IN – V OUT
V OUT + V F
I L = ------------------------------ T ON = ---------------------------- T OFF
L
L
where TON is the conduction time of the internal high-side switch and TOFF is the conduction
time of the external diode [in CCM, FSW = 1/(TON + TOFF)]. The maximum current ripple, at
fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle (see Section 6.1 to
calculate minimum duty). So fixing IL = 20% to 30% of the maximum output current, the
minimum inductance value can be calculated:
Equation 7
V OUT + V F 1 – D MIN
L MIN = ---------------------------- ----------------------I MAX
F SW
where FSW is the switching frequency, 1 / (TON + TOFF).
For example, for VOUT = 3.3 V, VIN = 12 V, IO = 2.5 A and FSW = 250 kHz, the minimum
inductance value to have IL = 30% of IO is about 12 H.
The peak current through the inductor is given by:
Equation 8
I L
I L PK = I O + -------2
So if the inductor value decreases, the peak current (which must be lower than the current
limit of the device) increases. The higher the inductor value, the higher the average output
current that can be delivered, without reaching the current limit.
In Table 7 some inductor part numbers are listed.
Table 7. Inductors
Manufacturer
Coilcraft
Wurth
SUMIDA
16/42
Series
Inductor value (H)
Saturation current (A)
MSS1038
3.8 to 10
3.9 to 6.5
MSS1048
12 to 22
3.84 to 5.34
PD Type L
8.2 to 15
3.75 to 6.25
PD Type M
2.2 to 4.7
4 to 6
CDRH6D226/HP
1.5 to 3.3
3.6 to 5.2
CDR10D48MN
6.6 to 12
4.1 to 5.7
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L5986
6.3
Application information
Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge and discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
Equation 9
I MAX
V OUT = ESR I MAX + ------------------------------------8 C OUT f SW
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Section 6.4, how to consider its effect in the system stability is
illustrated.
For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.75 A (resulting from the inductor value),
in order to have a VOUT = 0.01·VOUT, if the multi-layer ceramic capacitor is adopted, 11 µF
is needed and the ESR effect on the output voltage ripple can be neglected. In case of not
negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value.
So in case of 330 µF with ESR = 30 m, the resistive component of the drop dominates and
the voltage ripple is 22.5 mV
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth, the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application, the output capacitor and system bandwidth
must be chosen in order to sustain the load transient.
In Table 8 some capacitor series are listed.
Table 8. Output capacitors
Manufacturer
Series
Cap value (F)
Rated voltage (V)
ESR (m)
GRM32
22 to 100
6.3 to 25
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