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L5988D

L5988D

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    TSSOP16_EP

  • 描述:

    IC REG BUCK ADJ 4A SYNC 16HTSSOP

  • 数据手册
  • 价格&库存
L5988D 数据手册
L5988D 4 A continuous (more than 5 A pulsed) step-down switching regulator with synchronous rectification Datasheet - production data  FSW programmable up to 1 MHz  Voltage feed forward  Zero load current operation  Programmable current limit on both switches  Programmable sink current capability  Pre-bias start up capability  Thermal shutdown HTSSOP16 Applications Features  Consumer: STB, DVD, LCD TV, VCR, car radio, LCD monitors  4 A output current (more than 5 pulsed)  Operating input voltage from 2.9 V to 18 V  External 1.8 V ± 2% reference voltage  Networking: XDSL, modems, routers and switches  Output voltage from 0.6 to input voltage  Computer and peripherals: printers, audio / graphic cards, optical storage, hard disk drive  MLCC compatible  Industrial: DC-DC modules, factory automation  200 ns TON  HC LED driving  Programmable UVLO matches 3.3 V, 5 V and 12 V bus Figure 1. Test application circuit April 2015 This is information on a product in full production. DocID15324 Rev 4 1/52 www.st.com Contents L5988D Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 2/52 5.1 Multifunction pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 External voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.2 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5.3 UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.5.4 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.6 Minimum on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.7 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5 R.M.S. current of the embedded power MOSFETs . . . . . . . . . . . . . . . . . 36 6.6 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.7 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.8 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DocID15324 Rev 4 L5988D Contents 7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DocID15324 Rev 4 3/52 52 List of tables L5988D List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. 4/52 Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 A/D voltage windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 UOS voltage biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FSW resistor examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ILIM-ADJ resistor examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Uncompensated error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Component list application circuit (fSW = 400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Component list application circuit (fSW = 600 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 HTSSOP16 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DocID15324 Rev 4 L5988D List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Test application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage mode control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Sawtooth: voltage feed forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sawtooth: synchronization and frequency adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input RMS current of two synchronized regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 OVP not latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 OVP latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Constant current protection at extreme duty cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Minimum TON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Open loop gain: module bode diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Open loop gain bode diagram with ceramic output capacitor . . . . . . . . . . . . . . . . . . . . . . . 32 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Open loop gain: module bode diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Open loop gain bode diagram with high ESR output capacitor . . . . . . . . . . . . . . . . . . . . . 35 Maximum continuous output current vs. duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Estimation of the internal power losses (VIN = 12 V, VOUT = 1.2 V, fSW = 400 kHz). . . . . . 39 Estimation of the internal power losses (VIN = 5 V, VOUT = 1.2 V, fSW = 400 kHz). . . . . . . 40 Measurement of the thermal impedance of the evaluation board. . . . . . . . . . . . . . . . . . . . 41 Top board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Bottom board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Demonstration board application circuit (fSW = 400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Demonstration board application circuit (fSW = 600 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Junction temperature vs. fSW at VIN = 12 V, VOUT = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . 46 Junction temperature vs. fSW at VIN = 5 V, VOUT = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Junction temperature vs. fSW at VIN = 3.3 V, VOUT = 1.2 V . . . . . . . . . . . . . . . . . . . . . . . . 46 Junction temperature vs. VOUT at VIN = 12 V, fSW = 400 kHz . . . . . . . . . . . . . . . . . . . . . . 46 Junction temperature vs. VOUT at VIN = 5 V, fSW = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . 47 Junction temperature vs. VOUT at VIN = 3.3 V, fSW = 400 kHz . . . . . . . . . . . . . . . . . . . . . . 47 Efficiency vs. output current at VIN = 3.3 V, fSW = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . 47 Efficiency vs. output current at VIN = 5 V, fSW = 250 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Load transient from 0 to 3 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HTSSOP16 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DocID15324 Rev 4 5/52 52 Description 1 L5988D Description The L5988D is a monolithic step down power switching regulator able to deliver a continuous output current of 4 A to the load in most of the application conditions limited only by the thermal performance. The device is able to deliver more than 5 A to the load for a maximum time which is dependent on the thermal impedance of the system and the specific operating conditions). The input voltage can range from 2.9 V to 18 V. The device is capable of 100% duty cycle operation thanks to the embedded high side PMOS switch which doesn’t need external bootstrap capacitor to be driven. The internal switching frequency is adjustable by external resistor and can be set continuously from 100 kHz to 1 MHz. The L5988D can also be synchronized to an external frequency signal driven to the SYNCH pin I/O pin. The multifunction UOS pin allows to set-up properly the additional embedded features depending on the value of the voltage level.  U (UVLO): two UVLO thresholds can be selected to match the 3.3 V and 5 V or 12 V input buses  O (OVP): latched or not latched OVP protection selectable. In latched mode the switching activity is interrupted until an UVLO or INH event happens  S (SINK): the sink capability is always disabled during soft-start time to support prebiased output voltage. Afterwards the sink capability can be enabled or not depending on the voltage set on the multifunction pin. During soft-start phase a constant current protection is active to deliver extra current necessary to load the output capacitor. The current limit protection is achieved by sensing the current flowing in both embedded switches to assure an effective protection even at extreme duty cycle operations. Finished the soft-start phase the current protection feature triggers the “HICCUP” mode forcing the soft-start capacitor to be discharged and recharged. The current thresholds of both switches can be adjusted in tracking by using an external resistor to dimension the current protection accordingly to the local application. The soft-start time is based on a constant current charge of an external capacitor. As a consequence the time can be set accordingly to the value of the output capacitor. The latest smart power technology BCD6 (Bipolar-CMOS-DMOS version 6) features a low resistance of the embedded switches (35 m typical for a NMOS, 50 m typical for a PMOS), achieving high efficiency levels. The HTSSOP16 package with exposed pad accomplishes low RthJA (40 °C/W), useful in dissipating power internally generated during high output current / high frequency operations. 6/52 DocID15324 Rev 4 L5988D 2 Pin function Pin function Figure 2. Pin connection Table 1. Pinout description No. Name Description 1, 16 OUT Regulator output 2, 3 VIN Unregulated DC input voltage 4 VCC Unregulated DC signal input voltage 5 SS/INH An external logic signal (active LOW) disables the device. In case the pin is floating the device deliver a constant current (22 A typ.) to charge the soft-start capacitor (see Section 5.4 on page 18) 6 COMP Error amplifier output for frequency compensation 7 ILIM-ADJ Connecting a pull-up resistor to VREF or a pull-down resistor to GND the internal current limit thresholds can be tuned to match the local application. In case the pin is left floating no changes are applied to the default current limit thresholds 8 FB Feedback input. Connecting the output voltage directly to this pin results in a regulation voltage of 600 mV. An external resistive divider is required for higher output voltages 9 SYNCH Master/slave synchronization 10 FSW Connecting a pull-up resistor to VREF or a pull-down resistor to GND the internal oscillator frequency will be increased or decreased respectively. In case the pin is left floating the predefined oscillator frequency (400 kHz ± 10%) is active 11 U/O/S Multifunction pin used to program additional features: UVLO thresholds, OVP latched/not latched, SINK enabled/disabled 12 VREF 1.8 V voltage reference 13 SGND Signal ground 14, 15 PGND Power ground DocID15324 Rev 4 7/52 52 Maximum ratings 3 L5988D Maximum ratings Table 2. Absolute maximum ratings Symbol VCC VOUT Parameter Input voltage Output DC voltage -0.3 U/O/S, SS/INH, COMP, SYNCH, Analog pins Fsw, ILIM-ADJ Value Unit 20 V (1) to VCC V -0.3 to 4 V FB Feedback voltage 1.5 V Ptot Power dissipation at TA < 60 °C 2.25 W TJ Junction temperature range -40 to 150 °C TSTG Storage temperature range -55 to 150 °C 1. During the switching activity the negative peak voltage could reach -1.5 V without any damage for the device. Table 3. Thermal data Symbol RthJA Parameter Value Unit 40 (1) °C/W Test condition Value Unit HBM 1 kV CDM 250 V Thermal resistance junction to ambient max. 1. HTSSOP16 package mounted on ST demonstration board. Table 4. ESD protection Symbol ESD 8/52 DocID15324 Rev 4 L5988D 4 Electrical characteristics Electrical characteristics VCC = 12 V, TJ = 25 °C unless otherwise specified. Table 5. Electrical characteristic Symbol VCC Parameter Operating input voltage range Test condition Min. Vout = 0.6 V; Iout = 3 A 2.9 RDS(on) HS High side MOSFET on resistance Iout = 1.0 A (1) RDS(on) LS (1) Low side MOSFET on resistance Iout = 1.0 A Typ. Max. Unit 18 V 75 85 95 m 111 120 132 m 62 67 72 m 92 100 106 m IL HIGH SIDE Maximum peak limiting current ILIM-ADJ = float 3.6 4 4.4 A IL LOW SIDE Maximum valley limiting current ILIM-ADJ = float 4.14 4.6 5.06 A Switching frequency FSW = floating 360 400 440 kHz adjusted switching frequency RFSW PULL DWN = 27 k fSW fSW ADJ D 1000 Duty cycle 0 kHz 100 % 2.8 V Selectable under voltage lockout (UVLO) Turn ON Vcc threshold 3.3 V BUS 2.7 Turn OFF Vcc threshold 2.4 Hysteresis Turn ON Vcc threshold 12 V BUS 2.5 V 200 mV 8 Turn OFF Vcc threshold 6.8 8.6 V 7 V 1 V VSS/INH = 2 V 22 A VSS/INH = 0 5 A Hysteresis DC characteristic ISS INH Iq Iq st-by Soft-start current Device ON level 0.8 V Device OFF level Quiescent current Duty cycle = 0; VFB = 1 V Total stand-by quiescent current 0.3 V 3 mA 35 A Dynamic characteristic (see Figure 1 on page 1) VFB Voltage feedback in regulation 2.9 V < VCC < 18 V (1) 0.595 0.6 0.605 0.592 0.6 0.609 V Error amplifier VOH High level output voltage VFB = 0.2 V; SS floating VOL Low level output voltage VFB = 1.0 V DocID15324 Rev 4 3.1 V 0.1 V 9/52 52 Electrical characteristics L5988D Table 5. Electrical characteristic (continued) Symbol IO SOURCE Parameter Source output current IO SRCE LIM Source current limitation IO SINK AV0 Sink output current Test condition VFB = 0.2 V Min. (2) VFB = 0.2 V, VCOMP = 3 V VFB = 1.0 V, VCOMP = 0.5 V (2) DC open loop gain Typ. Max. Unit 25 mA 2 mA 30 mA 100 dB Sync function High input voltage 2.9 Low input voltage Slave sink current VSYNC = 3.3 V; FSW = float Master output amplitude ISOURCE = 5 mA Output pulse width SYNCH = floating 4.0 V 0.74 V 1 mA 2.9 V 100 Input pulse width ns 70 ns Reference section VREF Reference voltage Vcc = 2.9 V to 18 V Line regulation Vcc = 2.9 V to 18 V IREF = 0 mA Load regulation IREF = 0 to 5 mA (1) Short circuit current 1.756 1.8 1.837 V 1.754 1.8 1.852 V 6 12 mV 7.5 15 mV 12 18 24 mA 15 20 24 % VFB Protections VFB_OVP Overvoltage trip (VFB_OVP - VFB) / VFB VFB rising Bus thresholds TH1 – UVLO 3.3 V bus – OVP not latched – No sink (3) 0 0.2 V TH2 – UVLO 3.3 V bus – OVP not latched – Sink (3) 0.26 0.425 V TH3 – UVLO 3.3 V bus – OVP latched – No sink (3) 0.48 0.65 V TH4 – UVLO 3.3 V bus – OVP latched – Sink (3) 0.71 0.875 V TH5 – UVLO 12 V bus – OVP not latched – No sink (3) 0.93 1.085 V 10/52 DocID15324 Rev 4 L5988D Electrical characteristics Table 5. Electrical characteristic (continued) Symbol Parameter Test condition Min. Typ. Max. Unit TH6 – UVLO 12 V bus – OVP not latched – Sink (3) 1.16 1.31 V TH7 – UVLO 12 V bus – OVP latched – No sink (3) 1.385 1.525 V TH8 – UVLO 12 V bus – OVP latched – Sink (3) 1.615 VREF V 1. Specification over the junction temperature range (TJ) of -40 to +125 °C are guaranteed by design, characterization and statistical correlation. 2. Guaranteed by design. 3. VCC = 4 V. DocID15324 Rev 4 11/52 52 Functional description 5 L5988D Functional description The L5988D is based on a voltage mode control loop. Therefore the duty ratio of the internal switch is obtained through a comparison between a saw-tooth waveform (generated by an oscillator) and the output voltage of the error amplifier as shown in Figure 3. The advantage of this technique is the very short conduction time of the power elements thanks to the proper operation of the control loop without a precise current sense, which instead is required in current mode regulators. Thanks to this architecture the L5988D supports extremely low conversion ratio (D = VOUT/VIN) even at very high switching frequency (up to 1 MHz). Figure 3. Voltage mode control loop V OUT OSCILLATOR RAMP + E/A + - V REF PWM The main internal blocks are represented in Figure 4. Figure 4. Internal block diagram 12/52 DocID15324 Rev 4 L5988D Functional description Below follows a brief description of the main blocks: 5.1  A voltage pre-regulator supplies the internal circuitry. The external 1.8 V voltage reference is supplied by this regulator.  A voltage monitor circuit that checks the input and internal voltages  A fully integrated sawtooth oscillator whose frequency is 400 kHz ± 10% when the Fsw pin is floating. Its frequency can be increased/decreased connecting a proper resistor to GND or VREF  The internal current limitation circuitry monitors the current flowing in both embedded switches to guarantee an effective protection even in extreme duty cycle conditions  The over voltage protection (OVP) monitors the feedback voltage. If the voltage of this pin overcomes the 20% of the internal reference value (600 mV ± 1%) it will force the conduction of the low side switch until the overshoot is present  A voltage mode amplifier. The inverting input and the output are externally available for compensation  A pulse width modulator (PWM) comparator and the relative logic to drive the embedded switches  The soft-start circuit charges an external capacitor with a constant current equal to 20 µA (typ.). The soft-start feature is realized clamping the output of the error amplifier until the voltage across the capacitor is below 2.7 V  The circuitry acting on the SYNCH pin provides external signal reference to slave devices when the regulator works as a master or accept the synchronization from an external reference source  The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and the decoding logic. It recognizes eight different voltage windows of a VREF voltage magnitude for selecting additional features.  An inhibit block for stand-by operation  A circuit to realize the thermal protection function Multifunction pin The UOS pin is used to configure the device additional features accordingly to the voltage bias imposed through VREF voltage partitioning. The selectable options are:  UVLO level: two pre-defined the under voltage lock out thresholds can be selected to match the 3.3 V and 5 V or 12 V power bus  SINK capability: this feature is always disabled during the soft-start period to be compatible with pre-biased output voltages. After the soft-start phase, the synchronous rectification can be enabled or not depending on the status of the UOS pin. Anyway, in case an overvoltage is detected, the sink capability is always enabled to bring the FB back to regulation as fast as possible  OVP management: in case the latched mode is selected and an overvoltage event recurs, the switching activity will be suspended until VCC is reapplied or the SS/INH pin is toggled. Otherwise when the overvoltage transient is ended the regulator will work accordingly to the load request without regulation discontinuity DocID15324 Rev 4 13/52 52 Functional description L5988D The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and the decoding logic. Table 6 shows the internal thresholds of each voltage window composing the VREF magnitude. The voltage biasing of the multifunction can be set accordingly to table Table 7. Table 6. A/D voltage windows 1.8 V 1.575 V 1.35 V 1.125 V 0.9 V 0.675 V 0.45 V 0.225 V 0V UVLO OVP SINK 12 V BUS LATCH SINK 12 V BUS LATCH NO SINK 12 V BUS NO LATCH SINK 12 V BUS NO LATCH NO SINK 3.3 V BUS LATCH SINK 3.3 V BUS LATCH NO SINK 3.3 V BUS NO LATCH SINK 3.3 V BUS NO LATCH NO SINK Table 7. UOS voltage biasing 14/52 R1 (k) R2 (k) VOUS (V) UVLO OVP SINK 0 N.C. 1.8 12 V BUS LATCH SINK 0.68 2.7 1.438 12 V BUS LATCH NO SINK 1.2 2.7 1.246 12 V BUS NO LATCH SINK 2 2.7 1.034 12 V BUS NO LATCH NO SINK 3.3 2.7 0.810 3.3 V BUS LATCH SINK 6.2 2.7 0.546 3.3 V BUS LATCH NO SINK 11 2.7 0.355 3.3 V BUS NO LATCH SINK N.C. 0 0 3.3 V BUS NO LATCH NO SINK DocID15324 Rev 4 L5988D 5.2 Functional description Oscillator and synchronization The generation of the internal saw-tooth waveform is based on the constant current charge / discharge of an internal capacitor. The current generator is designed to get a switching frequency of 400 kHz ± 10% in case the FSW pin is left floating. The current mirror connected to FSW (see Figure 5) pin acts increasing / decreasing the value of the internal charging current to adjust the oscillator frequency. Since the internal circuitry forces the FSW voltage bias at 1.235 V, the user can easily source / sink current in this pin connecting a pull up resistor to VREF or a pull down to GND respectively. Figure 5. Oscillator circuit block diagram VREF Clock Clock Generator Synchronization SYNCH Ramp Generator Sawtooth The value of the pull up resistor versus VREF to decrease the oscillator frequency follows the formula: Equation 1 3 8.5  10 R 1  K  = --------------------------------------------- + 0.95 400 – F SW  KHz  In the same way to increase the switching frequency the pull down resistor is selected using the formula: Equation 2 3 18  10 R 2  K  = --------------------------------------------- – 2.1 F SW  KHz  – 400 Table 11 on page 26 shows some resistor values to adjust the oscillator frequency. DocID15324 Rev 4 15/52 52 Functional description L5988D Table 8. FSW resistor examples R1 (k) fSW (kHz) R2 (k) fSW (kHz) 43 198 360 450 47 215 180 499 56 245 120 548 62 261 91 594 82 295 56 711 110 322 43 801 150 343 33 915 220 361 27 1022 To improve the line transient performance, the voltage feed forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 6 a). Figure 6. Sawtooth: voltage feed forward The slope of the sawtooth does not change if the oscillator frequency is increased by an external signal or adjusted by the external resistor (see Figure 7). As a consequence the gain of the PWM stage is a function of the switching frequency and its contribution must be taken in account when performing the calculations of the compensation network (see Section 6.4.1 on page 29 and Section 6.4.2 on page 33). Figure 7. Sawtooth: synchronization and frequency adjust 16/52 DocID15324 Rev 4 L5988D Functional description Beating frequency noise is an issue when more than one voltage rail is on the same board. A simple way to avoid this problem is to operate all the regulators at the same switching frequency. The synchronization feature of a set of L5988D is simply get connecting together their SYNCH pin. The device with highest switching frequency will be the MASTER and provides the synchronization signal to the others. Therefore the SYNCH is a I/O pin to deliver or recognize a frequency signal. In order to minimize the RMS current flowing through the input filter, the L5988D provides a phase shift of 180° between the master and the SLAVES. In cases where more than two devices are synchronized, all slaves will have a common 180° phase shift with respect to the master. In case the synchronized set shares a switching frequency different to the nominal 400 kHz, it is suggested to provide the proper FSW resistor to each device. In this way all the devices will have a common peak amplitude of the internal sawtooth signal so the same oscillator gain in the open loop gain transfer function. In this way the same compensation network is valid for all the devices. Taking in account the case of two synchronized L5988D regulating the same output voltage, the RMS current in the input filter will be optimized and will observe the following formula: Equation 3 I RMS I OUT  -----------  2D   1 – 2D   2 =   I OUT -   2D – 1    2 – 2D   ---------- 2 if D < 0.5 if D > 0.5 Multiple regulators can be also synchronized to an external frequency signal fed to the SYNCH pin. In this case the set is phased to the reference and all the devices will work with 0° phase shift. The graphical representation of the input RMS current of the input filter in the case of two devices with 0° phase shift (synchronized to an external signal) or 180° phase shift (synchronized connecting their SYNCH pins) regulating the same output voltage is provided in Figure 8. To dimension the proper input capacitor please refer to Section 6.1 on page 25. DocID15324 Rev 4 17/52 52 Functional description L5988D Figure 8. Input RMS current of two synchronized regulators 5.3 External voltage reference An external 1.8 V regulated voltage is provided. This reference is useful to set the voltage at the multifunction pin (see Section 5.1 on page 13) or to source current to ILIM-ADJ and FSW pins (seeSection 5.2 and Section 5.5.2). The typical current capability is 4 mA. 5.4 Soft-start When VCC is above the selected UVLO threshold the start-up phase takes place. At startup, a voltage ramp is generated charging the external capacitor CSS with an internal current generator. The device is in inhibit mode as long as SS/INH pin is below the INH threshold. The L5988D implements the soft-start phase by clamping the output of the error amplifier and, being based on a voltage mode control, the duty cycle. In fact the comparison between the output of the error amplifier and the internal saw tooth waveform generates the duty cycle needed to keep the output voltage in regulation. Two different current sources charge the external capacitor depending on the pin voltage in order to reduce the power consumption in INH mode. Equation 4  I SS1 = 5 A I SS =   I SS2 = 2 2A 0  V SS/INH  1 1  V SS/INH  2.9 The equation for the soft-start time is: Equation 5 C SS C SS T SS = T 1 + T 2 = -----------   1 – 0  + -----------   2.9 – 1  I SS1 I SS2 18/52 DocID15324 Rev 4 L5988D Functional description Considering ISS2/ISS1 = 22/5 = 4.4, the proper soft-start capacitor is simply calculated as follows: Equation 6 C  nF  = Tss  mS   3.5 During the soft-start phase (VSS < 2.9 V):  the sink capability is always disabled (independently from the multifunction pin settings) to be compatible with pre-biased output voltage  in case the overcurrent limit is detected, a constant current protection is provided in order to deliver extra current for charging the output capacitor (see Section 5.5.2 for description of current protection management). During normal operation the CSS is discharged with a constant current of 22 A (typ.) only if:  HICCUP mode is triggered (see Section 5.5.2)  the input voltage goes below the UVLO threshold (see Section 5.5.3)  the internal temperature is over 150°C (see Section 5.5.4) A new SS cycle will start when the VSS drops below the INH threshold. New high performance ICs often require more than one supply voltage. Most of these applications require well defined start-up sequencing, in order to avoid potential damage and latch-up of the processing core. Sharing the same soft-start capacitor for a set of regulators, the output voltages increase with the same slew rate implementing a “simultaneous start-up” sequencing method. 5.5 Monitoring and protections 5.5.1 Overvoltage The device provides the overvoltage protection monitoring the output voltage through the FB pin. If the voltage sensed on FB pin reaches a value 20% (typ.) greater than the reference of the error amplifier, the low-side MOSFET is turned on to discharge as fast as possible the output capacitor. It is possible to set two different behaviors in case of OVP:  In case the OVP latched mode is active (see Section 5.1 on page 13), the internal oscillator is suspended and the low side switch will be kept on until the input voltage goes below the selected UVLO threshold or the SS/INH pin is forced below the INH threshold.  In case of NOT latched OVP mode is active, the low side MOS is forced ON until the feedback voltage is higher than the OVP threshold (20% greater than the reference of the error amplifier). DocID15324 Rev 4 19/52 52 Functional description L5988D Figure 9. OVP not latched Figure 10. OVP latched 20/52 DocID15324 Rev 4 L5988D 5.5.2 Functional description Current limiting The current limiting feature acts in different ways depending on the operative conditions.  In case an overcurrent detection happens after the soft-start phase, the internal logic will trigger the “HICCUP” mode. Both switches are turned off and the soft-start capacitor is discharged with a constant current of 22 A (typ.). When the SS/INH voltage drops below the INH threshold a new SS cycle will start.  During the soft-start phase the overcurrent information is used to provide a constant current protection. In this way additional current is available to charge the output capacitor during power up. The most common way is to sense the current flowing through the power MOSFETs. However, due to the noise created by the switching activity of the power MOSFETs, the current sense is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. For this reason, the current cannot be sensed through the high-side MOSFET in the case of extremely low duty cycles, nor through the low-side MOSFET in the case of very high duty cycles. The L5988D assures the effective protection sensing the current flowing in both embedded switches. The protection achieved by sensing the current in the high-side MOSFET is called “peak overcurrent protection”, while the protection achieved by sensing the current in the low-side MOSFET is called “valley overcurrent protection”. When the current limit is reached during normal operation, the so called HICCUP mode is triggered, and the soft-start cap is discharged and recharged. However, during the start-up phase, additional current is required to charge the output capacitor. This could continuously trigger the HICCUP intervention preventing the system from reaching a steady working condition. For this reason the HICCUP feature is disabled during the start-up phase and a constant current mode is active to charge the output capacitor. In this case, when the peak current limit is triggered after a conduction time equal to the “masking time”, the high-side MOSFET is turned off and the low side MOSFET is kept on until the flowing current goes below the “valley” current limit. If necessary, some switching pulses are skipped, as illustrated in Figure 11. Thus, the combination of the “peak” and “valley” current limits assure the effectiveness of the overcurrent protection even in extreme duty cycle conditions. The current threshold of the low side is designed higher than the high side one to guarantee the proper protection. The constant current mode during the soft-start phase limits the maximum current up to: Equation 7 V IN – V OUT I MAX = I VALLEY_TH + ------------------------------  T MASK L The overcurrent limit protection is adjustable (higher or lower than the nominal value) through an external resistor. To guarantee effective protection, both thresholds (valley and peak) are in tracking. DocID15324 Rev 4 21/52 52 Functional description L5988D The typical active thresholds in case of ILIM-ADJ pin left floating are IPEAK_TH = 4.0 A, IVALLEY_TH = 4.7 A. The dimensioning of the pull up resistor versus VREF to decrease the peak (and valley) thresholds follows the formula: Equation 8 · 5 1.2  10 R 9    = ------------------------------------4.0 – I PEAK_TH In the same way the pull down resistor is selected using the following formula to increase the maximum current thresholds: Equation 9 5 · 2.706  10 R 3    = ------------------------------------I PEAK_TH – 4.0 Figure 11. Constant current protection at extreme duty cycles ZOOM skipped switching pulses Constant current protection during soft start time soft start time 22/52 HICCUP protection Is triggered at the end of the SS time Valley current limit DocID15324 Rev 4 L5988D Functional description Table 9 shows some resistor values to adjust the current limits Table 9. ILIM-ADJ resistor examples 5.5.3 R9(k) ILIM PEAK(A) ILIM VALLEY(A) R3(k) ILIM PEAK(A) ILIM VALLEY(A) 43 1.24 1.62 1500 4.2 4.75 47 1.47 1.87 750 4.38 4.95 56 1.88 2.31 470 4.6 5.18 68 2.26 2.71 330 4.8 5.42 91 2.71 3.18 270 5.0 5.62 120 3.03 3.52 220 5.20 5.82 200 3.43 3.94 180 5.50 6.12 560 3.81 4.35 160 5.70 6.30 UVLO The under-voltage-lockout (UVLO) is adjustable by the multifunction pin (see Section 5.1 on page 13). It is possible to set two different thresholds: 5.5.4  2.9 V for 3.3 V BUS  8 V for 12 V BUS Thermal shutdown When the junction temperature reaches 150 °C the device enters in thermal shutdown. Both MOSFETs are turned off and the soft-start capacitor is discharged with a current of 22 µA. The device doesn’t restart until the junction temperature goes down to 120 °C. 5.6 Minimum on time The L5988D is based on a voltage mode control loop. The advantage of this technique is the very short conduction time of the power elements thanks to the proper functioning of the control loop without a current sense (that is challenging with low conduction times), which instead is required in current mode regulators. The optimized architecture, the design solutions and the high performance fabrication technique allow power elements to achieve extremely short conduction times. This allows very high switching frequency operation even in very low duty cycle applications. Figure 12 shows how the L5988D can easily manage a minimum conduction time of 200ns. Moreover, thanks to the embedded P-MOS used for the high-side, no bootstrap capacitor is required. This means that the device is able to manage a duty cycle of 100%. DocID15324 Rev 4 23/52 52 Functional description L5988D Figure 12. Minimum TON 5.7 Error amplifier The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance. The uncompensated error amplifier characteristics are the following: Table 10. Uncompensated error amplifier Parameter description Value Low frequency gain 100 dB GBWP 4.5 MHz Slew rate 7 V/s Output voltage swing 0 to 3.3 V Maximum source/sink current 25 mA / 40 mA In continuous conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used. Otherwise, a type III compensation network has to be used (see Section 6.4 on page 28 for details about the compensation network selection). Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin. 24/52 DocID15324 Rev 4 L5988D Application information 6 Application information 6.1 Input capacitor selection The capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have a RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 10 2 2 2D D I RMS = I O  D – --------------- + ------2  Where Io is the maximum DC output current, D is the duty cycles, is the efficiency. This function has a maximum at D = 0.5 and, considering = 1, it is equal to Io/2. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 11 V OUT + V LOW_SIDE D MAX = -------------------------------------------------------------------------------------------------V INMIN + V LOW_SIDE – V HIGH_SIDE and Equation 12 V OUT + V LOW_SIDE D MIN = ---------------------------------------------------------------------------------------------------V INMAX + V LOW_SIDE – V HIGH_SIDE Where VHIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches. The peak to peak voltage across the input filter can be calculated as: Equation 13 IO D D V PP = -----------------------   1 – ----  D + ----   1 – D  + ESR  I O C IN  f SW    Given a physical dimension, ceramic capacitors can met well the requirements of the input filter substaining an higher input current than electrolytic / tantalum types. In this case the equation of CIN as a function of the target VPP can be written as follows: Equation 14 IO D D C IN = -------------------------   1 – ----  D + ----   1 – D  V PP  f SW    DocID15324 Rev 4 25/52 52 Application information L5988D Considering this function has its maximum in D = 0.5: Equation 15 IO C IN_MIN = ---------------------------------------------2  V PP_MAX  f SW Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 1% VIN_MAX. Table 11. Input capacitors Manufacture MURATA TDK 6.2 Series Cap value (F) Rated voltage (V) GRM31 10 25 GRM55 10 25 C3225 10 25 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple has to be selected. The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current. The inductance value can be calculated by the following equation: Equation 16 V IN – V OUT V OUT I L = ------------------------------  T ON = --------------  T OFF L L Where TON and TOFF are the on and off time of the internal power switch. The maximum current ripple, at fixed Vout, is obtained at maximum TOFF that is at minimum duty cycle (see previous section to calculate minimum duty). So fixing IL = 20% to 40% of the maximum output current, the minimum inductance value can be calculated: Equation 17 V OUT + V F 1 – D MIN L MIN = ----------------------------  ----------------------I MAX F SW where FSW is the switching frequency 1/(TON + TOFF). For example for VOUT = 3.3 V, VIN = 12 V, IO = 4 A and FSW = 400 kHz the minimum inductance value to have IL = 30% of IO is about 4.7 µH. The peak current through the inductor is given by: Equation 18 I L I L PK = I O + -------2 So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. The higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit. 26/52 DocID15324 Rev 4 L5988D Application information In Table 12 some inductor part numbers are listed. Table 12. Inductors Manufacturer Series Inductor value (H) Saturation current (A) XPL7030 2.2 to 4.7 6.8 to 10.5 MSS1048 2.2 to 6.8 4.14 to 6.62 MSS1260 10 5.5 WE-HC/HCA 3.3 to 4.7 7 to 11 WE-TPC type XLH 3.6 to 6.2 4.5 to 6.4 WE-PD type L 10 5.6 DR74 3.3 to 4.7 4.3 to 5.4 DR125 10 5.3 BI HM78-60 4.7 to 10 5.4 to 6.8 SUMIDA HM78-60 4.7 to 10 5.4 to 6.8 Coilcraft Wurth Coiltronics 6.3 Output capacitor selection The current in the capacitor has a triangular waveform (with zero average value) which generates a voltage ripple across it. This ripple is due to the capacitive component and the resistive component (ESR). So the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 19 I MAX V OUT = ESR  I MAX + ------------------------------------8  C OUT  f SW Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR value. The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In Section 6.4, it will be illustrated how to consider its effect in the system stability. For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.6 A (resulting by the inductor value), in order to have a VOUT = 0.01·VOUT, if the multi layer capacitor are adopted, 10 µF are needed and the ESR effect on the output voltage ripple can be neglected. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So 100 µF with ESR = 40 mis compliant with the requested output voltage ripple The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application the output capacitor and system bandwidth DocID15324 Rev 4 27/52 52 Application information L5988D have to be chosen in order to sustain load transient and to have a fast response to the transient. In Table 13 some capacitor series are listed. Table 13. Output capacitors Manufacturer Series Cap value (F) Rated voltage (V) ESR (m) GRM32 22 to 100 6.3 to 25
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