L5991AD

® L5991 L5991A PRIMARY CONTROLLER WITH STANDBY CURRENT-MODE CONTROL PWM SWITCHING FREQUENCY UP TO 1MHz LOW START-UP CURRENT (< 120µA) HIGH-CURRENT OUTPUT DRIVE SUITABLE FOR POWER MOSFET (1A) FULLY LATCHED PWM LOGIC WITH DOUBLE PULSE SUPPRESSION PROGRAMMABLE DUTY CYCLE 100% AND 50% MAXIMUM DUTY CYCLE LIMIT STANDBY FUNCTION PROGRAMMABLE SOFT START PRIMARY OVERCURRENT FAULT DETECTION WITH RE-START DELAY PWM UVLO WITH HYSTERESIS IN/OUT SYNCHRONIZATION LATCHED DISABLE INTERNAL 100ns LEADING EDGE BLANKING OF CURRENT SENSE PACKAGE: DIP16 AND SO16 DESCRIPTION This primary controller I.C., developed in BCD60II technology, has been designed to implement off BLOCK DIAGRAM SYNC 1 RCT 2 TIMING 25V DC-LIM 15 MULTIPOWER BCD TECHNOLOGY DIP16 SO16 ORDERING NUMBERS: L5991/L5991A (DIP16) L5991D/L5991AD (SO16) line or DC-DC power supply applications using a fixed frequency current mode control. Based on a standard current mode PWM controller this device includes some features such as programmable soft start, IN/OUT synchronization, disable (to be used for over voltage protection and for power management), precise maximum Duty Cycle Control, 100ns leading edge blanking on current sense, pulse by pulse current limit, overcurrent protection with soft start intervention, and Standby function for oscillator frequency reduction when the converter is lightly loaded. VCC 8 VREF 4 DC 3 + T DIS Vref + 15V/10V - PWM UVLO 9 VC DIS 2.5V 13V BLANKING S R PWM OVER CURRENT ISEN 13 + FAULT SOFT-START SS 1.2V 7 August 2001 + 10 OUT Q VREF OK CLK DIS - 14 VREF 11 16 PGND ST-BY STAND-BY + E/A 2.5V 2R 1V R 12 SGND 6 COMP - 5 VFB D97IN725A 1/23 L5991 - L5991A ABSOLUTE MAXIMUM RATINGS Symbol VCC IOUT Parameter Supply Voltage (ICC < 50mA) (*) Output Peak Pulse Current Analog Inputs & Outputs (6,7) Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16) Power Dissipation @ Tamb = 70°C (DIP16) @ Tamb = 50°C (SO16) Junction Temperature, Operating Range Storage Temperature, Operating Range Value selflimit 1.5 -0.3 to 8 -0.3 to 6 1 0.83 -40 to 150 -55 to 150 Unit V A V V W W °C °C Ptot Tj Tstg (*) maximum package power dissipation limits must be observed PIN CONNECTION SYNC RCT DC VREF VFB COMP SS V CC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ST-BY DC-LIM DIS ISEN SGND PGND OUT VC THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction -Ambient (DIP16) Thermal Resistance Junction -Ambient (SO16) Value 80 120 Unit °C/W °C/W PIN FUNCTIONS N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name SYNC RCT DC VREF VFB COMP SS VCC VC OUT PGND SGND ISEN DIS DC-LIM ST-BY Function Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct Oscillator pin for external CT, RA, RB components Duty Cycle control 5.0V +/-1.5% reference voltage @ 25°C Error Amplifier Inverting input Error Amplifier Output Soft start pin for external capacitor Css Supply for internal "Signal" circuitry Supply for Power section High current totem pole output Power ground Signal ground Current sense Disable. It must never be left floating. TIE to SGND if not used. Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is imposed Standby. Connect a resistor to RCT. Connect to VREF or floating if not used. 2/23 L5991 - L5991A ELECTRICAL CHARACTERISTICS (VCC = 15V; Tj = 0 to 105°C; RT = 13.3kΩ (*) CT = 1nF; unless otherwise specified.) Symbol Parameter REFERENCE SECTION VREF Output Voltage Line Regulation Load Regulation TS Temperature Stability Total Variation Short Circuit Current IOS Power Down/UVLO OSCILLATOR SECTION Initial Accuracy Test Condition Tj = 25°C; IO = 1mA VCC = 12 to 20V; T j = 25°C IO = 1 to 10mA; Tj = 25°C Line, Load, Temperature Vref = 0V VCC = 6V; Isink = 0.5mA pin 15 = Vref; Tj = 25°C; Vcomp = 4.5V pin 15 = Vref; VCC = 12 to 20V Vcomp = 4.5V pin 15 = Vref; VCC = 12 to 20V Vcomp = 2V pin 3 = 0,7V, pin 15 = VREF pin 3 = 0.7V, pin 15 = OPEN pin 3 = 3.2V, pin 15 = VREF pin 3 = 3.2V, pin 15 = OPEN pin 3 = 2.79V, pin 15 = OPEN Min. 4.925 Typ. 5.0 2.0 2.0 0.4 5.0 0.2 95 93 46.5 100 100 50 Max. 5.075 10 10 5.130 150 0.5 105 107 53.5 0 0 47 93 75 2.8 0.75 Unit V mV mV mV/°C V mA V kHz kHz kHz % % % % % V V µA V dB dB V V mA mA MHz V/µs µA V ns V/V V µA µA V V ns 1.0 10 9 10.5 10 13 2 V V V V µA 4.80 30 Duty Cycle Duty Cycle Accuracy Oscillator Ramp Peak Oscillator Ramp Valley ERROR AMPLIFIER SECTION Input Bias Current VI Input Voltage Open Loop Gain GOPL SVR Supply Voltage Rejection Output Low Voltage VOL VOH Output High Voltage Output Source Current IO Output Sink Current Unit Gain Bandwidth Slew Rate SR PWM CURRENT SENSE SECTION Input Bias Current Ib IS Maximum Input Signal Delay to Output Gain Fault Threshold Voltage Vt SOFT START SECTION SS Charge Current ISSC ISSD SS Discharge Current SS Saturation Voltage VSSSAT VSSCLAMP SS Clamp Voltage LEADING EDGE BLANKING Internal Masking Time OUTPUT SECTION Output Low Voltage VOL Output High Voltage VOH VOUT CLAMP Output Clamp Voltage Collector Leakage 80 3.0 0.9 0.2 2.5 90 85 6 1.3 6 4 8 3 1.0 70 3 1.2 20 10 7 100 85 3.2 1.05 3.0 2.58 VFB to GND VCOMP = VFB VCOMP = 2 to 4V VCC = 12 to 20V Isink = 2mA Isource = 0.5mA, VFB = 2.3V VCOMP > 4V, VFB = 2.3V VCOMP = 1.1V, VFB = 2.7V 2.42 60 1.1 5 0.5 2 1.7 2.5 Isen = 0 VCOMP = 5V 0.92 2.85 1.1 15 1.08 100 3.15 1.3 26 15 0.6 Tj = 25°C VSS = 0.6V Tj = 25°C DC = 0% 14 5 IO = 250mA IO = 20mA; VCC = 12V IO = 200mA; VCC = 12V IO = 5mA; VCC = 20V VCC = 20V VC = 24V 20 (*) RT = RA//RB, RA = RB = 27kΩ, see Fig. 23. 3/23 L5991 - L5991A ELECTRICAL CHARACTERISTICS (continued.) Symbol Parameter OUTPUT SECTION Fall Time Rise Time UVLO Saturation SUPPLY SECTION Startup voltage VCCON VCCOFF Vhys IS Iop Iq Minimum Operating Voltage UVLO Hysteresis Start Up Current Operating Current Quiescent Current Test Condition CO = 1nF CO = 2.5nF CO = 1nF CO = 2.5nF VCC = VC = 0 to VCCON; Isink = 10mA L5991 L5991A L5991 L5991A L5991 L5991A Before Turn-on at: VCC = VC = VCCON -0.5V CT = 1nF, RT = 13.3kΩ, CO =1nF (After turn on), CT = 1nF, RT = 13.3kΩ, CO =0nF I8 = 20mA IST-BY = 2mA Vcomp Falling Vcomp Rising Master Operation ISOURCE = 0.8mA Vclock = 3.5V Slave Operation Low Level High Level VSYNC = 3.5V 14 7.8 9 7 4.5 0.5 40 Min. Typ. 20 35 50 70 Max. 60 100 1.0 15 8.4 10 7.6 5 0.8 75 9 7.0 21 25 45 2.5 4.0 16 9 11 8.2 Unit ns ns ns ns V V V V V V V µA mA mA V mV V V 120 13 10 30 VZ Zener Voltage STANDBY FUNCTION VREF-VST-BY Standby Threshold VT1 SYNCHRONIZATION SECTION V1 I1 V1 Clock Amplitude Clock Source Current Sync Pulse 4 3 7 1 V mA V V mA V V µA µA Sync Pulse Current I1 OVER CURRENT PROTECTION Fault Threshold Voltage Vt DISABLE SECTION Shutdown threshold Input Bias Current Quiescent current After IqSH Disable 3.5 0.5 1.1 2.4 -1 1.2 2.5 330 1.3 2.6 1 Vpin14 = 0 to 3V VCC = 15V Figure 1. L5991 - Quiescent current vs. input voltage. (X = 7.6V and Y= 8.4V for L5991A) Iq [m A ] 30 Figure 2. L5991 - Quiescent current vs. input voltage (after disable). (X = 7.6V and Y= 8.4V for L5991A) Iq [µ A ] 350 20 8 6 4 0 .2 0 .1 5 0 .1 0 .0 5 0 0 4 V 1 4 = 0 , P in 2 = o p e n T j = 2 5 °C 300 250 200 150 100 V 1 4 = V ref T j = 2 5 °C X Y X Y 50 0 0 4 8 8 12 16 V c c [V ] 20 24 28 12 16 V c c [V ] 20 24 4/23 L5991 - L5991A Figure 3. Quiescent current vs. input voltage. Iq [m A ] 9 .0 V 14 = 0, V 5 = V ref R t = 4.5Koh m ,T j = 25 °C 8 .5 1 M hz 5 00K hz 3 00K hz 1 00K hz Figure 4. Quiescent current vs. input voltage and switching frequency. Iq [m A ] 36 30 24 1 M Hz C o = 1 nF, T j = 25°C D C = 0% 8 .0 18 5 00 K H z 12 7 .5 3 00 K H z 1 00 K H z 6 0 8 10 12 14 16 18 V c c [V ] 20 22 24 7 .0 8 10 12 14 16 V cc [V ] 18 20 22 Figure 5. Quiescent current vs. input voltage and switching frequency. Iq [mA] 36 Co = 1nF, Tj = 25°C Figure 6. IC Consumption vs. Temperature. [mA] 100 Operating current Vcc =15V, after turn-on RT=13.3kΩ, CT=1nF DC=75%, Co=1nF Quiescent current Vcc =15V, after turn-on RT=13.3 kΩ, CT=1nF DC = 0 30 24 18 12 DC = 100% 1MHz 10 500KHz 1 300KHz 100KHz 0.1 6 0 8 10 12 14 16 Vcc [V] 18 20 22 0.01 -50 Start-up current Vc=Vcc= Vccon-0.5V, before turn-on -25 0 25 50 75 100 125 150 Junction temperature [˚C] Figure 7. Reference voltage vs. load current. Vref [V] 5.1 Figure 8. Vref vs. junction temperature. Vref [V]) 5.1 5.05 Vcc=15V Tj = 25°C 5.05 Vcc = 15V Iref = 1mA 5 5 4.95 4.95 4.9 0 5 10 Iref [mA] 15 20 25 4.9 -50 -25 0 25 50 Tj (°C) 75 100 125 150 5/23 L5991 - L5991A Figure 9. Vref vs. junction temperature. Vref [V] 5.1 Vcc = 15V Figure 10. Vref SVRR vs. switching frequency. SVRR (dB) 120 Vcc=15V Vp-p=1V 5.05 Iref= 20mA 80 5 4.95 40 4.9 -50 -25 0 25 50 Tj (°C) 75 100 125 150 0 1 10 100 1000 fsw (Hz) 10000 Figure 11. Output saturation. Vsat = V 10 Figure 12. Output saturation. V sat = V10 [V] 2.5 [V] 16 Vcc = Vc = 15V 14 Tj = 25°C 2 1.5 1 0.5 0 Vc c = Vc = 15V T j = 25°C 12 10 8 6 0 0.2 0.4 0.6 0.8 Isource [A] 1 1.2 0 0.2 0.4 0.6 Isink [A ] 0.8 1 1.2 Figure 13. UVLO Saturation Ipin10 [mA] 50 40 30 20 10 Vcc < Vccon before turn-on Figure 14. Timing resistor vs. switching frequency. fsw (KHz) 5000 Vcc = 15V, V15 =0V 2000 Tj = 25°C 1000 500 100pF 200 220pF 100 470pF 50 20 5.6nF 2.2nF 1nF 0 0 200 400 600 800 Vpin10 [mV] 1,000 1,200 1,400 10 10 20 Rt (kohm) 30 40 6/23 L5991 - L5991A Figure 15. Switching frequency vs. temperature. fsw (KHz) 320 Rt= 4.5Kohm, Ct = 1nF Figure 16. Switching frequency vs. temperature. fsw (KHz) 320 Rt= 4.5Kohm, Ct = 1nF 310 310 Vcc = 15V, V15=Vref Vcc = 15V, V15= 0 300 300 290 290 280 -50 -25 0 25 50 Tj (°C) 75 100 125 150 280 -50 -25 0 25 50 Tj (°C) 75 100 125 150 Figure 17. Dead time vs Ct. Dead time [ns] Figure 18. Maximum Duty Cycle vs Vpin3. DC Control Voltage Vpin3 [V] 3.5 V15 = Vref V15 = 0V 1,500 1,200 Rt =4.5Kohm V15 = 0V 3 2.5 900 V15 = Vref 2 Rt = 4.5Kohm, 600 1.5 300 Ct = 1nF 1 2 4 6 8 Timing capacitor Ct [nF] 10 0 10 20 30 40 50 60 70 Duty Cycle [%] 80 90 100 Figure 19. Delay to output vs junction temperature. Delay to output (ns) 42 Figure 20. E/A frequency response. G [dB] 150 Phase 140 40 38 36 120 100 100 80 34 32 30 28 -50 PIN10 = OPEN 1V pulse on PIN13 50 60 0 40 -25 0 25 50 Tj (°C) 75 100 125 150 20 0.01 0.1 1 10 100 f (KHz) 1000 10000 100000 7/23 L5991 - L5991A STANDBY FUNCTION The standby function, optimized for flyback topology, automatically detects a light load condition for the converter and decreases the oscillator frequency on that occurrence. The normal oscillation frequency is automatically resumed when the output load builds up and exceeds a defined threshold. This function allows to minimize power losses related to switching frequency, which represent the majority of losses in a lightly loaded flyback, without giving up the advantages of a higher switching frequency at heavy load. This is accomplished by monitoring the output of the Error Amplifier (VCOMP) that depends linearly on the peak primary current, except for an offset. If the the peak primary current decreases (as a result of a decrease of the power demanded by the load) and VCOMP falls below a fixed threshold (VT1), the oscillator frequency will be set to a lower value (fSB). When the peak primary current increases and VCOMP exceeds a second threshold (VT2) the oscillator frequency is set to the normal value (fosc). An appropriate hysteresis (VT2-VT1) prevents undesired frequency change when power is such that VCOMP moves close to the threshold. This operation is shown in fig. 21. Both the normal and the standby frequency are externally programmable. VT1 and VT2 are internally fixed but it is possible to adjust the thresholds in terms of input power level. APPLICATION INFORMATION Detailed Pin Function Description Pin 1. SYNC (In/Out Synchronization). This function allows the IC’s oscillator either to synchronize other controllers (master) or to be synchronized to an external frequency (slave). As a master, the pin delivers positive pulses during the falling edge of the oscillator (see pin 2). In slave operation the circuit is edge triggered. Refer to fig. 23 to see how it works. When several IC work in parallel no master-slave designation is needed because the fastest one becomes autoFigure 22. Synchronizing the L5991. RB SYNC 1 L5991 2 RCT CT 16 4 VREF RA ST-BY 1 L5991 2 RCT ROSC COSC SYNC L4981A (MASTER) 16 17 18 RCT CT ST-BY 16 L5991 (SLAVE) 4 1 2 RB VREF RA RCT 4 2 L5991 1 (MASTER) 16 ST-BY ROSC COSC RA VREF SYNC SYNC L4981A (SLAVE) 16 17 18 Figure 21. Standby dynamic operation. Pin fosc Normal operation PNO fSB PSB 1 2 VT1 Stand-by 3 VT2 4 VCOMP matically the master. During the ramp-up of the oscillator the pin is pulled low by a 600µA internal sink current generator. During the falling edge, that is when the pulse is released, the 600µA pull-down is disconnected. The pin becomes a generator whose source capability is typically 7mA (with a voltage still higher than 3.5V). In fig. 22, some practical examples of synchronizing the L5991 are given. Since the device automatically diminishes its operating frequency under light load conditions, it is reasonable to suppose that synchronization will refer to normal operation and not to standby. Pin 2. RCT (Oscillator). Two resistors (RA and RB) and one capacitor (CT), connected as shown in fig. 23, allow to set separately the operating frequency of the oscillator in normal operation (fosc) and in standby mode (fSB). CT is charged from Vref through RA and RB in normal operation (STANDBY = HIGH), through RA only in standby ( STANDBY = LOW). See pin 16 description to see how the STANDBY signal is generated. When the voltage on CT reaches 3V, the capacitor is quickly internally discharged. As the voltage has dropped to 1V it starts being charged again. SYNC RB CT (a) (b) D97IN728A (c) 8/23 L5991 - L5991A Figure 23. Oscillator and synchronization internal schematic. SYNC VREF 4 1 R1 CLAMP RA RCT 2 D1 50Ω ST-BY 16 STANDBY D97IN729A D R 600µA + - Q R3 R2 CLK RB CT The oscillation frequency can be established with the aid of the diagrams of fig. 14, where RT will be intended as the parallel of RA and RB in normal operation and RT = RA in standby, or considering the following approximate relationships: fosc ≅ 1 CT ⋅ (0.693 ⋅ (RA // RB) + KT (1), from fig. 14 or resulting from (1) and (2). To prevent the oscillator frequency from switching back and forth from fosc to fSB, the ratio fosc / fSB must not exceed 5.5. If during normal operation the IC is to be synchronized to an external oscillator, RA, RB and CT should be selected for a fosc lower than the master frequency in any condition (typically, 10-20% ), depending also on the tolerance of the parts. Pin 3. DC (Duty Cycle Control). By biasing this pin with a voltage between 1 and 3 V it is possible to set the maximum duty cycle between 0 and the upper extreme Dx (see pin 15). If Dmax is the desired maximum duty cycle, the voltage V3 to be applied to pin 3 is: V3 = 5 - 2(2-Dmax) (5) Dmax is determined by internal comparison between V3 and the oscillator ramp (see fig. 24), thus in case the device is synchronized to an external frequency fext (and therefore the oscillator amplitude is reduced), (5) changes into: Dmax   V3 = 5 − 4 ⋅ exp  − (6) RT ⋅ CT ⋅ fext    A voltage below 1V will inhibit the driver output stage. This could be used for a not-latched device disable, for example in case of overvoltage protection (see application ideas). If no limitation on the maximum duty cycle is required (i.e. DMAX = DX), the pin has to be left floating. An internal pull-up (see fig. 24) holds the voltage above 3V. Should the pin pick up noise (e.g. 9/23 which gives the normal operating frequency, and: 1 fSB ≅ CT ⋅ (0.693 ⋅ RA + KT) (2), which gives the standby frequency, that is the one the converter will operate at when lightly loaded. In the above expressions, RA // RB means: RA ⋅ RB RA//RB = , RA + RB while KT is defined as: 90 V15 = VREF (3), KT =  160 V15 = GND/OPEN and is related to the duration of the falling-edge of the sawtooth: Td ≈ 30 ⋅ 10−9 + KT ⋅ CT (4). Td is also the duration of the sync pulses delivered at pin 1 and defines the upper extreme of the duty cycle range, Dx (see pin 15 for DX definition and calculation) since the output is held low during the falling edge. In case V15 is connected to VREF, however, the switching frequency will be a half the values taken L5991 - L5991A during ESD tests), it can be connected to VREF through a 4.7kΩ resistor. Figure 24. Duty cycle control. duce the oscillator frequency when the converter is lightly loaded (standby). Pin 7. SS (Soft-Start). At device start-up, a capacitor (Css) connected between this pin and SGND (pin 12) is charged by an internal current generator, ISSC, up to about 7V. During this ramp, the E/A output is clamped by the voltage across Css itself and allowed to rise linearly, starting from zero, up to the steady-state value imposed by the control loop. The maximum time interval during which the E/A is clamped, referred to as soft-start time, is approximately: 3 ⋅ Rsense ⋅ IQpk ⋅ Css (7) ISSC where Rsense is the current sense resistor (see pin 13) and IQpk is the switch peak current (flowing through Rsense), which depends on the output load. Usually, CSS is selected for a TSS in the order of milliseconds. As mentioned before, the soft-start intervenes also in case of severe overload or short circuit on the output. Referring to fig. 25, pulse-by-pulse current limitation is somehow effective as long as Tss ≅ Figure 25. Regulation characteristic and related quantities. VOUT D.C.M. C.C.M. A IQpk 1-2 ·IQpk IQpk(max) B TON D TON(min) D97IN495 VREF R1 DC 4 3µA 3 23K RA R2 28K ST-BY 16 2 RB RCT + - TO PWM LOGIC CT D97IN727A Pin 4. VREF (Reference Voltage). The device is provided with an accurate voltage reference (5V±1.5%) able to deliver some mA to an external circuit. A small film capacitor (0.1 µF typ.), connected between this pin and SGND, is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. Before device turn-on, this pin has a sink current capability of 0.5mA. Pin 5. VFB (Error Amplifier Inverting Input). The feedback signal is applied to this pin and is compared to the E/A internal reference (2.5V). The E/A output generates the control voltage which fixes the duty cycle. The E/A features high gain-bandwidth product, which allows to broaden the bandwidth of the overall control loop, high slew-rate and current capability, which improves its large signal behavior. Usually the compensation network, which stabilizes the overall control loop, is connected between this pin and COMP (pin 6). Pin 6. COMP (Error Amplifier Output). Usually, this pin is used for frequency compensation and the relevant network is connected between this pin and VFB (pin 5). Compensation networks towards ground are not possible since the L5991 E/A is a voltage mode amplifier (low output impedance). See application ideas for some example of compensation techniques. It is worth mentioning that the calculation of the part values of the compensation network must take the standby frequency operation into account. In particular, this means that the open-loop crossover frequency must not exceed fSB/4 ÷ fSB/5. The voltage on pin 6 is monitored in order to re10/23 C ISHORT IOUT(max) IOUT the ON-time of the power switch can be reduced (from A to B). After the minimum ON-time is reached (from B onwards) the current is out of control. To prevent this risk, a comparator trips an overcurrent handling procedure, named ’hiccup’ mode operation, when a voltage above 1.2V (point C) is detected on current sense input (ISEN, pin 13). Basically, the IC is turned off and then soft-started as long as the fault condition is detected. As a result, the operating point is moved abruptly to D, creating a foldback effect. Fig. 26 illustrates the operation. The oscillation frequency appearing on the softstart capacitor in case of permanent fault, referred to as ’hiccup" period, is approximately given by: Thic ≅ 4.5 ⋅  1 ISSC + 1 ⋅ Css (8) ISSD   L5991 - L5991A Since the system tries restarting each hiccup cycle, there is not any latchoff risk. "Hiccup" keeps the system in control in case of short circuits but does not eliminate power components overstress during pulse-by-pulse limitation (from A to C). Other external protection circuits are needed if a better control of overloads is required. Pin 8. VCC (Controller Supply). This pin supplies the signal part of the IC. The device is enabled as VCC voltage exceeds the start threshold and works as long as the voltage is above the UVLO threshold. Otherwise the device is shut down and the current consumption is extremely low (