L5993

® L5993 CONSTANT POWER CONTROLLER CURRENT-MODE CONTROL PWM SWITCHING FREQUENCY UP TO 1MHz LOW START-UP CURRENT (< 120µA) CONSTANT OUTPUT POWER VS. SWITCHING FREQUENCY HIGH-CURRENT OUTPUT DRIVE SUITABLE FOR POWER MOSFET (1A) FULLY LATCHED PWM LOGIC WITH DOUBLE PULSE SUPPRESSION PROGRAMMABLE DUTY CYCLE 100%AND 50% MAXIMUM DUTY CYCLE LIMIT PROGRAMMABLE SOFT START PRIMARY OVERCURRENT FAULT DETECTION WITH RE-START DELAY PWM UVLO WITH HYSTERESIS IN/OUT SYNCHRONIZATION LATCHED DISABLE INTERNAL 100ns LEADING EDGE BLANKING OF CURRENT SENSE PACKAGE: DIP16 AND SO16N DESCRIPTION This primary controller I.C., developed in BCD60II technology, has been designed to implement off BLOCK DIAGRAM SYNC 1 RCT 2 TIMING + + 2.5V C-POWER 16 + BLANKING T DIS DC-LIM 15 MULTIPOWER BCD TECHNOLOGY DIP16 SO16N ORDERING NUMBERS: L5993 (DIP16) L5993D (SO16) line or DC-DC power supply applications using a fixed frequency current mode control. Based on a standard current mode PWM controller this device includes some features such as programmable soft start, IN/OUT synchronization, disable (to be used for over voltage protection and for power management), precise maximum Duty Cycle Control, 100ns leading edge blanking on current sense, pulse by pulse current limit, overcurrent protection with soft start intervention and ”constant power” function for cotrolling throughput power in multisync monitor SMPS. VCC 8 VREF 4 25V + 15V/10V PWM UVLO Vref DC 3 DIS 14 9 VC 13V S R PWM 10 OUT Q OVER CURRENT ISEN 13 + 1.2V 7 2R 1V R FAULT SOFT-START VREF OK CLK DIS 11 PGND SS + E/A 2.5V - 5 VFB 12 SGND 6 COMP D97IN765 July 1999 1/22 L5993 ABSOLUTE MAXIMUM RATINGS Symbol VCC IOUT Parameter Supply Voltage (ICC < 50mA) (*) Output Peak Pulse Current Analog Inputs & Outputs (6,7) Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16) Power Dissipation @ Tamb = 70°C (DIP16) @ Tamb = 50°C (SO16) Junction Temperature, Operating Range Storage Temperature, Operating Range Value selflimit 1.5 -0.3 to 8 -0.3 to 6 1 0.83 -40 to 150 -55 to 150 Unit V A V V W W °C °C Ptot Tj Tstg (*) maximum package power dissipation limits must be observed PIN CONNECTION SYNC RCT DC VREF VFB COMP SS VCC 1 2 3 4 5 6 7 8 D97IN783 16 15 14 13 12 11 10 9 C-POWER DC-LIM DIS ISEN SGND PGND OUT VC THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction -Ambient (DIP16) Thermal Resistance Junction -Ambient (SO16) Value 80 120 Unit °C/W °C/W PIN FUNCTIONS N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name SYNC RCT DC VREF VFB COMP SS VCC VC OUT PGND SGND ISEN DIS DC-LIM C-POWER Function Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct Oscillator pin for external Ct, Rt components Duty Cycle control 5.0V +/-1.5% reference voltage at 25°C Error Amplifier Inverting input Error Amplifier Output Soft start pin for external capacitor Css Supply for internal ”Signal” circuitry Supply for Power section High current totem pole output Power ground Signal ground Current sense Disable. It must never be left floating. Tie to SGND if not used. Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is imposed Constant Power vs. Switching Frequency. Connect a capacitor to SGND. The pin must be connected to VREF if not used. 2/22 L5993 ELECTRICAL CHARACTERISTICS (VCC = 15V; Tj = 0 to 105°C; RT = 13.3kΩ; CT = 1nF unless otherwise specified.) Symbol VRef Parameter Output Voltage Line Regulation Load Regulation TS IOS Temperature Stability Total Variation Short Circuit Current Power Down/UVLO OSCILLATOR SECTION Initial Accuracy Duty Cycle Duty Cycle Duty Cycle Accuracy Oscillator Ramp Peak Oscillator Ramp Valley ERROR AMPLIFIER SECTION Input Bias Current VI GOPL SVR V OL VOH IO Input Voltage Open Loop Gain Supply Voltage Rejection Output Low Voltage Output High Voltage Output Source Current Output Sink Current Unit Gain Bandwidth SR Ib IS Slew Rate Input Bias Current Maximum Input Signal Delay to Output Gain SOFT START ISSC ISSD VSSSAT VSSCLAMP SS Charge Current SS Discharge Current SS Saturation Voltage SS Clamp Voltage Internal Masking Time OUTPUT SECTION V OL VOH VOUT CLAMP Output Low Voltage Output High Voltage Output Clamp Voltage IO = 250mA IO = 20mA; VCC = 12V IO = 200mA; VCC = 12V IO = 5mA; VCC = 20V 10 9 10.5 10 13 1.0 V V V V 3/22 VSS = 0.6V, Tj = 25°C DC = 0% 7 100 14 5 20 10 26 15 0.6 µA µA V V ns 2.85 Isen = 0 VCOMP = 5V 0.92 PWM CURRENT SENSE SECTION 3 1.0 70 3 15 1.08 100 3.15 µA V ns V/V VFB to GND VCOMP = VFB VCOMP = 2 to 4V VCC = 12 to 20V Isink = 2mA, VFB = 2.7V Isou rce = 0.5mA, VFB = 2.3V VCOMP > 4V, VFB = 2.3V VCOMP > 1.1V, VFB = 2.7V 5 0.5 2 1.7 6 1.3 6 4 8 2.5 2.42 60 pin 15 = Vref Tj = 25°C V CC = 12 to 20V 95 93 100 100 105 107 0 0 47 93 75 2.8 0.75 80 3.0 0.9 0.2 2.5 90 85 1.1 85 3.2 1.05 3.0 2.58 kHz kHz % % % % % V V µA V dB dB V V mA mA MHz V/µs Line, Load, Temperature Vref = 0V VCC = 8.5V; Isink = 0.5mA 4.80 30 0.2 Test Condition Tj = 25°C; IO = 1mA VCC = 12 to 20V; Tj = 25°C IO = 1 to 10mA; Tj = 25°C Min. 4.925 Typ. 5.0 2.0 2.0 0.4 5.0 5.130 150 0.5 Max. 5.075 10 10 Unit V mV mV mV/°C V mA V REFERENCE SECTION pin 3 = 0,7V, pin 15 = Vref pin 3 = 0.7V, pin 15 = OPEN pin 3 = 3.2V, pin 15 = Vref pin 3 = 3.2V, pin 15 = OPEN pin 3 = 2.79V, pin 15 = OPEN LEADING EDGE BLANKING L5993 ELECTRICAL CHARACTERISTICS (continued.) Symbol OUTPUT SECTION Collector Leakage Fall Time Rise Time UVLO Saturation SUPPLY SECTION VCCON VCCOFF Vhys IS Iop Iq VZ Startup voltage Minimum Operating Voltage ULVO Hysteresis Start Up Current Operating Current Quiescent Current Zener Voltage Before Turn-on at: VCC = VCCON - 0.5V CT = 1nF,RT = 13.3kΩ, CO =1nF (After turn on), CT = 1nF, R T = 13.3kΩ, C O = 0nF I8 = 20mA Master Operation V1 I1 V1 I1 Vt Clock Amplitude Clock Source Current Sync Pulse Sync Pulse Current Fault Threshold Voltage Shutdown threshold ISH Shutdown Current VCC = 15V CONSTANT POWER ISOURCE = 0.8mA Vclock = 3.5V Slave Operation Low Level High Level VSYNC = 3.5V OVER CURRENT PROTECTION 1.1 2.4 1.2 2.5 330 1.3 2.6 V V µA DISABLE SECTION 3.5 0.5 1 V V mA 4 3 7 V mA 21 14 9 4.5 40 15 10 5 75 9 7.0 25 120 13 10 30 16 11 V V V µA mA mA V VCC = 20V VC = 24V C O = 1nF C O = 2.5nF C O = 1nF C O = 2.5nF VCC = 0V to VCCON; Isink = 10mA 2 20 35 50 70 20 60 100 1.0 µA ns ns ns ns V Parameter Test Condition Min. Typ. Max. Unit SYNCHRONIZATION SECTION Figure 1. Quiescent current vs. input voltage. 30 20 8 6 4 0.2 0.15 0.1 0.05 0 0 4/22 4 8 12 16 Vcc [V] 20 24 28 Iq [mA] V14 = 0, Pin2 = open Tj = 25 °C Figure 2. Quiescent current vs. input voltage (after disable). 350 300 250 200 150 100 50 0 0 4 8 12 16 Vcc [V] 20 24 V14 = Vref Tj = 25 ° C Iq [µA] L5993 Figure 3. Quiescent current vs. input voltage. Iq [m A ] 9 .0 V 1 4 = 0 , V 5 = V re f 8 .5 R t = 4 .5 K o h m ,T j = 2 5 ° C 1M hz 5 00K hz 300K hz 100K hz Figure 4. Quiescent current vs. input voltage and switching frequency. Iq [m A ] 36 30 24 1M H z C o = 1 n F, T j = 2 5 ° C D C = 0% 8 .0 18 50 0K H z 12 7 .5 30 0K H z 1 00K H z 6 7 .0 8 10 12 14 16 18 V c c [V ] 20 22 24 0 8 10 12 14 16 V cc [ V ] 18 20 22 Figure 5. Quiescent current vs. input voltage and switching frequency. Iq [mA] 36 Co = 1nF, Tj = 25 °C Figure 6. Reference voltage vs. load current. Vref [V] 5.1 Vcc=15V Tj = 25°C 30 24 18 12 DC = 100% 1MHz 5.05 5 500K Hz 30 0K Hz 4.95 10 0KHz 6 0 8 10 12 14 16 Vcc [V] 18 20 22 4.9 0 5 10 Iref [mA] 15 20 25 Figure 7. Vref vs. junction temperature. Vref [V]) 5.1 Figure 8. Vref vs. junction temperature. Vref [V] 5.1 Vcc = 15V 5.05 Vcc = 15V Iref = 1mA 5.05 Iref= 20mA 5 5 4.95 4.95 4.9 -50 -25 0 25 50 Tj (°C) 75 100 125 150 4.9 -50 -25 0 25 50 Tj (°C) 75 100 125 150 5/22 L5993 Figure 9. Vref SVRR vs. switching frequency. SVRR (dB) Figure 10. Output saturation. Vsat = V 10 [V] 16 120 Vcc=15V Vp-p=1V Vcc = Vc = 15V 14 12 10 Tj = 25°C 80 40 8 6 1 10 100 1000 fsw (Hz) 10000 0 0 0.2 0.4 0.6 0.8 Isource [A] 1 1.2 Figure 11. Output saturation. V s at = V [V ] 10 2 .5 2 1 .5 1 0 .5 0 Figure 12. UVLO Saturation Ipin10 [mA] 50 V c c = Vc = 15 V Tj = 25 ° C 40 30 20 10 0 Vcc < Vccon beforeturn-on 0 0.2 0.4 0 .6 Is ink [A ] 0 .8 1 1 .2 0 200 400 600 800 Vpin10 [mV] 1,000 1,200 1,400 Figure 13. Timing resistor vs. switching frequency. fsw (KHz) 5000 Vcc = 15V, V15 =0V Figure 14. Switching frequency vs. temperature fsw (KHz) 320 2000 1000 500 Tj = 25° C Rt= 4.5Kohm, Ct = 1nF 310 100pF Vcc = 15V, V15=Vref 200 220pF 300 470pF 100 50 20 10 10 20 Rt (kohm) 30 40 5 .6nF 2.2nF 1 nF 290 280 -50 -25 0 25 50 Tj ( °C) 75 100 125 150 6/22 L5993 Figure 15. Switching frequency vs. temperature. fsw (KHz) 320 Rt= 4.5Kohm, Ct = 1nF Figure 16. Dead time vs Ct. Dead time [ns] 1,500 1,200 900 Rt =4.5Kohm V15 = 0V 310 Vcc = 15V, V15= 0 300 V15 = Vref 600 290 300 280 -50 -25 0 25 50 Tj ( °C) 75 100 125 150 2 4 6 8 Timing capacitor Ct [nF] 10 Figure 17. Maximum Duty Cycle vs Vpin3. DC Control Voltage Vpin3 [V] 3.5 Figure 18. Delay to output vs junction temperature. Delay to output (ns) 42 V15 = Vref V15 = 0V 40 38 3 2.5 36 2 Rt = 4.5Kohm, 34 32 30 PIN10 = OPEN 1V pulse on PIN13 1.5 1 0 10 20 30 Ct = 1nF 40 50 60 70 Duty Cycle [%] 80 90 100 28 -50 -25 0 25 50 Tj (°C) 75 100 125 150 Figure 19. E/A frequency response. G [dB] 150 120 Phase 140 100 100 80 50 60 0 40 20 0.01 0.1 1 10 100 f (KHz) 1000 10000 100000 7/22 L5993 CONSTANT POWER FUNCTION Pulse-by-pulse current limitation prevents peak primary current from exceeding a given level. This, in turn, limits the maximum power deliverable to the output or, in other words, the power capability of a converter. The capability, however, depends on switching frequency: for example, in a discontinuous current mode flyback they are just proportional. In SMPS’ of raster-scanned CRT displays the switching frequency is usually synchronized to the raster line scan signal of the display in order to increase noise immunity. More and more often, CRT displays are required to operate within a range of different video frequencies (e.g. from 31 kHz to 64 kHz), thus also the switching frequency of the SMPS will vary in that range. In case of some failure, the power throughput may be excessive without necessarily tripping the pulse-by-pulse current limitation circuit because of a high operating frequency. For the sake of safety, it would be then desirable to design the power stage of a converter (power MOSFET, transformer, catch diode) so as to be able to withstand the maximum power throughput under failure conditions. However, this is a considerable increase of size and cost. The ”Constant Power” function of the L5993 allows to overcome this problem. The device changes the threshold of its pulse-by-pulse current limitation circuit so as to maintain fairly constant the power capability of a flyback converter despite the changes of the switching frequency. This is accomplished by clamping the output of the error amplifier (VCOMP) to a value which decreases as the frequency of the signal fed into pin 1 (SYNC) builds up. The frequency-to-voltage conversion needed to achieve this functionality is performed by detecting the peak voltage of the (synchronized) oscillator with a peak-holding circuit. One external capacitor only is required. It is important to point out that shape, amplitude and duration of the synchronization pulses are of no concern with this technique. APPLICATION INFORMATION Detailed Pin Functions Description Pin 1. SYNC (In/Out Synchronization). This function allows the IC’s oscillator either to synchronize other controllers (master) or to be synchronized to an external frequency (slave). As a master, the pin delivers positive pulses during the falling edge of the oscillator (see pin 2). In slave operation the circuit is edge triggered. Refer to fig. 21 to see how it works. When several IC work in parallel no master-slave designation is needed because the fastest one becomes automatically the master. During the ramp-up of the oscillator the pin is pulled low by a 600µA internal sink current generator. During the falling edge, that is when the pulse is released, the 600µA pull-down is disconnected. The pin becomes a generator whose source capability is typically 7mA (with a voltage still higher than 3.5V). In fig. 20, some practical examples of synchronizing the L5993 are given. Pin 2. RCT (Oscillator). A resistor (RT) and a capacitor (CT), connected as shown in fig. 21 set the operating frequency fosc of the oscillator. CT is charged through RT until its voltage reaches 3V, then is quickly internally discharged. As the voltage has dropped to 1V it starts being charged again. The frequency can be established with the aid of fig. 13 diagrams or considering the approximate relationship: fosc ≅ 1 CT ⋅ (0.693 ⋅ RT + KT) (1) where KT is defined as:  90, V15 = VREF KT =  (2) 160 V15 = GND/OPEN and is linked to the duration of the falling edge of the sawtooth: Td ≅ 30 ⋅ 10-9 + KT ⋅ CT (3) Td is also the duration of the sync pulses delivRT Figure 20. Sinchronizing the L5993. SYNC 1 1 4 VREF RT SYNC VREF L4981A (MASTER) 16 17 RCT 18 SYNC 1 L5993 (SLAVE) 4 2 RCT VREF RT RCT 4 2 L5993 1 (MASTER) SYNC SYNC L4981A (SLAVE) 16 17 18 L5993 2 RCT L5993 2 CT ROSC COSC CT CT ROSC COSC (a) (b) D97IN766B (c) 8/22 L5993 Figure 21. Oscillator and synchronization internal schematic. SYNC VREF 4 1 R1 CLAMP RT RCT 2 D1 50Ω R3 R2 + 600µ A D R Q CLK CT D97IN500B ered at pin 1 and defines the upper extreme of the duty cycle range, Dx (see pin 15 for Dx definition and calculation). In case V15 is connecte d to VREF, however, the switching frequency of the system will be a half fosc . If the IC is to be synchronized to an external oscillator, RT and CT should be selected for a fosc lower than the master frequency in any condition (typically, 10-20% ), depending on the tolerance of RT and CT . Pin 3. DC (Duty Cycle Control). By biasing this pin with a voltage between 1 and 3 V it is possible to set the maximum duty cycle between 0 and the upper extreme Dx (see pin 15). If Dmax is the desired maximum duty cycle, the voltage V3 to be applied to pin 3 is: V3 = 5 - 2(2-Dmax) (4) Dmax is determined by internal comparison between V3 and the oscillator ramp (see fig. 22), thus in case the device is synchronized to an external frequency fext (and therefore the oscillator amplitude is reduced), (4) changes into: V3 = 5 − 4 ⋅ exp  − Figure 22. Duty cycle control. VREF R1 DC 4 3µA 3 23K RT R2 28K RCT 2 + - TO PWM LOGIC CT D97IN711A quired (i.e. DMAX = DX), the pin has to be left floating. An internal pull-up (see fig. 22) holds the voltage above 3V. Should the pin pick up noise (e.g. during ESD tests), it can be connected to VREF through a 4.7kΩ resistor. Pin 4. VREF (Reference Voltage). The device is provided with an accurate voltage reference (5V±1.5%) able to deliver some mA to an external circuit. A small film capacitor (0.1 µF typ.), connected between this pin and SGND, is recommended to ensure the stability of the generator and to prevent noise from affectingthe reference. Before device turn-on, this pin has a sink current capability of 0.5mA. 9/22   Dmax  (5) RT ⋅ CT ⋅ fext   A voltage below 1V will inhibit the driver output stage. This could be used for a not-latched device disable, for example in case of overvoltage protection (see application ideas). If no limitation on the maximum duty cycle is re- L5993 Pin 5. VFB (Error Amplifier Inverting Input). The feedback signal is applied to this pin and is compared to the E/A internal reference (2.5V). The E/A output generates the control voltage which fixes the duty cycle. The E/A features high gain-bandwidth product, which allows to broaden the bandwidth of the overall control loop, high slew-rate and current capability, which improves its large signal behavior. Usually the compensation network, which stabilizes the overall control loop, is connected between this pin and COMP (pin 6). Pin 6. COMP (Error Amplifier Output). Usually, this pin is used for frequency compensation and the relevant network is connected between this pin and VFB (pin 5). Compensation networks towards ground are not possible since the L5993 E/A is a voltage mode amplifier (low output impedance). See application ideas for some example of compensation techniques. Pin 7. SS (Soft-Start). At device start-up, a capacitor (Css) connected between this pin and SGND (pin 12) is charged by an internal current generator, ISSC, up to about 7V. During this ramp, the E/A output is clamped by the voltage across Css itself and allowed to rise linearly, starting from zero, up to the steady-state value imposed by the control loop. The maximum time interval during which the E/A is clamped, referred to as soft-start time, is approximately: Tss ≅ 3 ⋅ Rsense ⋅ IQpk ⋅ Css ISSC (6) Figure 23. Regulation characteristic and related quantities VOUT D.C.M. C.C.M. A IQpk 1-2 ·IQpk IQpk(max) B C TON D TON(min) D97IN495 ISHORT IOUT(max) IOUT where Rsense is the current sense resistor (see pin 13) and IQpk is the switch peak current (flowing through Rsense), which depends on the output Figure 24. Hiccup mode operation. IOUT load. Usually, CSS is selected for a TSS in the order of milliseconds. As mentioned before, the soft-start intervenes also in case of severe overload or short circuit on the output. Referring to fig. 23, pulse-by-pulse current limitation is somehow effective as long as the ON-time of the power switch can be reduced (from A to B). After the minimum ON-time is reached (from B onwards) the current is out of control. To prevent this risk, a comparator trips an overcurrent handling procedure, named ’hiccup’ mode operation, when a voltage above 1.2V (point C) is detected on current sense input (ISEN, pin 13). Basically, the IC is turned off and then soft-started as long as the fault condition is detected. As a result, the operating point is moved abruptly to D, creating a foldback effect. Fig. 24 illustrates the operation. The oscillation frequency appearing on the soft- SHORT ISEN FAULT SS 5V 0.5V Thic D98IN986 7V time 10/22 L5993 start capacitor in case of permanent fault, referred to as ’hiccup” period, is approximately given by: Thic ≅ 4.5 ⋅  Figure 25. Turn-on and turn-off speeds adjustment Rg’ 1 ISSC + 1 ⋅ Css (7) ISSD   V CC 8 13V DRIVE & CONTROL VC 9 Since the system tries restarting each hiccup cycle, there is not any latchoff risk. ”Hiccup” keeps the system in control in case of short circuits but does not eliminate power components overstress during pulse-by-pulse limitation (from A to C). Other external protection circuits are needed if a better control of overloads is required. Pin 8. VCC (Controller Supply). This pin supplies the signal part of the IC. The device is enabled as VCC voltage exceeds the start threshold and works as long as the voltage is above the UVLO threshold. Otherwise the device is shut down and the current consumption is extremely low ( 1 , 330 ⋅ ƒ mi n where ƒ min (Hz) is the minimum synchronizing frequency. When this function is not used, pin 16 has to be connecteddirectly to pin 4. Considering the ordinary design criteria for the transformer, the circuit usually works well without any adjustment. Anyway, the variations of the maximum power limit on varying the switching frequency and/or the mains voltage can be minimized by modifying one or more of the following parameters: - Primary inductance; - Transformer turns ratio; - Oscillator free-running frequency; - Sense resistor. A trial process is required, involving the parameters that are more practicable to modify. In fact, the optimum behavior is achieved for a specific combination of the above parameters and de13/22 L5993 pends both on the mains voltage range and the synchronization frequency range. An additional ”fine tuning” can be achieved by adding a small DC offset (in the ten mV) on the current sense pin (13, ISEN). For wide range mains applications it is anyway recommended to compensate the propagationdelay of the current sense path (PWM comparator + latch + driver) with the circuit shown in the ”Application Ideas” section, fig. 41. Layout hints Generally speaking a proper circuitboard layout is vital for correct operation but is not an easy task. Careful component placing, correct traces routing, appropriate traces widths and, in case of high voltages, compliance with isolation distances are the major issues. The L5993 eases this task by putting two pins at disposal for separate current returns of bias (SGND) and switch drive currents (PGND) The matter is complex and only few important points will be here reminded. 1) All current returns (signal ground, power ground, shielding, etc.) should be routed separately and should be connected only at a single ground point. 2) Noise coupling can be reduced by minimizing the area circumscribed by current loops. This applies particularly to loops where high pulsed currents flow. 3) For high current paths, the traces should be doubled on the other side of the PCB whenever possible: this will reduce both the resistance and the inductance of the wiring. 4) Magnetic field radiation (and stray inductance) can be reduced by keeping all traces carrying switched currents as short as possible. 5) In general, traces carrying signal currents should run far from traces carrying pulsed currents or with quickly swinging voltages. From this viewpoint, particular care should be taken of the high impedance points (current sense input, feedback input, ...). It could be a good idea to route signal traces on one PCB side and power traces on the other side. 6) Provide adequate filtering of some crucial points of the circuit, such as voltage references, IC’s supply pins, etc. 14/22 C11 4700pF 4KV C12 F01 AC 250V T3.15A BD01 R01 2.2 D52 R02 220K 17 D53 50V C62 100 µF 100V Q71 C71 R71 R72 Q72 HEATER CONTROL OFF NOR SUSPEND 14V UNSWITCHED Q73 C74 R73 +50V PC01 C08 470pF VR51 10K R55 18K C61 0.022µF R58 1.2K D97IN619A LF01 P1 AC IM C03 220µF 400V R18 22K 16 R51 C53 3 7 D54 15 14 C54 220µF 100V C52 10µF 100V C10 0.1 µF 200V R19 4.7M R20 4.7M 18 1 80V C01 0.1µF C02 0.1µF R03 10K D05 BYW13 -1000 D02 1N4148 D04 RGP100 R07 47 R12 33K R06 27 8 C04 470 µF 8 R08 22 10 R09 5.6K R11 1K 13 C05 470pF R10 0.22 R54 1K R53 4.7K C58 47µF 25V R52 47 10 D56 11 Q01 STP6 NA60FI C56 470µF 25V C57 470µF 25V D55 13 12 C55 470 µF 16V R04 470K Q01 KSP45 GND Q02 KTC1815Y ZD01 20V 6.3V R13 5.1K R05 10K APPLICATION IDEAS Here follows a series of ideas/suggestions aimed at C07 1 µF 14 9 4 15 R05 10K 2 C06 5600pF 5 L5993 12 11 R21 470 6 SYNC IN R17 1K 1 ZD02 5.6V R75 14V SWITCHED 7 16V ZD71 16V C59 0.01µF R56 100 Q74 Q75 -12V SWITCHED Figure 31. Typical application circuit for 15” Multisync monitor (70W) C09 0.01µF C11 1µF Q51 TL431 16 R74 H/V DEF. CONTROL SUSPEND OFF NOR either improving performance or solving common application problems of L5993 based supplies. L5993 15/22 L5993 Figure 32. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies VIN VC 9 ISOLATION BOUNDARY 10 OUT L5993 13 ISEN 12 PGND 11 SGND D97IN769 Figure 33. Low consumption start-up VIN 2.2MΩ 33KΩ STD1NB50-1 VCC 20V 47KΩ VREF 4 8 L5993 11 T SELF-SUPPLY WINDING 12 D97IN770B Figure 34. Bipolar Transistor Drive VIN VCC 8 VC 9 10 OUT ISEN 13 L5993 11 PGND D97IN771 16/22 L5993 Figure 35. Typical E/A compensation networks. + 1.3mA Ri VFB Rd Cf Rf COMP 6 5 + EA 2R From VO 2.5V R 12 SGND Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. + 1.3mA RP Ri CP Rd Cf VFB Rf COMP 6 5 + EA 2R From VO 2.5V R 12 SGND D97IN507 Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. Figure 36. Feedback with optocoupler VOUT 6 COMP L5993 5 VFB TL431 D97IN772 Figure 37. Slope compensation techniques VREF RT RCT RSLOPE CT ISEN RSENSE OPTIONAL VREF 4 RT 2 RCT CT 4 10 OUT R R 2 CSLOPE I L5993 13 12 SGND I RSLOPE L5993 ISEN 13 12 SGND OPTIONAL L5993 12 SGND OPTIONAL D97IN773A 13 ISEN RSLOPE RSENSE RSENSE 17/22 L5993 F igure 38. Protection against overvoltage/feedback disconnection (latched) RSTART RSTART VCC DIS 8 14 12 SGND VZ DIS 11 PGND D97IN774 VCC 8 14 12 SGND L5993 L5993 11 PGND D98IN906 2.2K Figure 39. Protection against overvoltage/feedback disconnection (not latched) RSTART Figure 40. Device shutdown on overcurrent 2.5 R SENSE I R2 R1 VREF 4 R1 VREF VCC 4 8 Ipk max ≅ • 1- Ipk 14 DIS R2 ISEN L5993 DC 3 12 L5993 11 11 12 SGND 13 RSENSE OPTIONAL PGND D97IN775A D97IN776A Figure 41. Constant power in pulse-by-pulse current limitation (flyback discontinuous) VIN 80 ÷ 400VDC RFF OUT 10 R FF = 6·106 R·Lp RSENSE Lp L5993 11 PGND SGND 12 13 ISEN R RSENSE D97IN777 Figure 42. Voltage mode operation. DC 10K COMP 6 SGND 3 L5993 12 13 ISEN D97IN778A 18/22 L5993 Figure 43. Device shutdown on mains undervoltage. VIN 80÷400VDC R1 4.7K VREF 4 L5993 3 5.1 R2 10KΩ SGND D97IN779A 12 PGND 11 Figure 44. Constant power ”Fine Tuning”. SGND 12 4 L5993 13 10 VREF RA ISEN R RSENSE OPTIONAL D97IN780A Figure 45. Synchronization to flyback pulses (for monitors). SYNC 1KΩ 5.1V 1 L5993 12 SGND D97IN781A Figure 46. Switching frequency halving on absence of sync. signal (for monitor). 1KΩ 5.1V VREF R1 1 (R1 //R2 )•C>> SYNC 4 1 fmin L5993 R2 DC-LIM 15 12 SGND f D97IN782A C 19/22 L5993 mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX. DIM. OUTLINE AND MECHANICAL DATA DIP16 20/22 L5993 mm MIN. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 9.8 5.8 1.27 8.89 4 5.3 1.27 0.62 8°(max.) 0.150 0.181 0.016 0.35 0.19 0.5 45° (typ.) 10 6.2 0.386 0.228 0.050 0.350 0.157 0.209 0.050 0.024 0.394 0.244 0.1 TYP. MAX. 1.75 0.25 1.6 0.46 0.25 0.014 0.007 0.020 0.004 MIN. inch TYP. MAX. 0.069 0.009 0.063 0.018 0.010 DIM. OUTLINE AND MECHANICAL DATA SO16 Narrow (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 21/22 L5993 I nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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