L5994_02

L5994 L5994A ADJUSTABLE TRIPLE OUTPUT POWER SUPPLY CONTROLLER FEATURE s DUAL PWM CONTROLLERS ADJUSTABLE 1.9V to 5.3V(Section1) 1.6V to 3.5V(Section2) s AUXILIARY DRIVER FOR LINEAR REGULATOR s CURRENT MODE CONTROL USING A LOW SENSE RESISTOR s DUAL SYNC RECTIFIERS DRIVERS s "ONE SHOT" FEATURE (L5994A only) s 96% EFFICIENCY ACHIEVABLE s 50µA@12V STAND BY CONSUMPTION s 4.75V TO 25V OPERATING SUPPLY VOLTAGE s EXCELLENT LOAD TRANSIENT RESPONSE s "PULSE SKIPPING" FUNCTION s OUTPUT UNDER VOLTAGE SHUTDOWN s ADAPTATIVE ANTI SHOOT-THROUGH CONTROL s OVER/UNDER VOLTAGE DETECTION s POWER GOOD SIGNALS s SEPARATED DISABLE s THERMAL SHUTDOWN Figure 1. System Block Diagram TQFP32 ORDERING NUMBERS: L5994 L5994A APPLICATIONS s NOTEBOOK AND SUB NOTEBOOK COMPUTERS s s s 1.8V AND 2.5V I/O SUPPLY WORDPAD INTERNET APPLIANCE DESCRIPTION The device provides a dual PWM controller and a linear driver controller that can support the complete power management in mobile equipment with high efficiency. 2.5V 5V to 25V L5994 POWER SECTION 1.8V SYNC 12V LDO 5.1V LDO POWER MANAGEMENT & SYSTEM SUPERVISOR 3.39V REF POWER GOOD µP MEMORY PERIPHERALS D98IN862 April 2002 1/26 L5994 - L5994A DESCRIPTION (continued) The device produces an adjustable regulated voltage in both sections and a linear regulated voltage with an external bipolar such as for PCMCIA applications. The auxiliary linear driver is able to source up to 1A for 12V bus and is also possible to use it for the regulation of 2.5V from 5V bus. Synchronous rectification and pulse skipping mode for the buck sections optimise the overall efficiency over a wide load current range. The two high performance PWM output sections are monitored for over voltage, under voltage and over current conditions. A POWER GOOD signal is provided for each section. On detection of a fault, the relevant POWER GOOD signal is generated and a specific shutdown procedure takes place to prevent physical damage and data corruption. A disable function allows to manage the output power sections separately, optimising the quiescent consumption of the IC in stand-by conditions. The internal architecture is a current mode that allows to have fast transient response without compromise the efficiency due to the ultra low sense resistor. Under voltage shutdown is forced in case of short circuit in one of the two sections. The drivers are provided of an adaptative anti cross conduction system for high output current application ABSOLUTE MAXIMUM RATINGS Symbol Vin Vi Power Supply Voltage Maximum pin voltage to pins 1,24,25,32 Parameters Value 0 to 27 -0.3 to (Vin + 0.3) Unit V V THERMAL DATA Symbol RTH j-amb Tj Parameters Thermal Resistance Junction to Ambient Operative Junction Temperature Range Value 60 -40 to 140 Unit °C/W °C PIN CONNECTIONS (Top views) H1GATE R1GATE R2GATE H2GATE 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 CRST PWROK1 RUN1 VREF SGND NOSKIP OSC RUN2 PREG5 H1SRC H2SRC PGND 32 31 30 29 28 27 26 25 H1STRAP VIN SREG5 V5SW V1SNS I1SNS COMP1 SOFT1 1 2 3 4 5 6 7 8 H2STRAP PWROK2 VFBLIN VDRLIN V2SNS I2SNS COMP2 SOFT2 D98IN863B 2/26 L5994 - L5994A BLOCK DIAGRAM SOFT1 8 SLOPE I1SNS V1SNS COMP1 6 5 7 + + + 1 VREF OVER CURRENT COMPARATOR + Hside LOGIC AND SHOOTTHROUGH CONTROL ZERO CROSSING COMPARATOR + PULSE SKIPPING COMPARATOR + PREG5 ERROR SUMMING SOFT SOFT2 17 SOFT ERROR SUMMING + SLOPE 19 20 18 I2SNS V2SNS COMP2 ∑ I1SNS V1SNS V2SNS I2SNS ∑ + + OVER CURRENT COMPARATOR + ZERO CROSSING COMPARATOR + PULSE SKIPPING COMPARATOR + - VREF 24 H1STRAP H2STRAP H1GATE 32 Hside LOGIC AND SHOOTTHROUGH CONTROL 25 H2GATE H1SRC 31 REG5 30 26 PREG5 27 28 H2SRC R1GATE Lside Lside R2GATE PGND 29 LINEAR REGULATOR + OVERVOLT COMPARATOR V5SW + SWITCH COMPARATOR VREF BUFFER + 13 VREF 16 RUN2 11 10 14 NOSKIP 9 23 D98IN864A W5SW VIN 4 2 21 UNDERVOLT COMPARATOR VREF POWER MANAGEMENT & SYSTEM SUPERVISOR VDRLIN - REG12 LDO 22 SREG5 3 4.7V VFBLIN VREF SGND 12 OSCILLATOR & SYNCHRONIZATION 15 OSC RUN1 PWROK1 CRST PWROK2 ELECTRICAL CHARACTERISTICS (Vin = 12V; Tj = 25°C; Vosc = GND; unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit DC CHARACTERISTIC Vin I2 Input supply voltage Operating quiescent current V1out,4V R1GATE= R2GATE = OPEN H1GATE = H2GATE = OPEN RUN1= RUN2 = SREG5 (DRIVERS OFF) RUNQ=RUN2=GND NOSKIP=GND Vin=12V Vin=20V 4.75 1.1 25 1.4 V mA I2 Stand by current 50 60 90 100 µA µA SECTION 1 PWM CONTROLLER V1out V1SNS feedback voltage V in = 5V to 20V NOSKIP = REG5 Vi1sns-Vv1sns = 0 to 40mA VSOFT1 = 3.1V Vin > 6.8V Vin < 5.8V 1.81 1.89 1.97 V V6-V5 V6-V5 Overcurrent Threshold current Pulse skipping mode threshold voltage 37 50 13 6.5 63 mV mV mV 3/26 L5994 - L5994A ELECTRICAL CHARACTERISTICS (continued) Symbol V5 Parameter Over voltage threshold ON V1SNS Under voltage threshold ON V1SNS SECTION 2 PWM CONTROLLER V2out V2SNS feedback voltage Vin = 5V to 20V NOSKIP = REG5 Vi2sns-Vv2sns = 0 to 40mA VSOFT2 = 3.1V Vin > 6.8V 1.843 1.451 1.566 1.64 1.714 V Test Condition Min. 2.09 1.66 Typ. 2.15 1.71 Max. 2.21 1.76 Unit V V V19-V20 V19-V20 V20 Overcurrent Threshold current Pulse skipping mode threshold voltage Over voltage threshold ON V2SNS Under voltage threshold ON V2SNS 37 50 13 1.9 1.496 63 mV mV 1.957 1.541 V V PWM CONTROLLERS CHARACTERISTICS fOSC V15 Td Tov Tuv V5,V20 I8,I17 V8,V17 Switching frequency accuracy Voltage range for 300KHz operation Dead time Over voltage propagation time Under voltage propagation time Output UVLO threshold latched Soft start current Soft start clamp voltage HS rise LS rise V1SNS to PWROK or V2SNS to PWROK V1SNS to PWROK or V2SNS to PWROK Respect output voltage 65 3.2 70 4 3.1 OSC = 2.5V OSC = GND OR 5V 255 170 2.4 50 30 1.25 1.5 75 4.8 300 200 345 230 2.6 KHz V ns µs µs % µA V HIGH AND LOW SIDE GATE DRIVER (BOTH SECTIONS) I25,I27 I32,I30 Source output peak current Sink output peak current RH RL VOH RdsON resistance RdsON resistance Output high voltage Cload = 3.3nF C load = 3.3nF Driver out high Driver out low HSTRAP = PREG5 Isource = 10mA; HSOURCE = GND 4.4 1 1 2.1 1.5 5.3 4 3 5.61 A A Ohm Ohm V 4/26 L5994 - L5994A ELECTRICAL CHARACTERISTICS (continued) Symbol VOL Parameter Output low voltage Test Condition HSTRAP = PREG5 Isource = 10mA; HSOURCE = GND Min. Typ. Max. 0.5 Unit V LINEAR REGULATOR DRIVER SECTION Imax Vref VDRLIN IFBLIN VCP Driver current VFBLIN threshold Input voltage range Bias Current Input voltage clamp “One Shot” activation threshold (L5994A only) “One Shot” Pulse (L5994A only) INTERNAL REGULATOR DRIVER SECTION V29 I29 V5SW V12 VREG5 output voltage Totale current capability V in = 7 to 25V VPREG5 = 5.3V Vin = 7V Vin > 7V, V5SW fall I load = 1mA Vin = 5 to 20V Iload = 1 to 5mA V12 = Vref-0.3V 5.0 25 70 4.2 2.45 2.425 4.53 2.5 2.5 4.8 2.55 2.575 5.3 5.5 V mA Iclamp = 100µA VDRLIN falling 16 12.88 13.7 14.52 1.5 VFBLIN < 2.5V VDRLIN = 15V 2.44 4.5 2.5 30 2.56 20 2 mA V V µA V V µs Swith-over threshold voltage Reference voltage V V I12 Source current at reference voltage 15 mA POWER GOOD AND ENABLE FUNCTION V16,V11 V16,V11 T10 T27,T30 RUN1, RUN2, enable voltage RUN1, RUN2, disable voltage Power good delay Shutdown delay time before LS activation (except for over voltage fault) CRST timing rate Power good high level Power good low level SYNCHRONIZATION V15 Synchronization pulse width Synchronization input voltage (falling edge) Fsw = 1MHz IPOWEROK = 320µA 400 5 ns V High level Low level CRST=100nF CRST=100nF 115 115 147 147 2.4 0.8 180 180 V V ms ms V12 = Vref-0.3V I POWEROK = 40µA I POWEROK = 320µA 4.1 1.47 ms/nF V 0.4 V 5/26 L5994 - L5994A PIN DESCRIPTION N° 1 2 3 4 Name H1STRAP Vin SREG5 V5SW Function Section 1 bootstrap capacitor connection. A bootstrap capacitor must be connected between this pin and pin H1SRC to supply the H1GATE driver. Device supply voltage. Internal logic supply. It must be connected to PREG5 pin through a R-C low-pass filter. Alternative supply voltage for the internal 5V regulator. If its voltage is greater than 4.5V, the internal regulator is supplied via this pin. If left floating, the regulator is supplied through the Vin pin. This pin connects the (-) input of section 1 current sense comparator. It must be connected downstream the external RSENSE resistor. This pin connects the (+) input of section 1 current sense comparator. It must be connected upstream the external RSENSE resistor. Feedback input for section 1. It must be connected directly or through a resistor divider to the output of the section 1. Soft start connection for section 1. The soft start time is programmed by an external capacitor connected between this pin and SGND. Approximatively 0.7ms/nF. Used for start-up and shut-down timing. A capacitor must be connected between this pin and SGND defining a time of 1.47ms/nF. Power Good open drain diagnostic signal. This output is in high inpedence when sect. 1 is enabled and running properly after a delay defined by the CRST capacitor. When not used may be left floating. Control input to enable / disable the section 1. A high logic level (>2.4V) enables this section, a low level (2.4V) disables pulse skipping at low load current, a low level (2.4V) enables this section, a low level (