L6206QTR

L6206Q DMOS dual full bridge driver Datasheet - production data  Undervoltage lockout  Integrated fast free wheeling diodes VFQFPN48 Application (7 x 7 mm)  Bipolar stepper motor  Dual or quad DC motor Features Description  Operating supply voltage from 8 to 52 V  5.6 A output peak current RDS(on) 0.3  typ. value at Tj = 25 °C  Operating frequency up to 100 kHz  Programmable high side overcurrent detection and protection  Diagnostic output  Paralleled operation  Cross conduction protection  Thermal shutdown The L6206Q device is a DMOS dual full bridge driver designed for motor control applications, developed using BCDmultipower technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. Available in a VFQFPN48 7 x 7 package, the L6206Q device features thermal shutdown and a non-dissipative overcurrent detection on the high side Power MOSFETs plus a diagnostic output that can be easily used to implement the overcurrent protection. Figure 1. Block diagram 9%227 9%227 9%227 9&3 96$ 9%227 &+$5*( 3803 352*&/$ 2&'$ 2&'$ 29(5 &855(17 '(7(&7,21 9 7+(50$/ 3527(&7,21 (1$ 287$ 287$ 9 *$7( /2*,& ,1$ 6(16($ ,1$ 92/7$*( 5(*8/$725 9 9 %5,'*($ 2&'% 2&'% 29(5 &855(17 '(7(&7,21 96% 352*&/% (1% 287% 287% *$7( /2*,& 6(16(% ,1% ,1% %5,'*(% ',1$ March 2017 This is information on a product in full production. DocID022028 Rev 4 1/27 www.st.com Contents L6206Q Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . .11 4.4 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Paralleled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Output current capability and IC power dissipation . . . . . . . . . . . . . . 21 8 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.1 VFQFPN48 (7 x 7 x 1.0 mm) package information . . . . . . . . . . . . . . . . . 24 11 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 DocID022028 Rev 4 L6206Q Electrical data 1 Electrical data 1.1 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol VS VOD VOCDA, VOCDB Parameter Value Unit Supply voltage VSA = VSB = VS 60 V Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS = 60 V; VSENSEA = VSENSEB = GND 60 V OCD pins voltage range - -0.3 to +10 V - -0.3 to +7 V VPROGCLA, PROGCL pins voltage range VPROGCLB VBOOT Bootstrap peak voltage VSA = VSB = VS VS + 10 V VIN,VEN Input and enable voltage range - -0.3 to +7 V VSENSEA, VSENSEB Voltage range at pins SENSEA and SENSEB - -1 to +4 V IS(peak) Pulsed supply current (for each VS pin), internally limited by the overcurrent protection VSA = VSB = VS; tPULSE < 1 ms 7.1 A RMS supply current (for each VS pin) VSA = VSB = VS 2.5 A Storage and operating temperature range - -40 to 150 °C IS Tstg, TOP 1.2 Test condition Recommended operating conditions Table 2. Recommended operating conditions Symbol VS VOD Parameter Test condition Supply voltage VSA = VSB = VS Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS; VSENSEA = VSENSEB VSENSEA, Voltage range at pins SENSEA and VSENSEB SENSEB 52 V 52 V -6 6 V DC -1 1 V 2.5 A +125 °C 100 kHz - Tj Operating junction temperature - fsw Switching frequency - DocID022028 Rev 4 8 Max. Unit Pulsed tW < trr RMS output current IOUT Min. -25 3/27 27 Pin connection 2 L6206Q Pin connection NC 1 OUT1A 2 VCP OUT2A OUT2A NC 44 ENA 45 IN1A 46 PROGCLA IN2A 47 SENSEA NC 48 SENSEA OCDA Figure 2. Pin connection (top view) 43 42 41 40 39 38 37 EPAD 36 NC 35 VSA 30 NC NC 8 29 NC NC 9 28 NC OUT1B 10 27 VSB OUT1B 11 26 VSB NC 12 25 NC 13 14 15 16 17 18 19 20 21 22 23 24 NC 7 OUT2B GND NC OUT2B 31 ENB 6 VBOOT NC GND IN2B 32 PROGCLB 5 IN1B NC NC SENSEB VSA 33 SENSEB 34 4 NC 3 NC OCDB OUT1A AM02556v1 1. The exposed PAD must be connected to GND pin. Table 3. Pin description Pin Name Type 43 IN1A Logic input Bridge A logic input 1. 44 IN2A Logic input Bridge A logic input 2. 45, 46 SENSEA Power supply 48 OCDA 2, 3 OUT1A Power output 6, 31 GND GND 10, 11 OUT1B Power output 13 OCDB 15, 16 SENSEB Power supply 17 IN1B Logic input 4/27 Function Bridge A source pin. This pin must be connected to power ground directly or through a sensing power resistor. Bridge A overcurrent detection and thermal protection pin. An internal Open-drain output open-drain transistor pulls to GND when overcurrent on bridge A is detected or in case of thermal protection. Bridge A output 1. Signal ground terminals. These pins are also used for heat dissipation toward the PCB. Bridge B output 1. Bridge B overcurrent detection and thermal protection pin. An internal Open-drain output open-drain transistor pulls to GND when overcurrent on bridge B is detected or in case of thermal protection. Bridge B source pin. This pin must be connected to power ground directly or through a sensing power resistor. Bridge B input 1 DocID022028 Rev 4 L6206Q Pin connection Table 3. Pin description (continued) Pin Name Type 18 IN2B Logic input Function Bridge B input 2 19 PROGCLB R pin Bridge B overcurrent level programming. A resistor connected between this pin and ground sets the programmable current limiting value for bridge B. By connecting this pin to ground the maximum current is set. This pin cannot be left unconnected. 20 ENB Logic input Bridge B enable. LOW logic level switches OFF all Power MOSFETs of bridge B. If not used, it must be connected to +5 V. 21 VBOOT Supply voltage Bootstrap voltage needed for driving the upper Power MOSFETs of both bridge A and bridge B. 22, 23 OUT2B Power output Bridge B output 2. 26, 27 VSB Power supply Bridge B power supply voltage. It must be connected to the supply voltage together with pin VSA. 34, 35 VSA Power supply Bridge A power supply voltage. It must be connected to the supply voltage together with pin VSB. 38, 39 OUT2A Power output Bridge A output 2. 40 VCP Output 41 ENA Logic input Bridge A enable. LOW logic level switches OFF all Power MOSFETs of bridge A. If not used, it must be connected to +5 V. R pin Bridge A overcurrent level programming. A resistor connected between this pin and ground sets the programmable current limiting value for bridge A. By connecting this pin to ground, the maximum current is set. This pin cannot be left unconnected. 42 PROGCLA Charge pump oscillator output. DocID022028 Rev 4 5/27 27 Electrical characteristics 3 L6206Q Electrical characteristics VS = 48 V, TA = 25 °C, unless otherwise specified. Table 4. Electrical characteristics Symbol VSth(ON) Parameter Test condition Min. Typ. Max. Unit Turn-on threshold - 6.6 7 7.4 V VSth(OFF) Turn-off threshold - 5.6 6 6.4 V IS Tj(OFF) Quiescent supply current All bridges OFF; Tj = -25 °C to 125 °C(1) - 5 10 mA Thermal shutdown temperature - - 165 - °C Tj = 25 °C - 0.34 0.4 Tj = 125 °C(1) - 0.53 0.59 Tj = 25 °C - 0.28 0.34 Tj = 125 °C(1) - 0.47 0.53 EN = low; OUT = VS - - 2 mA -0.15 - - mA Output DMOS transistors High-side switch ON resistance RDS(ON) Low-side switch ON resistance IDSS Leakage current EN = low; OUT = GND  Source drain diodes VSD Forward ON voltage ISD = 2.5 A, EN = LOW - 1.15 1.3 V trr Reverse recovery time If = 2.5 A - 300 - ns tfr Forward recovery time - - 200 - ns Logic input VIL Low level logic input voltage - -0.3 - 0.8 V VIH High level logic input voltage - 2 - 7 V IIL Low level logic input current GND logic input voltage -10 - - µA IIH High level logic input current 7 V logic input voltage - - 10 µA Vth(ON) Turn-on input threshold - - 1.8 2 V Vth(OFF) Turn-off input threshold - 0.8 1.3 - V Vth(HYS) Input threshold hysteresis - 0.25 0.5 - V 100 250 400 ns Switching characteristics tD(on)EN Enable pin to out, turn ON delay time(2) ILOAD = 2.5 A, resistive load tD(on)IN Input pin to out, turn ON delay time ILOAD = 2.5 A, resistive load (deadtime included) - 1.6 - µs Output rise time(2) ILOAD = 2.5 A, resistive load 40 - 250 ns Enable pin to out, turn OFF delay time(2) ILOAD = 2.5 A, resistive load 300 550 800 ns tRISE tD(off)EN 6/27 DocID022028 Rev 4 L6206Q Electrical characteristics Table 4. Electrical characteristics (continued) Symbol tD(off)IN Parameter Test condition Min. Typ. Max. Unit Input pin to out, turn OFF delay time ILOAD = 2.5 A, resistive load - 600 - ns Output fall time(2) ILOAD = 2.5 A, resistive load 40 - 250 ns tDT Deadtime protection - 0.5 1 - µs fCP Charge pump frequency -25 °C < Tj < 125 °C - 0.6 1 MHz tFALL Overcurrent detection Is over Input supply overcurrent detection threshold -25 °C < Tj < 125 °C; RCL = 39 k -25 °C < Tj < 125 °C; RCL = 5 k -25 °C < Tj < 125 °C; RCL = GND - 0.57 4.42 5.6 - A A A ROPDR Open-drain ON resistance I = 4 mA - 40 60  tOCD(ON) OCD turn-on delay time(3) I = 4 mA; CEN < 100 pF - 200 - ns time(3) I = 4 mA; CEN < 100 pF - 100 - ns tOCD(OFF) OCD turn-off delay 1. Tested at 25 °C in a restricted range and guaranteed by characterization. 2. See Figure 3. 3. See Figure 4. Figure 3. Switching characteristic definition EN Vth(ON) Vth(OFF) t IOUT 90% 10% t D01IN1316 tFALL tD(OFF)EN tRISE tD(ON)EN AM02557v1 DocID022028 Rev 4 7/27 27 Electrical characteristics L6206Q Figure 4. Overcurrent detection timing definition IOUT OCD Threshold t VOCD 90% 10% t tOCD(ON) tOCD(OFF) AM02558v1 8/27 DocID022028 Rev 4 L6206Q Circuit description 4 Circuit description 4.1 Power stages and charge pump The L6206Q device integrates two independent Power MOS full bridges. Each power MOS has an RDS(ON) = 0.3  (typical value at 25 °C) with intrinsic fast freewheeling diode. Cross conduction protection is implemented by using a deadtime (tDT = 1 µs typical value) set by an internal timing circuit between the turn-off and turn-on of two Power MOSFETs in one leg of a bridge. Pins VSA and VSB must be connected together to the supply voltage (VS). Using an N-channel Power MOSFET for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained through an internal oscillator and few external components to realize a charge pump circuit, as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz (typically) with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table 5. Table 5. Charge pump external component values Component Value CBOOT 220 nF CP 10 nF RP 100  D1 1N4148 D2 1N4148 Figure 5. Charge pump circuit VS D1 CBOOT D2 RP CP VCP VBOOT VSA VSB AM02559v1 4.2 Logic inputs Pins IN1A, IN2A, IN1B, IN2B, ENA, and ENB are TTL/CMOS and µC compatible logic inputs. The internal structure is shown in Figure 6. The typical values for turn-on and turn-off thresholds are respectively Vth(ON) = 1.8 V and Vth(OFF) = 1.3 V. Pins ENA and ENB are commonly used to implement overcurrent and thermal protection by connecting them respectively to the outputs OCDA and OCDB, which are open-drain outputs. If this type of connection is chosen, particular care needs to be taken in driving these pins. Two configurations are shown in Figure 7 and Figure 8. If driven by an opendrain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as DocID022028 Rev 4 9/27 27 Circuit description L6206Q shown in Figure 7. If the driver is a standard push-pull structure the resistor REN and the capacitor CEN are connected as shown in Figure 8. The resistor REN should be chosen in the range from 2.2 k to 180 k. Recommended values for REN and CEN are respectively 100 k and 5.6 nF. More information on selecting the values can be found in Section 4.3: Non-dissipative overcurrent detection and protection. Figure 6. Logic inputs internal structure 9 (6' 3527(&7,21 $0Y Figure 7. ENA and ENB pins open collector driving 9 9 5 (1 23(1 &2//(&7 25 287387 (1 $RU(1 % & (1 $0Y Figure 8. ENA and ENB pins push-pull driving 9 386+38// 287387 5(1 (1$RU(1% &(1 $0Y 10/27 DocID022028 Rev 4 L6206Q Circuit description Table 6. Truth table Inputs Outputs EN IN1 IN2 OUT1 OUT2 L X(1) X(1) High Z(2) High Z(2) H L L GND GND H H L VS GND H L H GND VS H H H VS VS 1. X = Do not care. 2. High Z = high impedance output. 4.3 Non-dissipative overcurrent detection and protection The L6206Q device integrates an overcurrent detection circuit (OCD). With this internal overcurrent detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 9 shows a simplified schematic of the overcurrent detection circuit for bridge A. Bridge B is provided with an analogous circuit. To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side Power MOSFET. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold Isover, the OCD comparator signals a fault condition. When a fault condition is detected, an internal open-drain MOSFET with a pulldown capability of 4 mA connected to the OCD pin is turned on. Figure 10 shows the OCD operation. This signal can be used to regulate the output current simply by connecting the OCD pin to the EN pin and adding an external R-C, as shown in Figure 9. The off-time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. IREF and, therefore, the output current detection threshold, are selectable by the RCL value, following Equation 1 and Equation 2: Equation 1 Isover = 5.6 A ± 30% at -25 °C < Tj < 125 °C if RCL = 0  (PROGCL connected to GND) Equation 2 Isover = 22100 ---------------- ± 10% at -25 °C < Tj < 125 °C if 5 k < RCL < 40 k R CL Figure 11 shows the output current protection threshold versus RCL value in the range 5 k to 40 k. DocID022028 Rev 4 11/27 27 Circuit description L6206Q The disable time (tDISABLE), before recovering normal operation, can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected either by CEN or REN values and its magnitude is reported in Figure 12. The delay time (tDELAY), before turning off the bridge when an overcurrent has been detected, depends only on the CEN value. Its magnitude is reported in Figure 13. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable delay time and the REN value should be chosen according to the desired disable time. The resistor REN should be chosen in the range from 2.2 k to 180 k. Recommended values for REN and CEN are respectively 100 k and 5.6 nF which allow a 200 µs disable time to be obtained. Figure 9. Overcurrent protection simplified schematic 287$ 96$ 287$ 32:(56(16( FHOO +,*+6,'('026V2) 7+(%5,'*($ ,$ 32:(5'026 QFHOOV 72*$7( /2*,& 9 5(1$ (1$ 32:(5'026 QFHOOV 32:(56(16( FHOO  2&' &203$5$725 ,$ Q ,$ Q ,$,$Q ,5() ,17(51$/ 23(1'5$,1 &(1$ ,$  2&'$ 9  29(5 7(03(5$785( ,5() 352*&/$ ',19 5&/$ 12/27 DocID022028 Rev 4 L6206Q Circuit description Figure 10. Overcurrent protection waveforms IOUT ISOVER VEN VDD Vth(ON) Vth(OFF) VEN(LOW) ON OCD OFF ON tDELAY BRIDGE tDISABLE OFF tOCD(ON) tEN(FALL) tOCD(OFF) tEN(RISE) tD(ON)EN tD(OFF)EN AM02564v1 Figure 11. Output current protection threshold versus RCL value 5 4.5 4 3.5 3 I SO VER [A] 2.5 2 1.5 1 0.5 0 5k 10k 15k 20k 25k R CL [ Ω ] 30k 35k 40k AM02565v1 DocID022028 Rev 4 13/27 27 Circuit description L6206Q Figure 12. tDISABLE versus CEN and REN (VDD = 5 V) 5 (1 W ',6$%/( >—V@     5 (1   5 (1   5 (1   5 (1         & (1 >Q )@ $0 Figure 13. tDELAY versus CEN (VDD = 5 V) W'(/$<  >       &(1 >Q)@   $0 4.4 Thermal protection In addition to overcurrent detection, the L6206Q device integrates a thermal protection for preventing device destruction in the case of junction overtemperature. It works by sensing the die temperature by means of a sensitive element integrated in the die. The device switches off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value). 14/27 DocID022028 Rev 4 L6206Q 5 Application information Application information A typical application using the L6206Q device is shown in Figure 14. Typical component values for the application are shown in Table 7. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6206Q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the ENA/OCDA and ENB/OCDB nodes to ground set the shutdown time for bridge A and bridge B respectively when an overcurrent is detected (see Section 4.3: Non-dissipative overcurrent detection and protection). The two current sources (SENSEA and SENSEB) should be connected to power ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) (see Table 3.). It is recommended to keep power ground and signal ground separated on the PCB. Table 7. Component values for typical application Component Value C1 100 F C2 100 nF CBOOT 220 nF CP 10 nF CENA 5.6 nF CENB 5.6 nF D1 1N4148 D2 1N4148 RCLA 5 k RCLB 5 k RENA 100 k RENB 100 k RP 100  DocID022028 Rev 4 15/27 27 Application information L6206Q Figure 14. Typical application 
 
       
 
 
   
  
  
  
  ".W Note: 16/27 To reduce the IC thermal resistance, and therefore improve the dissipation path, the NC pins can be connected to GND. DocID022028 Rev 4 L6206Q 6 Paralleled operation Paralleled operation The outputs of the L6206Q device can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges. When the two halves of one full bridge (for example OUT1A and OUT2A) are connected in parallel, the peak current rating is not increased as the total current must still flow through one bond wire on the power supply or sense pin. In addition, the overcurrent detection senses the sum of the current in the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the overcurrent detection threshold. For most applications the recommended configuration is half bridge 1 of bridge A paralleled with the half bridge 1 of bridge B, and the same for the half bridges 2, as shown in Figure 15. The current in the two devices connected in parallel share well as the RDS(ON) of the devices on the same die is well matched. When connected in this configuration the overcurrent detection circuit, which senses the current in each bridge (A and B), senses the current in the upper devices connected in parallel independently and the sense circuit with the lowest threshold trips first. With the enable pins connected in parallel, the first detection of an overcurrent in either upper DMOS device turns off both bridges. Assuming that the two DMOS devices share the current equally, the resulting overcurrent detection threshold is twice the minimum threshold set by the resistors RCLA or RCLB in Figure 15. It is recommended to use RCLA = RCLB. In this configuration the resulting bridge has the following characteristics.  Equivalent device: full bridge  RDS(ON) 0.15  typ. value at Tj = 25 °C  5 A max. RMS load current  11.2 A max. OCD threshold DocID022028 Rev 4 17/27 27 Paralleled operation L6206Q Figure 15. Parallel connection for higher current 96 $  96 9'& 96 % & & 32:(5 *5281'  ' & %22 7 6,*1$/ *5281' 53 ' 9&3      &3 9%22 7 6(16( $ 6(16( % 287 $ 287 $ /2$'  287 % 287 %  (1 % 2&' $ (1 $    5 (1 (1 & (1   ,1 $ ,1 ,1 $        *1' 2&' % ,1 % ,1 % ,1 352*&/ $ 5 &/$   352*&/ % 5 &/% $0Y To operate the device in parallel and maintain a lower overcurrent threshold, half bridge 1 and the half bridge 2 of bridge A can be connected in parallel and the same is done for bridge B, as shown in Figure 16. In this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device is reduced, but the peak current rating is not increased. When connected in this configuration the overcurrent detection circuit, senses the sum of the current in upper devices connected in parallel. With the enable pins connected in parallel, an overcurrent turns off both bridges. Since the circuit senses the total current in the upper devices, the overcurrent threshold is equal to the threshold set by the resistor RCLA or RCLB in Figure 16. RCLA sets the threshold when outputs OUT1A and OUT2A are high and resistor RCLB sets the threshold when outputs OUT1B and OUT2B are high. It is recommended to use RCLA = RCLB. In this configuration, the resulting bridge has the following characteristics. 18/27  Equivalent device: full bridge  RDS(ON) 0.15  typ. value at Tj = 25 °C  2.5 A max. RMS load current  5.6 A max. OCD threshold DocID022028 Rev 4 L6206Q Paralleled operation Figure 16. Parallel connection with lower overcurrent threshold 96$  96 9'& & 96% & 32:(5 *5281'      ' 53 9&3  &%227 6,*1$/ *5281' ' &3 9%227 6(16($ 6(16(% 287$ 287$ /2$' 287% 287%   (1$ 2&'% (1% 5(1 (1 &(1             *1' 2&'$ ,1$ ,1$ ,1$ ,1% ,1% ,1% 352*&/$ 5&/$   352*&/% 5&/% $0Y It is also possible to parallel the four half bridges to obtain a simple half bridge as shown in Figure 17. In this configuration the overcurrent threshold is equal to twice the minimum threshold set by the resistors RCLA or RCLB in Figure 17. It is recommended to use RCLA = RCLB. The resulting half bridge has the following characteristics.  Equivalent device: half bridge  RDS(ON) 0.075  typ. value at Tj = 25 °C  5 A max. RMS load current  11.2 A max. OCD threshold DocID022028 Rev 4 19/27 27 Paralleled operation L6206Q Figure 17. Paralleling the four half bridges 96 $  96 9'& & 96 % & 32:(5 *5281'  6,*1$/ *5281' ' & %227 53 ' 9&3    &3 9%227 6(16( $ 6(16( % 287 $ 287 $ /2$' 287 % 287 % *1'     2&' $ (1 $ 2&' % (1 % 5 (1 (1 & (1               ,1 $ ,1 $ ,1 ,1 % ,1 % 352*&/ $ 5 &/$ 352*&/ % 5 &/% $0Y 20/27 DocID022028 Rev 4 L6206Q Output current capability and IC power dissipation 7 Output current capability and IC power dissipation Figure 18 and Figure 19 show the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types:  One full bridge ON at a time (Figure 18) in which only one load at a time is energized.  Two full bridges ON at the same time (Figure 19) in which two loads at the same time are energized. For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large the onboard copper dissipating area must be in order to guarantee a safe operating junction temperature (125 °C maximum). Figure 18. IC power dissipation vs. output current with one full bridge on at a time 21()8//%5,'*(21 $7 $7,0( ,$   , 287 ,%  3'>:@ , 287  7HVWFRQGLWLRQV VXSSO\YROWDJH 9         1R3:0 I6: N+]VORZGHFD\  , 287>$@ $0Y Figure 19. IC power dissipation vs. output current with two full bridges ON at the same time 7:2)8//%5,'*(621 $7 7+(6$0(7,0(   ,$ , 287 ,%  , 287 3'>: @  7HVW FRQGLWLRQV VXSSO\YROWDJH 9          , 287 >$ @ 1R3:0 I 6: N+]VORZGHFD\ $0Y DocID022028 Rev 4 21/27 27 Thermal management 8 L6206Q Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it must be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Table 8. Thermal data Symbol RthJA Parameter Thermal resistance junction-ambient Package VFQFPN48 (1) Typ. Unit 17 °C/W 1. VFQFPN48 mounted on EVAL6208Q rev. 1.1 board (see EVAL6208Q databrief): four-layer FR4 PCB with a dissipating copper surface of about 45 cm2 on each layer and 25 via holes below the IC. 22/27 DocID022028 Rev 4 L6206Q Electrical characteristics curves 9 Electrical characteristics curves Figure 20. Typical quiescent current vs. supply voltage Figure 21. Typical high-side RDS(on) vs. supply voltage 5'621> @ ,T>P $@  IVZ N+]  7M ƒ&  7M ƒ&   7M ƒ&  7M ƒ&                9 6>9@            96>9@ $0Y Figure 22. Normalized typical quiescent current vs. switching frequency $0Y Figure 23. Normalized RDS(on) vs. junction temperature (typical value) ,T,TDWN+] 5 '6215' 621D W  ƒ&                               7M>ƒ&@ I6: >N+]@ $0Y $0Y Figure 24. Typical low-side RDS(on) vs. supply voltage Figure 25. Typical drain-source diode forward ON characteristic 5 '621> @ 6' >$@     7M ƒ& 7M ƒ&              96 >9@            96'>P9@ $0Y DocID022028 Rev 4 $0Y 23/27 27 Package information 10 L6206Q Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10.1 VFQFPN48 (7 x 7 x 1.0 mm) package information Figure 26. VFQFPN48 (7 x 7 x 1.0 mm) package outline 24/27 DocID022028 Rev 4 L6206Q Package information Table 9. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A 0.80 0.90 1.00 A1 - 0.02 0.05 A2 - 0.65 1.00 A3 - 0.25 - b 0.18 0.23 0.30 D 6.85 7.00 7.15 D2 4.95 5.10 5.25 E 6.85 7.00 7.15 E2 4.95 5.10 5.25 e 0.45 0.50 0.55 L 0.30 0.40 0.50 ddd - 0.08 - DocID022028 Rev 4 25/27 27 Order codes 11 L6206Q Order codes Table 10. Ordering information Order codes Package L6206Q VFQFPN48 7 x 7 x 1.0 mm L6206QTR 12 Packaging Tray Tape and reel Revision history Table 11. Document revision history Date Revision 15-Nov-2011 1 First release 10-Jun-2013 2 Unified package name to “VFQFPN48” in the whole document. Corrected headings in Table 1 and Table 2 (replaced “Parameter” by “Test condition”). Updated Table 4 (Added subscripts to “If” and “ROPDR”). Added titles to Equation 1 and Equation 2 and cross-references in Section 4.3: Non-dissipative overcurrent detection and protection. Corrected unit in Table 7 (row C1). Updated Figure 13 (added subscripts to “tDELAY” and “CEN”). Added Table 8: Thermal data in Section 8: Thermal management. Updated Section 10: Package information (modified titles, reversed order of Figure 26 and Table 9). Minor corrections throughout document. 01-Aug-2013 3 Updated Figure 1 on page 1. Corrected note 1. below Table 8 on page 22. 4 Updated Table 7 on page 15 (removed CREF row). Updated Figure 9 on page 12 and Figure 14 on page 16 (replaced by new figures). Minor modifications throughout document. 10-Mar-2017 26/27 Changes DocID022028 Rev 4 L6206Q IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID022028 Rev 4 27/27 27