L6207
DMOS dual full bridge driver with PWM current controller
Datasheet - production data
Thermal shutdown
Undervoltage lockout
Integrated fast freewheeling diodes
Applications
Bipolar stepper motor
Dual DC motor
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Description
The L6207 device is a DMOS dual full bridge
designed for motor control applications, realized
in BCD technology, which combines isolated
DMOS power transistors with CMOS and bipolar
circuits on the same chip. The device also
includes two independent constant off time PWM
current controllers that perform the chopping
regulation. Available in PowerSO36 and SO24
(20 + 2 + 2) packages, the L6207 device features
a non-dissipative overcurrent protection on the
high-side Power MOSFETs and thermal
shutdown.
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Features
Operating supply voltage from 8 to 52 V
5.6 A output peak current (2.8 A DC)
RDS(ON) 0.3 typ. value at Tj = 25 °C
Operating frequency up to 100 KHz
Non-dissipative overcurrent protection
Dual independent constant tOFF PWM current
controllers
Slow decay synchronous rectification
Cross conduction protection
October 2018
This is information on a product in full production.
DocID7513 Rev 3
1/32
www.st.com
Contents
L6207
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6
PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
9
7.1
Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1
Output current capability and IC power dissipation . . . . . . . . . . . . . . . . . 23
8.2
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1
PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2
SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2/32
DocID7513 Rev 3
L6207
1
Block diagram
Block diagram
Figure 1. Block diagram
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32
Maximum ratings
2
L6207
Maximum ratings
Table 1. Absolute maximum ratings
Symbol
VS
VOD
VBOOT
VIN, VEN
VREFA,
VREFB
Parameter
Test conditions
Value
Unit
VSA = VSB = VS
60
V
VSA = VSB = VS = 60 V;
VSENSEA = VSENSEB = GND
60
V
VSA = VSB = VS
VS + 10
V
Input and enable voltage range
-
-0.3 to +7
V
Voltage range at pins VREFA and VREFB
-
-0.3 to +7
V
-
-0.3 to +7
V
-
-1 to +4
V
Pulsed supply current (for each VS pin),
internally limited by the overcurrent
protection
VSA = VSB = VS;
tPULSE < 1 ms
7.1
A
RMS supply current (for each VS pin)
VSA = VSB = VS
2.8
A
-
-40 to 150
C
Supply voltage
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
Bootstrap peak voltage
VRCA, VRCB Voltage range at pins RCA and RCB
VSENSEA,
VSENSEB
IS(peak)
IS
Tstg, TOP
Voltage range at pins SENSEA and
SENSEB
Storage and operating temperature range
Table 2. Recommended operating conditions
Symbol
VS
VOD
VREFA,
VREFB
VSENSEA,
VSENSEB
Parameter
Supply voltage
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
Test conditions
Min.
Max.
Unit
VSA = VSB = VS
8
52
V
VSA = VSB = VS;
VSENSEA = VSENSEB
-
52
V
-
-0.1
5
V
(pulsed tW < trr)
(DC)
-6
-1
6
1
V
V
Voltage range at pins VREFA and VREFB
Voltage range at pins SENSEA and
SENSEB
IOUT
RMS output current
-
-
2.8
A
fsw
Switching frequency
-
-
100
KHz
4/32
DocID7513 Rev 3
L6207
Maximum ratings
Table 3. Thermal data
Symbol
Description
Rth-j-pins
Maximum thermal resistance junction pins
Rth-j-case
Maximum thermal resistance junction case
(1)
SO24
PowerSO36
Unit
14
-
C/W
-
1
C/W
51
-
C/W
Rth-j-amb1
Maximum thermal resistance junction ambient
Rth-j-amb1
Maximum thermal resistance junction ambient(2)
-
35
C/W
Rth-j-amb1
(3)
-
15
C/W
(4)
77
62
C/W
Rth-j-amb2
Maximum thermal resistance junction ambient
Maximum thermal resistance junction ambient
1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2
(with a thickness of 35 µm).
2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2
(with a thickness of 35 µm).
3. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2
(with a thickness of 35 µm), 16 via holes and a ground layer.
4. Mounted on a multilayer FR4 PCB without any heat sinking surface on the board.
DocID7513 Rev 3
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32
Pin connections
3
L6207
Pin connections
Figure 2. Pin connections (top view)
GND
1
36
GND
N.C.
2
35
N.C.
N.C.
3
34
N.C.
VSA
4
33
VSB
OUT2A
5
32
OUT2B
N.C.
6
31
N.C.
VCP
7
30
VBOOT
ENA
8
29
ENB
VREFA
9
28
VREFB
IN1A
10
27
IN2B
IN2A
11
26
IN1B
SENSEA
12
25
SENSEB
RCA
13
24
RCB
N.C.
14
23
N.C.
OUT1A
15
22
OUT1B
N.C.
16
21
N.C.
N.C.
17
20
N.C.
GND
18
19
GND
D02IN1347
PowerSO36(1)
1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).
Table 4. Pin description
Package
SO24
PowerSO36
Pin no.
Pin no.
1
6/32
Name
Type
Function
10
IN1A
Logic input
Bridge A logic input 1.
2
11
IN2A
Logic input
Bridge A logic input 2.
3
12
4
13
RCA
RC pin
RC network pin. A parallel RC network connected
between this pin and ground sets the current controller
OFF-time of the bridge A.
5
15
OUT1A
Power output
Bridge A output 1.
SENSEA Power supply
Bridge A source pin. This pin must be connected to
power ground through a sensing power resistor.
DocID7513 Rev 3
L6207
Pin connections
Table 4. Pin description (continued)
Package
SO24
PowerSO36
Name
Type
Function
Pin no.
Pin no.
6, 7, 18, 19
1, 18, 19, 36
GND
GND
Signal ground terminals. In SO package, these pins are
also used for heat dissipation toward the PCB.
8
22
OUT1B
Power output
Bridge B output 1.
9
24
RCB
RC pin
RC network pin. A parallel RC network connected
between this pin and ground sets the current controller
OFF-time of the bridge B.
10
25
11
26
IN1B
Logic input
Bridge B input 1
12
27
IN2B
Logic input
Bridge B input 2
13
28
VREFB
Analog input
Bridge B current controller reference voltage.
Do not leave this pin open or connect to GND.
SENSEB Power supply
Bridge B source pin. This pin must be connected to
power ground through a sensing power resistor.
Bridge B enable. LOW logic level switches OFF all
Power MOSFETs of bridge B. This pin is also connected
to the collector of the overcurrent and thermal protection
Logic input(1)
transistor to implement overcurrent protection.
If not used, it has to be connected to +5 V through
a resistor.
14
29
ENB
15
30
VBOOT
Supply
voltage
Bootstrap voltage needed for driving the upper Power
MOSFETs of both bridge A and bridge B.
16
32
OUT2B
Power output
Bridge B output 2.
17
33
VSB
Power supply
Bridge B power supply voltage. It must be connected to
the supply voltage together with pin VSA.
20
4
VSA
Power supply
Bridge A power supply voltage. It must be connected to
the supply voltage together with pin VSB.
21
5
OUT2A
Power output
Bridge A output 2.
22
7
VCP
Output
Charge pump oscillator output.
23
8
ENA
24
9
VREFA
Bridge A enable. LOW logic level switches OFF all
Power MOSFETs of bridge A. This pin is also connected
Logic input(1) to the collector of the overcurrent and thermal protection
transistor to implement overcurrent protection.
If not used, it has to be connected to +5 V through
a resistor.
Analog input
Bridge A current controller reference voltage.
Do not leave this pin open or connect to GND.
1. Also connected at the output drain of the overcurrent and thermal protection MOSFET. Therefore, it has to be driven putting
in series a resistor with a value in the range of 2.2 K - 180 K, recommended 100 K
DocID7513 Rev 3
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32
Electrical characteristics
4
L6207
Electrical characteristics
Table 5. Electrical characteristics
(Tamb = 25 °C, Vs = 48 V, unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VSth(ON)
Turn-on threshold
-
6.6
7
7.4
V
VSth(OFF)
Turn-off threshold
-
5.6
6
6.4
V
All bridges OFF;
Tj = -25 °C to 125 °C(1)
-
5
10
mA
-
-
165
-
C
-
0.34
0.4
W
-
0.53
0.59
W
Tj = 25 °C
-
0.28
0.34
W
Tj = 125 °C(1)
-
0.47
0.53
W
EN = low; OUT = VS
-
-
2
mA
EN = low; OUT = GND
-0.15
-
-
mA
ISD = 2.8 A, EN = LOW
-
1.15
1.3
V
IS
Tj(OFF)
Quiescent supply current
Thermal shutdown temperature
Output DMOS transistors
High-side switch ON resistance
RDS(ON)
Low-side switch ON resistance
IDSS
Leakage current
Tj = 25 °C
Tj = 125
°C(1)
Source drain diodes
VSD
Forward ON voltage
trr
Reverse recovery time
If = 2.8 A
-
300
-
ns
tfr
Forward recovery time
-
-
200
-
ns
VIL
Low level logic input voltage
-
-0.3
-
0.8
V
VIH
High level logic input voltage
-
2
-
7
V
IIL
Low level logic input current
GND logic input voltage
-10
-
-
µA
IIH
High level logic input current
7 V logic input voltage
-
-
10
µA
Logic input
Vth(ON)
Turn-on input threshold
-
-
1.8
2.0
V
Vth(OFF)
Turn-off input threshold
-
0.8
1.3
-
V
Vth(HYS)
Input threshold hysteresis
-
0.25
0.5
-
V
Switching characteristics
tD(on)EN
Enable to out turn ON delay time(2)
ILOAD = 2.8 A, resistive load
100
250
400
ns
tD(on)IN
Input to out turn ON delay time
ILOAD = 2.8 A, resistive load
(deadtime included)
-
1.6
-
µs
Output rise time(2)
ILOAD = 2.8 A, resistive load
40
-
250
ns
tD(off)EN
Enable to out turn OFF delay time(2)
ILOAD = 2.8 A, resistive load
300
550
800
ns
tD(off)IN
Input to out turn OFF delay time
ILOAD = 2.8 A, resistive load
-
600
-
ns
tRISE
8/32
DocID7513 Rev 3
L6207
Electrical characteristics
Table 5. Electrical characteristics
(Tamb = 25 °C, Vs = 48 V, unless otherwise specified) (continued)
Symbol
tFALL
Parameter
(2)
Output fall time
tdt
Deadtime protection
fCP
Charge pump frequency
Test conditions
Min.
Typ.
Max.
Unit
ILOAD = 2.8 A, resistive load
40
-
250
ns
-
0.5
1
-
µs
-25 °C t ON MIN = 1.5s (typ. value)
t ON > t RCRISE – t DT
tRCRISE = 600 · COFF
Figure 12 shows the lower limit for the on time tON for having a good PWM current
regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the
device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the
device continues to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and,
therefore, higher switching frequency), but the smaller is the value for COFF, the more
influential will be the noises on the circuit performance.
16/32
DocID7513 Rev 3
L6207
PWM current control
Figure 11. tOFF versus COFF and ROFF
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Slow decay mode
7
L6207
Slow decay mode
Figure 13 shows the operation of the bridge in the slow decay mode. At the start of the off
time, the lower power MOS is switched off and the current recirculates around the upper half
of the bridge. Since the voltage across the coil is low, the current decays slowly. After the
deadtime the upper power MOS is operated in the synchronous rectification mode. When
the monostable times out, the lower power MOS is turned on again after some delay set by
the deadtime to prevent cross conduction.
Figure 13. Slow decay mode output stage configurations
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DocID7513 Rev 3
L6207
Slow decay mode
Figure 17. tDELAY versus CEN (VDD = 5 V)
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7.2
Thermal protection
In addition to the overcurrent protection, the L6207 device integrates a thermal protection
for preventing the device destruction in case of junction overtemperature. It works sensing
the die temperature by means of a sensible element integrated in the die. The device
switches-off when the junction temperature reaches 165 °C (typ. value) with 15 °C
hysteresis (typ. value).
DocID7513 Rev 3
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32
Application information
8
L6207
Application information
A typical application using the L6207 device is shown in Figure 18. Typical component
values for the application are shown in Table 8. A high quality ceramic capacitor in the range
of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near
the L6207 device to improve the high frequency filtering on the power supply and reduce
high frequency transients generated by the switching. The capacitors connected from the
ENA and ENB inputs to ground set the shutdown time for the bridge A and bridge B
respectively when an overcurrent is detected (see Section 7.1: Non-dissipative overcurrent
protection on page 18). The two current sensing inputs (SENSEA and SENSEB) should be
connected to the sensing resistors with a trace length as short as possible in the layout. The
sense resistors should be non-inductive resistors to minimize the di/dt transients across the
resistor. To increase noise immunity, unused logic pins (except ENA and ENB) are best
connected to 5 V (high logic level) or GND (low logic level) (see Table 4: Pin description on
page 6). It is recommended to keep power ground and signal ground separated on the PCB.
Table 8. Component values for typical application
22/32
Component
Value
C1
100 F
C2
100 nF
CA
1 nF
CB
1 nF
CBOOT
220 nF
CP
10 nF
CENA
5.6 nF
CENB
5.6 nF
CREFA
68 nF
CREFB
68 nF
D1
1N4148
D2
1N4148
RA
39 K
RB
39 K
RENA
100 K
RENB
100 K
RP
100
RSENSEA
0.3
RSENSEB
0.3
DocID7513 Rev 3
L6207
Application information
Figure 18. Typical application
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Output current capability and IC power dissipation
In Figure 19 and Figure 20 are shown the approximate relation between the output current
and the IC power dissipation using PWM current control driving two loads, for two different
driving types:
One full bridge ON at a time (Figure 19) in which only one load at a time is energized.
Two full bridges ON at the same time (Figure 20) in which two loads at the same time
are energized.
For a given output current and driving type the power dissipated by the IC can be easily
evaluated, in order to establish which package should be used and how large must be the
on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
DocID7513 Rev 3
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32
Application information
L6207
Figure 19. IC Power dissipation versus output current with one full bridge ON
at a time
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Figure 20. IC Power dissipation versus output current with two full bridges ON
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L6207
8.2
Application information
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness. Figure 22, 23 and 23 show the
junction to ambient thermal resistance values for the PowerSO36 and SO24 packages.
For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper
thickness FR4 board with a 6 cm2 dissipating footprint (copper thickness of 35 µm), the
Rth j-amb is about 35 °C/W. Figure 21 shows mounting methods for this package. Using
a multilayer board with vias to a ground plane, thermal impedance can be reduced down to
15 °C/W.
Figure 21. Mounting the PowerSO package
Slug soldered
to PCB with
dissipating area
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
Figure 22. PowerSO36 junction ambient thermal resistance versus on-board copper
area
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Application information
L6207
Figure 23. SO24 junction ambient thermal resistance versus on-board copper area
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DocID7513 Rev 3
L6207
Application information
Figure 24. Typical quiescent current vs. supply Figure 25. Typical high-side RDS(ON) vs. supply
voltage
voltage
Iq [m A]
RDS(ON) []
5.6
0.380
fsw = 1 kHz
0.376
Tj = 25 °C
5.4
0.368
0.364
Tj = 125 °C
5.2
Tj = 25 °C
0.372
Tj = 85 °C
0.360
0.356
5.0
0.352
0.348
4.8
0.344
0.340
0.336
4.6
0
10
20
30
V S [V]
40
50
60
0
5
10
15
20
25
30
VS [V]
Figure 26. Normalized typical quiescent current
vs. switching frequency
Iq / (Iq @ 1 kHz)
Figure 27. Normalized RDS(ON) vs. junction
temperature (typical value)
R DS (ON) / (RDS(ON) @ 25 °C)
1.7
1.8
1.6
1.5
1.6
1.4
1.4
1.3
1.2
1.2
1.1
1.0
1.0
0.9
0.8
0
20
40
60
80
100
0
20
40
60
80
100
120
140
fSW [kHz]
Tj [°C]
Figure 28. Typical low-side RDS(ON) vs. supply
voltage
Figure 29. Typical drain-source diode forward
ON characteristic
R DS(ON) []
ISD [A]
0.300
3.0
0.296
2.5
Tj = 25 °C
Tj = 25 °C
0.292
2.0
0.288
1.5
0.284
1.0
0.280
0.5
0.276
0
5
10
15
V S [V]
20
25
30
0.0
700
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900
1000
1100
1200
1300
VSD [mV]
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Package information
9
L6207
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
9.1
PowerSO36 package information
Figure 30. PowerSO36 package outline
1
1
D
H
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$
F
D
'(7$,/ %
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'(7$,/ $
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6
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6($7,1*3/$1(
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&23/$1$5,7<
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Package information
Table 9. PowerSO36 package mechanical data
Dimensions
Symbol
mm
inch
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
3.60
-
-
0.141
a1
0.10
-
0.30
0.004
-
0.012
-
3.30
-
-
0.130
a2
a3
0
-
0.10
0
-
0.004
b
0.22
-
0.38
0.008
-
0.015
c
0.23
-
0.32
0.009
-
0.012
D(1)
15.80
-
16.00
0.622
-
0.630
D1
9.40
-
9.80
0.370
-
0.385
E
13.90
-
14.50
0.547
-
0.570
e
-
0.65
-
-
0.0256
-
11.05
-
-
0.435
-
10.90
-
11.10
0.429
-
0.437
E2
-
-
2.90
-
-
0.114
E3
5.80
-
6.20
0.228
-
0.244
E4
2.90
-
3.20
0.114
-
0.126
G
0
-
0.10
0
-
0.004
H
15.50
-
15.90
0.610
-
0.626
h
-
-
1.10
-
-
0.043
L
0.80
-
1.10
0.031
-
0.043
e3
(1)
E1
N
10° (max.)
S
8° (max.)
1. “D” and “E1” do not include mold flash or protrusions.
- Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch).
- Critical dimensions are “a3”, “E” and “G”.
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Package information
9.2
L6207
SO24 package information
Figure 31. SO24 package outline
&
Table 10. SO24 package mechanical data
Dimensions
Symbol
mm
inch
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.35
-
2.65
0.093
-
0.104
A1
0.10
-
0.30
0.004
-
0.012
B
0.33
-
0.51
0.013
-
0.020
C
0.23
-
0.32
0.009
-
0.013
15.20
-
15.60
0.598
-
0.614
E
7.40
-
7.60
0.291
-
0.299
e
-
1.27
-
-
0.050
-
H
10.0
-
10.65
0.394
-
0.419
h
0.25
-
0.75
0.010
-
0.030
L
0.40
-
1.27
0.016
-
0.050
-
0.004
D
(1)
k
ddd
0° (min.), 8° (max.)
-
-
0.10
-
1. “D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.
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Revision history
Revision history
Table 11. Document revision history
Date
Revision
Changes
03-Sep-2003
1
Initial release.
20-Feb-2014
2
Updated Section : Description on page 1 (removed “MultiPower-” from
“MultiPower-BCD technology”).
Added Revision history on page 31.
Updated Section 1: Block diagram (added section title, numbered and
moved Figure 1: Block diagram from page 1 to page 3).
Added title to Section 2: Maximum ratings on page 4, added numbers
and titles from Table 1: Absolute maximum ratings to Table 3: Thermal
data.
Added title to Section 3: Pin connections on page 6, added number and
title to Figure 2: Pin connections (top view), renumbered note 1 below
Figure 2, added title to Table 4: Pin description, renumbered note 1
below Table 4.
Added title to Section 4: Electrical characteristics on page 8, added title
and number to Table 5, renumbered notes 1 to 4 below Table 5.
Renumbered Figure 3 and Figure 4.
Added section numbers to Section 5: Circuit description on page 11,
Section 5.1 and Section 5.2. Removed “and uC” from first sentence in
Section 5.2. Renumbered Table 6, added header to Table 6.
Renumbered Figure 5 to Figure 8.
Added numbers to Section 6: PWM current control on page 14.
Renumbered Figure 9 to Figure 12. Added titles to Equation 1: on
page 16 till Equation 4: on page 16.
Added section numbers to Section 7: Slow decay mode on page 18,
Section 7.1 and Section 7.2). Renumbered Figure 13 to Figure 17.
Added section numbers to Section 8: Application information on
page 22, Section 8.1 and Section 8.2. Renumbered Table 8, added
header to Table 8. Renumbered Figure 18 to Figure 29.
Updated Section 9: Package information on page 28 (added main title
and ECOPACK text. Added titles from Table 9: PowerSO36 package
mechanical data to Table 10: SO24 package mechanical data and from
Figure 30: PowerSO36 package outline to Figure 31: SO24 package
outline, reversed order of named tables and figures. Removed 3D
figures of packages, replaced 0.200 by 0.020 inch of max. B value in
Table 10).
Added cross-references throughout document.
Added Section 10: Revision history and Table 11.
Minor modifications throughout document.
03-Oct-2018
3
Removed PowerDIP24 package from the whole document.
Removed “Tj“ from Table 2 on page 4.
Minor modifications throughout document.
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L6207
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
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