L6207Q
DMOS dual full bridge driver
Datasheet - production data
Description
The L6207Q device is a DMOS dual full bridge
driver designed for motor control applications,
realized in BCDmultipower technology, which
combines isolated DMOS power transistors with
CMOS and bipolar circuits on the same chip.
The device also includes two independent
constant OFF time PWM current controllers that
perform the chopping regulation. Available in
a VFQFPN48 7 x 7 package, the L6207Q device
features thermal shutdown and a non-dissipative
overcurrent detection on the high-side Power
MOSFETs.
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Features
Operating supply voltage from 8 to 52 V
5.6 A output peak current
RDS(on) 0.3 typ. value at Tj = 25 °C
Operating frequency up to 100 kHz
Non-dissipative overcurrent protection
Dual independent constant tOFF PWM current
controllers
Slow decay synchronous rectification
Cross conduction protection
Thermal shutdown
Undervoltage lockout
Integrated fast freewheeling diodes
Applications
Bipolar stepper motor
Dual or quad DC motor
June 2013
This is information on a product in full production.
DocID018993 Rev 3
1/27
www.st.com
Contents
L6207Q
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.3
PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4
Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5
Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 16
5.6
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Output current capability and IC power dissipation . . . . . . . . . . . . . . 21
8
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
11
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
DocID018993 Rev 3
L6207Q
1
Block diagram
Block diagram
Figure 1. Block diagram
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DocID018993 Rev 3
3/27
27
Electrical data
L6207Q
2
Electrical data
2.1
Absolute maximum ratings
Table 1. Absolute maximum ratings
Symbol
VS
Parameter
Test condition
Value
Unit
Supply voltage
VSA = VSB = VS
60
V
Differential voltage between VSA, OUT1A,
OUT2A, SENSEA and VSB, OUT1B, OUT2B,
SENSEB
VSA = VSB = VS = 60 V;
VSENSEA = VSENSEB = GND
60
V
VBOOT
Bootstrap peak voltage
VSA = VSB = VS
VS + 10
V
VIN,VEN
Input and enable voltage range
-0.3 to +7
V
VREFA,
VREFB
Voltage range at pins VREFA and VREFB
-0.3 to +7
V
Voltage range at pins RCA and RCB
-0.3 to +7
V
-1 to +4
V
VOD
VRCA,VRCB
VSENSEA,
VSENSEB
IS(peak)
IS
Tstg, TOP
2.2
Voltage range at pins SENSEA and SENSEB
Pulsed supply current (for each VS pin),
internally limited by the overcurrent
protection
VSA = VSB = VS;
tPULSE < 1 ms
7.1
A
RMS supply current (for each VS pin)
VSA = VSB = VS
2.5
A
-40 to 150
°C
Storage and operating temperature range
Recommended operating conditions
Table 2. Recommended operating conditions
Symbol
Parameter
Test condition
Supply voltage
VSA = VSB = VS
VOD
Differential voltage between VSA, OUT1A,
OUT2A, SENSEA and VSB, OUT1B, OUT2B,
SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and SENSEB
VS
IOUT
4/27
Min.
Max.
Unit
8
52
V
52
V
Pulsed tW < trr
-6
6
V
DC
-1
1
V
2.5
A
+125
°C
100
kHz
RMS output current
Tj
Operating junction temperature
fsw
Switching frequency
-25
DocID018993 Rev 3
L6207Q
3
Pin connection
Pin connection
NC
RCA
NC
SENSEA
SENSEA
IN2A
IN1A
VREFA
ENA
VCP
OUT2A
OUT2A
NC
Figure 2. Pin connection (top view)
48
47
46
45
44
43
42
41
40
39
38
37
1
OUT1A
EPAD
2
36
NC
35
VSA
GND
NC
7
30
NC
NC
8
29
NC
NC
9
28
NC
OUT1B
10
27
VSB
OUT1B
11
26
VSB
NC
12
25
NC
13
14
15
16
17
18
19
20
21
22
23
24
NC
31
OUT2B
6
OUT2B
GND
VBOOT
NC
ENB
32
VREFB
5
IN2B
NC
NC
IN1B
NC
SENSEB
VSA
33
NC
34
SENSEB
3
4
RCB
OUT1A
AM02556v1
Note:
The exposed PAD must be connected to GND pin.
Table 3. Pin description
Pin
Name
Type
Function
43
IN1A
Logic input
Bridge A logic input 1.
44
IN2A
Logic input
Bridge A logic input 2.
45, 46
SENSEA
Power supply
48
RCA
RC pin
2, 3
OUT1A
Power output
6, 31
GND
GND
10, 11
OUT1B
Power output
13
RCB
RC pin
Bridge A source pin. This pin must be connected to power ground
through a sensing power resistor.
RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF time of bridge A.
Bridge A output 1.
Signal ground terminals. These pins are also used for heat dissipation
toward the PCB.
Bridge B output 1.
RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF time of bridge B.
DocID018993 Rev 3
5/27
27
Pin connection
L6207Q
Table 3. Pin description (continued)
Pin
Name
Type
15, 16
SENSEB
Power supply
17
IN1B
Logic input
Bridge B input 1
18
IN2B
Logic input
Bridge B input 2
19
VREFB
Analog input
(1)
Bridge B source pin. This pin must be connected to power ground
through a sensing power resistor.
Bridge B current controller reference voltage. Do not leave this pin open
or connect to GND.
Bridge B enable. Low logic level switches off all power MOSFETs of
Bridge B. This pin is also connected to the collector of the overcurrent
and thermal protection transistor to implement overcurrent protection. If
not used, it must be connected to +5 V through a resistor.
20
ENB
21
VBOOT
Supply voltage
22, 23
OUT2B
Power output
Bridge B output 2.
26, 27
VSB
Power supply
Bridge B power supply voltage. It must be connected to the supply
voltage together with pin VSA.
34, 35
VSA
Power supply
Bridge A power supply voltage. It must be connected to the supply
voltage together with pin VSB.
38, 39
OUT2A
Power output
Bridge A output 2.
40
VCP
Output
41
ENA
42
VREFA
Logic input
Function
Bootstrap voltage needed for driving the upper power MOSFETs of both
Bridge A and bridge B.
Charge pump oscillator output.
(1)
Bridge A enable. Low logic level switches off all power MOSFETs of
bridge A. This pin is also connected to the collector of the overcurrent
and transistor to implement overcurrent protection. If not used, it must be
connected to +5 V through a resistor. Thermal protection
Analog input
Bridge A current controller reference voltage. Do not leave this pin open
or connect to GND.
Logic input
1. Also connected at the output drain of the overcurrent and thermal protection MOSFET. Therefore, it must be driven putting
in series a resistor with a value in the range of 2.2 k - 180 k, recommended 100 k.
6/27
DocID018993 Rev 3
L6207Q
4
Electrical characteristics
Electrical characteristics
VS = 48 V, TA = 25 °C, unless otherwise specified.
Table 4. Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VSth(ON)
Turn-on threshold
6.6
7
7.4
V
VSth(OFF)
Turn-off threshold
5.6
6
6.4
V
5
10
mA
IS
Tj(OFF)
All bridges OFF; Tj = -25 °C to
125 °C(1)
Quiescent supply current
Thermal shutdown temperature
165
°C
Output DMOS transistors
High-side switch ON resistance
RDS(ON)
Low-side switch ON resistance
IDSS
Tj = 25 °C
0.34
0.4
Tj = 125 °C(1)
0.53
0.59
Tj = 25 °C
0.28
0.34
Tj = 125 °C(1)
0.47
0.53
EN = low; OUT = VS
Leakage current
EN = low; OUT = GND
2
-0.15
mA
mA
Source drain diodes
VSD
Forward ON voltage
ISD = 2.5 A, EN = low
1.15
1.3
V
trr
Reverse recovery time
If = 2.5 A
300
ns
tfr
Forward recovery time
200
ns
Logic input
VIL
Low level logic input voltage
-0.3
0.8
V
VIH
High level logic input voltage
2
7
V
IIL
Low level logic input current
GND logic input voltage
IIH
High level logic input current
7 V logic input voltage
-10
µA
1.8
10
µA
2
V
Vth(ON)
Turn-on input threshold
Vth(OFF)
Turn-off input threshold
0.8
1.3
V
Vth(HYS)
Input threshold hysteresis
0.25
0.5
V
100
250
Switching characteristics
tD(on)EN
Enable to out turn ON delay time(2)
ILOAD = 2.5 A, resistive load
tD(on)IN
Input to out turn ON delay time
ILOAD = 2.5 A, resistive load
(deadtime included)
Output rise time(2)
ILOAD = 2.5 A, resistive load
40
tD(off)EN
Enable to out turn OFF delay time(2) ILOAD = 2.5 A, resistive load
300
tD(off)IN
Input to out turn OFF delay time
tRISE
ILOAD = 2.5 A, resistive load
DocID018993 Rev 3
400
1.6
550
600
ns
µs
250
ns
800
ns
ns
7/27
27
Electrical characteristics
L6207Q
Table 4. Electrical characteristics (continued)
Symbol
tFALL
Parameter
Output fall time
Test condition
(2)
tDT
Deadtime protection
fCP
Charge pump frequency
ILOAD = 2.5 A, resistive load
Min.
Typ.
40
0.5
-25 °C < Tj < 125 °C
Max.
Unit
250
ns
1
0.6
µs
1
MHz
PWM comparator and monostable
Source current at pins RCA and
RCB
VRCA = VRCB = 2.5 V
Voffset
Offset voltage on sense comparator
VREFA, VREFB = 0.5 V
tPROP
Turn OFF propagation delay(3)
tBLANK
Internal blanking time on SENSE
pins
tON(MIN)
Minimum ON time
IRCA, IRCB
3.5
5.5
mA
±5
mV
500
ns
1
µs
1.5
tOFF
PWM recirculation time
IBIAS
Input bias current at pins VREFA and
VREFB
2
µs
ROFF = 20 k; COFF = 1 nF
13
µs
ROFF = 100 k; COFF = 1 nF
61
µs
10
µA
5.6
7.1
A
60
Over current detection
Isover
ROPDR
tOCD(ON)
tOCD(OFF)
Input supply overcurrent detection
threshold
-25 °C < Tj < 125 °C
Open drain ON resistance
I = 4 mA
40
OCD turn-on delay time
(4)
I = 4 mA; CEN < 100 pF
200
ns
OCD turn-off delay time
(4)
I = 4 mA; CEN < 100 pF
100
ns
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See Figure 3.
3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
4. See Figure 4.
8/27
4
DocID018993 Rev 3
L6207Q
Electrical characteristics
Figure 3. Switching characteristic definition
EN
Vth(ON)
Vth(OFF)
t
IOUT
90%
10%
t
D01IN1316
tFALL
tD(OFF)EN
tRISE
tD(ON)EN
AM02557v1
Figure 4. Overcurrent detection timing definition
IOUT
ISOVER
ON
BRIDGE
OFF
VEN
90%
10%
tOCD(ON)
tOCD(OFF)
AM02558v1
DocID018993 Rev 3
9/27
27
Circuit description
L6207Q
5
Circuit description
5.1
Power stages and charge pump
The L6207Q device integrates two independent power MOSFET full bridges, each power
MOSFET has an RDS(ON) = 0.3 (typical value at 25 °C) with intrinsic fast freewheeling
diode. Cross conduction protection is implemented by using a deadtime (tDT = 1 µs typical
value) set by internal timing circuit between the turn-off and turn-on of two power MOSFETs
in one leg of a bridge.
Pins VSA and VSB must be connected together to the supply voltage (VS).
Using an N-channel power MOSFET for the upper transistors in the bridge requires a gate
drive voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained
through an internal oscillator and a few external components to realize a charge pump
circuit, as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz
(typically) with 10 V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Table 5.
Table 5. Charge pump external component values
Component
Value
CBOOT
220 nF
CP
10 nF
RP
100
D1
1N4148
D2
1N4148
Figure 5. Charge pump circuit
VS
D1
CBOOT
D2
RP
CP
VCP
VBOOT
VSA VSB
AM02559v1
10/27
DocID018993 Rev 3
L6207Q
5.2
Circuit description
Logic inputs
Pins IN1A, IN2A, IN1B and IN2B are TTL/CMOS and µC compatible logic inputs. The internal
structure is shown in Figure 6. Typical values for turn-on and turn-off thresholds are
respectively Vth(ON) = 1.8 V and Vth(OFF) = 1.3 V.
Pins ENA and ENB have identical input structures with the exception that the drains of the
overcurrent and thermal protection MOSFETs (one for bridge A and one for bridge B) are
also connected to these pins. Due to these connections, some care must be taken in driving
these pins. Two configurations are shown in Figure 7 and 8. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected, as shown in
Figure 7. If the driver is a standard push-pull structure, the resistor REN and the capacitor
CEN are connected, as shown in Figure 8. The resistor REN should be chosen in the range
from 2.2 k to 180 k. Recommended values for REN and CEN are respectively 100 k and
5.6 nF. More information on selecting the values is found in Section 5.5.
Figure 6. Logic inputs internal structure
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DocID018993 Rev 3
11/27
27
Circuit description
L6207Q
Table 6. Truth table
Inputs
Outputs
Description(1)
EN
IN1
IN2
OUT1
OUT2
L
X(2)
X
High Z(3)
High Z
Disable
H
L
L
GND
GND
Brake mode (lower path)
H
H
L
VS
GND (Vs)(4)
Forward
H
L
H
GND (Vs)
VS
Reverse
H
H
H
VS
VS
Brake mode (upper path)
1. Valid only in case of load connected between OUT1 and OUT2.
2. X = don’t care.
3. High Z = high impedance output.
4. GND (VS) = GND during tON, VS during tOFF.
5.3
PWM current control
The L6207Q device includes a constant OFF time PWM current controller for each of the
two bridges. The current control circuit senses the bridge current by sensing the voltage
drop across an external sense resistor connected between the source of the two lower
power MOSFET transistors and ground, as shown in Figure 9. As the current in the load
builds up, the voltage across the sense resistor increases proportionally. When the voltage
drop across the sense resistor becomes greater than the voltage at the reference input
(VREFA or VREFB), the sense comparator triggers the monostable switching the low-side
MOSFET off. The low-side MOSFET remains off for the time set by the monostable and the
motor current recirculates in the upper path. When the monostable times out, the bridge
again turns on. As the internal deadtime, used to prevent cross conduction in the bridge,
delays the turn-on of the power MOSFET, the effective OFF time is the sum of the
monostable time plus the deadtime.
Figure 9. PWM current controller simplified schematic
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DocID018993 Rev 3
L6207Q
Circuit description
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately
after the low-side Power MOSFET turns on, a high peak current flows through the sensing
resistor due to the reverse recovery of the freewheeling diodes. The L6207Q device
provides a 1 s blanking time tBLANK that inhibits the comparator output so that this current
spike cannot prematurely retrigger the monostable.
Figure 10. Output current regulation waveforms
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Thermal protection
In addition to the overcurrent detection, the L6207Q device integrates a thermal protection
to prevent device destruction in the case of junction overtemperature. It works sensing the
die temperature by means of a sensitive element integrated in the die. The device switches
off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ.
value).
18/27
DocID018993 Rev 3
L6207Q
6
Application information
Application information
A typical application using the L6207Q device is shown in Figure 18. Typical component
values for the application are shown in Table 7. A high quality ceramic capacitor in the range
of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near
the L6207Q to improve the high frequency filtering on the power supply and reduce high
frequency transients generated by the switching. The capacitors connected from the ENA
and ENB inputs to ground set the shutdown time for bridge A and bridge B, respectively,
when an overcurrent is detected (see Section 5.5). The two current sensing inputs
(SENSEA and SENSEB) should be connected to the sensing resistors with a trace length as
short as possible in the layout. The sense resistors should be non-inductive resistors to
minimize the di/dt transients across the resistor. To increase noise immunity, unused logic
pins (except ENA and ENB) are best connected to 5 V (high logic level) or GND (low logic
level) (see Section 3). It is recommended to keep power ground and signal ground
separated on the PCB.
Table 7. Component values for typical application
Component
Value
C1
100 F
C2
100 nF
CA
1 nF
CB
1 nF
CBOOT
220 nF
CP
10 nF
CENA
5.6 nF
CENB
5.6 nF
CREFA
68 nF
CREFB
68 nF
D1
1N4148
D2
1N4148
RA
39 k
RB
39 k
RENA
100 k
RENB
100 k
RP
100
RSENSEA
0.3
RSENSEB
0.3
DocID018993 Rev 3
19/27
27
Application information
L6207Q
Figure 18. Typical application
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20/27
To reduce the IC thermal resistance, therefore improving the dissipation path, the NC pins
can be connected to GND.
DocID018993 Rev 3
L6207Q
Output current capability and IC power dissipation
7
Output current capability and IC power dissipation
Figure 19 and 20 show the approximate relation between the output current and the IC
power dissipation using PWM current control driving two loads, for two different driving
types:
One full bridge ON at a time (Figure 19) in which only one load at a time is energized.
Two full bridges ON at the same time (Figure 20) in which two loads are energized at
the same time.
For a given output current and driving type the power dissipated by the IC can be easily
evaluated, in order to establish which package should be used and how large the onboard
copper dissipating area must be to guarantee a safe operating junction temperature (125 °C
maximum).
Figure 19. IC power dissipation vs. output current with one full bridge ON at a time
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Figure 20. IC power dissipation vs. output current with two full bridges ON at the same time
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Thermal management
8
L6207Q
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it must
be considered very carefully. Besides the available space on the PCB, the right package
should be chosen considering the power dissipation. Heatsinking can be achieved using
copper on the PCB with proper area and thickness.
Table 8. Thermal data
Symbol
RthJA
Parameter
Thermal resistance junction-ambient
Package
Typ.
Unit
VFQFPN48(1)
17
°C/W
1. VFQFPN48 mounted on EVAL6208Q rev 1 board (see EVAL6208Q databrief): four-layer FR4 PCB with
a dissipating copper surface of about 45 cm2 on each layer and 25 via holes below the IC.
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Electrical characteristics curves
9
Electrical characteristics curves
Figure 21. Typical quiescent current vs. supply
voltage
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Figure 22. Typical high-side RDS(on) vs. supply
voltage
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IVZ N+]
7M &
7M &
7M &
7M &
9 6>9@
Figure 23. Normalized typical quiescent current
vs. switching frequency
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Figure 24. Normalized RDS(on) vs. junction
temperature (typical value)
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Figure 25. Typical low-side RDS(on) vs. supply
voltage
Figure 26. Typical drain-source diode forward
ON characteristic
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Package information
10
L6207Q
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 27. VFQFPN48 (7 x 7 x 1.0 mm) package outline
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Package information
Table 9. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
Max.
0.80
0.90
1.00
A1
0.02
0.05
A2
0.65
1.00
A3
0.25
A
b
0.18
0.23
0.30
D
6.85
7.00
7.15
D2
4.95
5.10
5.25
E
6.85
7.00
7.15
E2
4.95
5.10
5.25
e
0.45
0.50
0.55
L
0.30
0.40
0.50
ddd
0.08
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Order codes
11
L6207Q
Order codes
Table 10. Ordering information
Order codes
Package
L6207Q
VFQFPN48 7x7x1.0 mm
L6207QTR
12
Packaging
Tray
Tape and reel
Revision history
Table 11. Document revision history
Date
Revision
29-Jul-2011
1
First release
28-Nov-2011
2
Document moved from preliminary to final datasheet.
3
Unified package name to “VFQFPN48” in the whole document.
Figure 1 moved to page 3, added Section 1: Block diagram.
Corrected headings in Table 1 and Table 2 (replaced “Parameter” by
“Test condition”).
Updated note 4. below Table 6 (replaced “tON” by “tOFF”).
Corrected unit in Table 7 (row C1).
Added titles to Equation 1 to Equation 5 in Section 5.3: PWM current
control.
Added Table 8: Thermal data in Section 8: Thermal management.
Updated Section 10: Package information (modified titles, reversed
order of Figure 27 and Table 9).
Unified “CEN”, “tDT”, “tON”, “tOFF”, “COFF”, “ROFF”, “Vth(ON)”,
“Vth(OFF)”(subscript, lower/upper case) in the whole document.
Minor corrections throughout document.
11-Jun-2013
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Changes
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