L6228Q
DMOS driver for bipolar stepper motor
Features
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
Operating supply voltage from 8 to 52 V 2.8 A output peak current (1.4 A RMS) RDS(on) 0.73 Ω typ. value @ TJ = 25 °C Operating frequency up to 100 kHz Non dissipative overcurrent protection Dual independent constant tOFF PWM current controllers Fast/slow decay mode selection Fast decay quasi-synchronous rectification Decoding logic for stepper motor full and half step drive Cross conduction protection Thermal shutdown Undervoltage lockout Integrated fast free wheeling diodes
VFQFPN32 5 mm x 5 mm
Description
The L6228Q is a DMOS fully integrated stepper motor driver with non-dissipative overcurrent protection, realized in BCDmultipower technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. The device includes all the circuitry needed to drive a two-phase bipolar stepper motor including: a dual DMOS full bridge, the constant off time PWM current controller that performs the chopping regulation and the phase sequence generator, that generates the stepping sequence. Available in VFQFPN32 5 mm x 5 mm package, the L6228Q features a non-dissipative overcurrent protection on the high side power MOSFETs and thermal shutdown.
Applications
■
Bipolar stepper motor Block diagram
VBOOT VBOOT
Figure 1.
VBOOT VCP CHARGE PUMP OCDA OCDB OVER CURRENT DETECTION 10V
VBOOT
VSA
OUT1A 10V OUT2A
THERMAL PROTECTION EN CONTROL GATE LOGIC
SENSEA
HALF/FULL CLOCK RESET CW/CCW STEPPING SEQUENCE GENERATION ONE SHOT MONOSTABLE
PWM MASKING TIME + SENSE COMPARATOR BRIDGE A OVER CURRENT DETECTION GATE LOGIC BRIDGE B
VSB
VREFA RCA
VOLTAGE REGULATOR
OUT1B OUT2B SENSEB VREFB RCB
10V
5V
D01IN1225
August 2010
Doc ID 14321 Rev 4
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Contents
L6228Q
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 1.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 3 4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Normal drive mode (full-step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 18 Wave drive mode (full-step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . 18 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 6 7 8 9 10
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output current capability and IC power dissipation . . . . . . . . . . . . . . 25 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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L6228Q
Electrical data
1
1.1
Table 1.
Symbol VS VOD VBOOT VIN,VEN
Electrical data
Absolute maximum ratings
Absolute maximum ratings
Parameter Supply voltage Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Bootstrap peak voltage Input and enable voltage range Voltage range at pins VREFA and VREFB Voltage range at pins RCA and RCB Voltage range at pins SENSEA and SENSEB Pulsed supply current (for each VS pin), internally limited by the overcurrent protection VSA = VSB = VS; tPULSE < 1 ms Parameter VSA = VSB = VS VSA = VSB = VS = 60 V; VSENSEA = VSENSEB = GND VSA = VSB = VS Value 60 60 VS + 10 -0.3 to +7 -0.3 to +7 -0.3 to +7 -1 to +4 Unit V V V V V V V
VREFA, VREFB VRCA, VRCB VSENSEA, VSENSEB IS(peak) IS Tstg, TOP
3.55 1.4 -40 to 150
A A °C
RMS supply current (for each VS pin) VSA = VSB = VS Storage and operating temperature range
1.2
Table 2.
Symbol VS VOD
Recommended operating conditions
Recommended operating conditions
Parameter Supply voltage Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Voltage range at pins VREFA and VREFB Voltage range at pins SENSEA and SENSEB RMS output current Operating junction temperature Switching frequency -25 (pulsed tW < trr) (DC) Parameter VSA = VSB = VS VSA = VSB = VS; VSENSEA = VSENSEB -0.1 -6 -1 Min 8 Max 52 52 Unit V V
VREFA, VREFB VSENSEA, VSENSEB IOUT Tj fsw
5 6 1 1.4 +125 100
V V V A °C kHz
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Electrical data
L6228Q
1.3
Thermal data
Table 3.
Symbol Rth(JA)
Thermal data
Parameter Thermal resistance junction-ambient max (1).
2
Value 42
Unit °C/W
1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm on the top side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC).
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L6228Q
Pin connection
2
Pin connection
Figure 2. Pin connection (top view)
Note:
1 2
The pins 2 to 8 are connected to die PAD. The die PAD must be connected to GND pin.
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Pin connection Table 4.
N° 1, 21 9 11 12 13
L6228Q
Pin description
Pin GND OUT1B RCB SENSEB VREFB Type GND Ground terminals. Function
Power output Bridge B output 1. RC pin Power supply Analog input RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF-time of the bridge B. Bridge B source pin. This pin must be connected to power ground through a sensing power resistor. Bridge B current controller reference voltage. Do not leave this pin open or connected to GND. Step mode selector. HIGH logic level sets HALF STEP mode, LOW logic level sets FULL STEP mode. If not used, it has to be connected to GND or +5 V. Decay mode selector. HIGH logic level sets SLOW DECAY mode. LOW logic level sets FAST DECAY mode. If not used, it has to be connected to GND or +5 V. Chip enable. LOW logic level switches OFF all power MOSFETs of both bridge A and bridge B. This pin is also connected to the collector of the overcurrent and thermal protection to implement over current protection. If not used, it has to be connected to +5 V through a resistor. Bootstrap voltage needed for driving the upper power MOSFETs of both bridge A and bridge B.
14
HALF/FULL
Logic input
15
CONTROL
Logic input
16
EN
Logic input
(1)
17 19 20 22 23 24 25
VBOOT OUT2B VSB VSA OUT2A VCP RESET
Supply voltage
Power output Bridge B output 2. Power supply Power supply Bridge B power supply voltage. It must be connected to the supply voltage together with pin VSA Bridge A power supply voltage. It must be connected to the supply voltage together with pin VSB Charge pump oscillator output. Reset pin. LOW logic level restores the home state (state 1) on the phase sequence generator state machine. If not used, it has to be connected to +5 V. Bridge A current controller reference voltage. Do not leave this pin open or connected to GND. Step clock input. The state machine makes one step on each rising edge. Selects the direction of the rotation. HIGH logic level sets clockwise direction, whereas LOW logic level sets counterclockwise direction. If not used, it has to be connected to GND or +5 V. Bridge A source pin. This pin must be connected to power ground through a sensing power resistor. RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF-time of the bridge A.
Power output Bridge A output 2. Output Logic input
26 27 28
VREFA CLOCK CW/CCW
Analog Input Logic input Logic input
29 30 31
SENSEA RCA OUT1A
Power supply RC pin
Power output Bridge A output 1.
1. Also connected at the output drain of the over current and thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ
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L6228Q
Electrical characteristics
3
Table 5.
Symbol VSth(ON) VSth(OFF) IS Tj(OFF)
Electrical characteristics
Electrical characteristics (TA = 25 °C, Vs = 48 V, unless otherwise specified)
Parameter Turn-on threshold Turn-off threshold Quiescent supply current Thermal shutdown temperature All bridges OFF; TJ = -25 °C to 125 °C(1) Test condition Min 5.8 5 Typ 6.3 5.5 5 165 Max 6.8 6 10 Unit V V mA °C
Output DMOS transistors
RDS(on)
IDSS
High-side + low-side switch ON resistance Leakage current
TJ = 25 °C TJ =125 °C
(1)
1.47 2.35
1.69 2.70 2
Ω Ω mA mA
EN = Low; OUT = VS EN = Low; OUT = GND -0.3
Source drain diodes VSD trr tfr Forward ON voltage Reverse recovery time Forward recovery time ISD = 1.4 A, EN = LOW If = 1.4 A 1.15 300 200 1.3 V ns ns
Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW) VIL VIH IIL IIH Vth(ON) Vth(OFF) Vth(HYS) Low level logic input voltage High level logic input voltage Low level logic input current High level logic input current Turn-on input threshold Turn-off input threshold Input threshold hysteresis 0.8 0.25 GND logic input voltage 7 V logic input voltage 1.8 1.3 0.5 -0.3 2 -10 10 2.0 0.8 7 V V µA µA V V V
Switching characteristics tD(ON)EN tD(OFF)EN tRISE tFALL tDCLK tCLK(min)L tCLK(min)H Enable to output turn-on delay time (2) Enable to output turn-off delay time (2) Output rise time
(2)
500 500 ILOAD =1.4 A, resistive load 40 40
650 800
800 1000 250 250
ns ns ns ns µs
Output fall time (2) Clock to output delay time Minimum clock time Minimum clock
(4) (3)
2 1 1
µs µs
time (4)
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Electrical characteristics Table 5.
Symbol fCLK tS(MIN) tH(MIN) tR(MIN) tRCLK(MIN) tDT fCP
L6228Q
Electrical characteristics (continued) (TA = 25 °C, Vs = 48 V, unless otherwise specified)
Parameter Clock frequency Minimum set-up time(5) Minimum hold time
(5) (5) (5)
Test condition
Min
Typ
Max 100 1 1 1 1
Unit kHz µs µs µs µs µs
Minimum reset time
Minimum reset to clock delay time Dead time protection Charge pump frequency
0.5 TJ = -25 °C to 125 °C
(1)
1 0.6 1
MHz
PWM comparator and monostable IRCA, IRCB Voffset tPROP tBLANK tON(MIN) tOFF IBIAS Source current at pins RCA and RCB Offset voltage on sense comparator Turn OFF propagation delay
(6)
VRCA = VRCB = 2.5 V VREFA, VREFB = 0.5 V
3.5
5.5 ±5 500 1 2.5 3
mA mV ns µs µs µs µs 10 µA
Internal blanking time on SENSE pins Minimum on time PWM recirculation time Input bias current at pins VREFA and VREFB ROFF = 20 kΩ; COFF = 1 nF ROFF = 100 kΩ; COFF = 1 nF
13 61
Over current protection ISOVER ROPDR tOCD(ON) tOCD(OFF) Input supply overcurrent protection threshold Open drain ON resistance OCD turn-on delay time (7) OCD turn-off delay time
(7)
Tj = -25 °C to 125 °C (1) I = 4 mA I = 4 mA; CEN < 100 pF I = 4 mA; CEN < 100 pF
2.8 40 200 100 60
A W ns ns
1. Tested at 25 °C in a restricted range and guaranteed by characterization 2. See Figure 3. 3. See Figure 4. 4. See Figure 5. 5. See Figure 6. 6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF. 7. See Figure 7.
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L6228Q Figure 3. Switching characteristic definition
EN
Electrical characteristics
Vth(ON) Vth(OFF) t IOUT 90%
10%
D01IN1316
t tFALL tD(OFF)EN tD(ON)EN tRISE
Figure 4.
Clock to output delay time
CLOCK
Vth(ON)
t IOUT
D01IN1317
t tDCLK
Figure 5.
Minimum timing definition; clock input
CLOCK Vth(ON) tCLK(MIN)L
Vth(OFF)
Vth(OFF) tCLK(MIN)H
D01IN1318
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Electrical characteristics Figure 6. Minimum timing definition; logic inputs
CLOCK Vth(ON)
L6228Q
LOGIC INPUTS
tS(MIN) RESET Vth(OFF) Vth(ON)
tH(MIN)
tR(MIN)
tRCLK(MIN)
D01IN1319
Figure 7.
Overcurrent detection timing definition
IOUT ISOVER
ON BRIDGE OFF VEN 90%
10% tOCD(ON) tOCD(OFF)
D02IN1399
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Circuit description
4
4.1
Circuit description
Power stages and charge pump
The L6228Q integrates two independent power MOS full bridges. Each power MOS has an RDS(on) = 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM Current Controller and the Phase Sequence Generator (see below). Cross conduction protection is achieved using a dead time (tDT = 1 μs typical value) between the switch off and switch on of two power MOSFETs in one leg of a bridge. Pins VSA and VSB must be connected together to the supply voltage VS. The device operates with a supply voltage in the range from 8 V to 52 V. It has to be noticed that the RDS(on) increases of some percents when the supply voltage is in the range from 8 V to 12 V. Using N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply voltage VBOOT is obtained through an internal Oscillator and few external components to realize a charge pump circuit as shown in Figure 8. The oscillator output (VCP) is a square wave at 600 kHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table 6. Table 6. Charge pump external components values
Component CBOOT CP D1 D2 Value 220 nF 10 nF 1N4148 1N4148
Figure 8.
Charge pump circuit
VS D1 D2 CBOO T
CP
VCP
VBOO T
VS A
VS B
D01IN1328
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Circuit description
L6228Q
4.2
Logic inputs
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and microcontroller compatible logic inputs. The internal structure is shown in Figure 9. Typical value for turn-on and turn-off thresholds are respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V. Pin EN (Enable) has identical input structure with the exception that the drain of the Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving this pin. The EN input may be driven in one of two configurations as shown in Figure 10 or Figure 11. If driven by an open drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Figure 10. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Figure 11. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and 5.6nF. More information on selecting the values is found in the overcurrent protection section. Figure 9. Logic inputs internal structure
5V
ESD PROTECTION
D01IN1329
Figure 10. EN pin open collector driving
5V REN OPEN COLLECTOR OUTPUT EN CEN ESD PROTECTION
D01IN1330
5V
Figure 11. EN pin push-pull driving
5V REN
PUSH-PULL OUTPUT
EN CEN ESD PROTECTION
D01IN1331
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L6228Q
Circuit description
4.3
PWM current control
The L6228Q includes a constant off time PWM current controller for each of the two bridges. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 12. As the current in the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the monostable and the motor current recirculates as defined by the selected decay mode, described in the next section. When the monostable times out the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time. Figure 12. PWM current controller simplified schematic
VSA (or B) TO GATE LOGIC BLANKING TIME MONOSTABLE 1μs FROM THE LOW-SIDE GATE DRIVERS 2H MONOSTABLE SET 1H 2 PHASE STEPPER MOTOR
5mA
Q (0) (1)
S R
BLANKER
IOUT OUT2A(or B) DRIVERS + DEAD TIME DRIVERS + DEAD TIME OUT1A(or B)
5V 2.5V +
SENSE COMPARATOR + COMPARATOR OUTPUT RCA(or B) COFF ROFF -
2L
1L
VREFA(or B) RSENSE
SENSEA(or B)
D01IN1332
Figure 13 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. More details regarding the Synchronous Rectification and the output stage configuration are included in the next section. Immediately after the power MOS turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The L6228Q provides a 1 μs blanking time tBLANK that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable.
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Circuit description Figure 13. Output current regulation waveforms
IOUT VREF RSENSE tOFF 1μs tBLANK tON tOFF 1μs tBLANK
L6228Q
VSENSE VREF 0
Slow Decay
c Fast De ay
Slow Decay
c Fast De ay
VRC 5V 2.5V
tRCRISE
tRCRISE
tRCFALL 1μs tDT ON
SYNCHRONOUS OR QUASI SYNCHRONOUS RECTIFICATION
D01IN1334
tRCFALL 1μs tDT
OFF
B
C
D
A
B
C
D
Figure 14 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately calculated from the equations: tRCFALL = 0.6 · ROFF · COFF tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with: 20 kΩ ≤ ROFF ≤ 100 kΩ 0.47 nF ≤ COFF ≤ 100 nF tDT = 1 µs (typical value) Therefore: tOFF(MIN) = 6.6 µs tOFF(MAX) = 6 ms These values allow a sufficient range of tOFF to implement the drive circuit for most motors. The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the pin RCOFF. The Rise Time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON can not be smaller than the minimum on time tON(MIN).
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Circuit description
⎧ t ON > t ON ( MIN ) = 2.5 μ s ⎫ ⎨ ⎬ ⎩ t ON > t RCRISE – t DT ⎭
(typ. value)
tRCRISE = 600 · COFF Figure 15 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant. So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit performance. Figure 14. tOFF versus COFF and ROFF
1 .10
4
R off = 100kΩ 1 .10
3
R off = 47kΩ R off = 20kΩ
toff [μs]
100
10
1
0.1
1 Coff [nF]
10
100
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Circuit description Figure 15. Area where tON can vary maintaining the PWM regulation
100
L6228Q
ton(min) [us]
10
2.5μs (typ. value)
1 0.1
1 Coff [nF]
10
100
4.4
Decay modes
The CONTROL input is used to select the behavior of the bridge during the off time. When the CONTROL pin is low, the fast decay mode is selected and both transistors in the bridge are switched off during the off time. When the CONTROL pin is high, the slow decay mode is selected and only the low side transistor of the bridge is switched off during the off time. Figure 16 shows the operation of the bridge in the fast decay mode. At the start of the off time, both of the power MOS are switched off and the current recirculates through the two opposite free wheeling diodes. The current decays with a high dI/dt since the voltage across the coil is essentially the power supply voltage. After the dead time, the lower power MOS in parallel with the conducting diode is turned on in synchronous rectification mode. In applications where the motor current is low it is possible that the current can decay completely to zero during the off time. At this point if both of the power MOS were operating in the synchronous rectification mode it would then be possible for the current to build in the opposite direction. To prevent this only the lower power MOS is operated in synchronous rectification mode. This operation is called quasi-synchronous rectification mode. When the monostable times out, the power MOS are turned on again after some delay set by the dead time to prevent cross conduction. Figure 17 shows the operation of the bridge in the slow decay mode. At the start of the off time, the lower power MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchronous rectification mode. When the monostable times out, the lower power MOS is turned on again after some delay set by the dead time to prevent cross conduction.
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L6228Q Figure 16. Fast decay mode output stage configurations
Circuit description
A) ON TIME
D01IN1335
B) 1μs DEAD TIME
C) QUASI-SYNCHRONOUS RECTIFICATION
D) 1μs SLOW DECAY
Figure 17. Slow decay mode output stage configurations
A) ON TIME
D01IN1336
B) 1μs DEAD TIME
C) SYNCHRONOUS RECTIFICATION
D) 1μs DEAD TIME
4.5
Stepping sequence generation
The phase sequence generator is a state machine that provides the phase and enable inputs for the two bridges to drive a stepper motor in either full step or half step. Two full step modes are possible, the normal drive mode where both phases are energized each step and the wave drive mode where only one phase is energized at a time. The drive mode is selected by the HALF/FULL input and the current state of the sequence generator as described below. A rising edge of the CLOCK input advances the state machine to the next state. The direction of rotation is set by the CW/CCW input. The RESET input resets the state machine to state 1.
4.6
Half step mode
A HIGH logic level on the HALF/FULL input selects half step mode. Figure 18 shows the motor current waveforms and the state diagram for the phase sequencer generator. At start-up or after a RESET the phase sequencer is at state 1. After each clock pulse the state changes following the sequence 1,2,3,4,5,6,7,8,… if CW/CCW is high (clockwise movement) or 1,8,7,6,5,4,3,2,… if CW/CCW is low (counterclockwise movement).
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Circuit description
L6228Q
4.7
Normal drive mode (full-step two-phase-on)
A LOW level on the HALF/FULL input selects the full step mode. When the low level is applied when the state machine is at an ODD numbered state the normal drive mode is selected. Figure 19 shows the motor current waveform state diagram for the state machine of the phase sequencer generator. The normal drive mode can easily be selected by holding the HALF/FULL input low and applying a RESET. At start -up or after a RESET the state machine is in state 1. While the HALF/FULL input is kept low, state changes following the sequence 1,3,5,7,… if CW/CCW is high (Clockwise movement) or 1,7,5,3,… if CW/CCW is low (Counterclockwise movement).
4.8
Wave drive mode (full-step one-phase-on)
A LOW level on the pin HALF/FULL input selects the full step mode. When the low level is applied when the state machine is at an EVEN numbered state the wave drive mode is selected. Figure 20 shows the motor current waveform and the state diagram for the state machine of the phase sequence generator. To enter the wave drive mode the state machine must be in an EVEN numbered state. The most direct method to select the Wave Drive Mode is to first apply a RESET, then while keeping the HALF/FULL input high apply one pulse to the clock input then take the HALF/FULL input low. This sequence first forces the state machine to state 1. The clock pulse, with the HALF/FULL input high advances the state machine from state 1 to either state 2 or 8 depending on the CW/CCW input. Starting from this point, after each clock pulse (rising edge) will advance the state machine following the sequence 2,4,6,8,… if CW/CCW is high (clockwise movement) or 8,6,4,2,… if CW/CCW is low (counterclockwise movement). Figure 18. Half step mode
IOUTA
3 4 5
2
6
IOUTB
1
8
7
Start Up or Reset
CLOCK
D01IN1320
1
2
3
4
5
6
7
8
Figure 19. Normal drive mode
IOUTA
3 4 5
2
6
IOUTB
1
8
7
Start Up or Reset
CLOCK
D01IN1322
1
3
5
7
1
3
5
7
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L6228Q Figure 20. Wave drive mode
IOUTA
3 4 5
Circuit description
2
6
IOUTB
1
8
7
CLOCK
Start Up or Reset
D01IN1321
2
4
6
8
2
4
6
8
4.9
Non-dissipative overcurrent protection
The L6228Q integrates an overcurrent detection circuit (OCD) for full protection. This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 21 shows a simplified schematic of the overcurrent detection circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold (typically 2.8 A) the OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3 V typical) by an internal open drain MOS with a pull down capability of 4 mA. By using an external R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs.
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Circuit description Figure 21. Overcurrent protection simplified schematic
OUT1A POWER SENSE 1 cell I1A POWER DMOS n cells I2A POWER DMOS n cells VSA OUT2A
L6228Q
HIGH SIDE DMOSs OF THE BRIDGE A
POWER SENSE 1 cell
TO GATE LOGIC
μC or LOGIC
+
OCD COMPARATOR I1A / n (I1A+I2A) / n I2A / n
VDD REN. CEN. EN RDS(ON) 40Ω TYP.
INTERNAL OPEN-DRAIN
IREF
OVER TEMPERATURE
OCD COMPARATOR
FROM THE BRIDGE B
D01IN1337
Figure 22 shows the overcurrent detection operation. The disable time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 23. The delay time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 24. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable delay time and the REN value should be chosen according to the desired disable time. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs disable time.
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L6228Q Figure 22. Overcurrent protection waveforms
IOUT ISOVER
Circuit description
VEN VDD Vth(ON) Vth(OFF) VEN(LOW)
ON OCD OFF ON BRIDGE OFF tOCD(ON) tEN(FALL) tD(OFF)EN tOCD(OFF) tEN(RISE) tD(ON)EN
D02IN1400
tDELAY
tDISABLE
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Circuit description Figure 23. tDISABLE versus CEN and REN (VDD = 5 V)
3 1 .1 0
L6228Q
R EN = 220 kΩ
R EN = 100 kΩ
R EN = 47 kΩ R EN = 33 kΩ R EN = 10 kΩ
tDISABLE [µs]
100
10
1
1
10
100
C E N [n F ]
Figure 24. tDELAY versus CEN (VDD = 5 V)
10
tdelay [μs]
1
0.1
1
10 Cen [nF]
100
4.10
Thermal protection
In addition to the overcurrent protection, the L6228Q integrates a thermal protection for preventing the device destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value).
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L6228Q
Application information
5
Application information
A typical bipolar stepper motor driver application using L6228Q is shown in Figure 25. Typical component values for the application are shown in Table 7. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6228Q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor connected from the EN input to ground sets the shut down time when an over current is detected (see overcurrent protection). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the dI/dt transients across the resistor. To increase noise immunity, unused logic pins (except EN) are best connected to 5 V (high logic level) or GND (low logic level) (see pin description). It is recommended to keep power ground and signal ground separated on PCB. Table 7. Component values for typical application
Component C1 C2 CA CB CBOOT CP CEN CREF D1 D2 RA RB REN RSENSEA RSENSEB Value 100 µF 100 nF 1 nF 1 nF 220 nF 10 nF 5.6 nF 68 nF 1N4148 1N4148 39 kΩ 39 kΩ 100 kΩ 0.6 Ω 0.6 Ω
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Application information Figure 25. Typical application
L6228Q
Note:
To reduce the IC thermal resistance, therefore improve the dissipation path, the NC pins can be connected to GND.
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Output current capability and IC power dissipation
6
Output current capability and IC power dissipation
In Figure 26, Figure 27, Figure 28 and Figure 29 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving a two-phase stepper motor, for different driving sequences:
● ● ● ●
HALF STEP mode (Figure 26) in which alternately one phase / two phases are energized. NORMAL DRIVE (FULL-STEP TWO PHASE ON) mode (Figure 27) in which two phases are energized during each step. WAVE DRIVE (FULL-STEP ONE PHASE ON) mode (Figure 27) in which only one phase is energized at each step. MICROSTEPPING mode (Figure 29), in which the current follows a sine-wave profile, provided through the Vref pins.
For a given output current and driving sequence the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125 °C maximum).
Figure 26. IC power dissipation versus output current in HALF STEP mode
H ALF STEP
10 8
IA IB
I OUT
6
PD [W]
4 2 0
I OUT Test Conditions: Supply Voltage = 24V No PWM f SW = 30 kHz (slow decay)
0 0.25 0.5 0.75 1 1.25 1.5
I OUT [A]
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Output current capability and IC power dissipation Figure 27. IC power dissipation versus output current in NORMAL mode (full step two phase on)
NORM AL DRIVE
10 8 6
L6228Q
IA
I OUT
IB I OUT
PD [W ]
4 2 0
Test Conditions: Supply Volt age =24 V
0 0.25 0.5 0.75 1 1.25 1.5
I OUT [A ]
No PWM f SW = 30 kHz (slow decay)
Figure 28. IC power dissipation versus output current in WAVE mode (full step one phase on)
WAVE DRIVE
10 8
IA IB
I OUT
6
PD [W]
4 2 0
I OUT Test Conditions: Supply Voltage = 24V
0 0.25 0.5 0.75 1 1.25 1.5
No PW M fSW = 3 0 kHz (slow decay)
I OUT [A]
Figure 29. IC power dissipation versus output current in MICROSTEPPING mode
MICROSTEPPING
10 8 6
IA
I OUT
I OUT IB
PD [W]
4 2 0
0
0.25 0.5 0.75 1
1.25 1.5
I OUT [A]
Test Conditions: Supply Voltage = 24V f SW = 30 kHz (slow decay) f SW = 50 kHz (slow decay)
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Thermal management
7
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. For instance, using a VFQFPN32L 5x5 package the typical Rth(JA) is about 42 °C/W when mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC).
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Package mechanical data
L6228Q
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 8. VFQFPN32 5x5x1.0 pitch 0.50
Databook (mm) Dim. Min A b b1 D D2 D3 E E2 E3 e L ddd 0.30 0.80 0.18 0.165 4.85 3.00 1.10 4.85 4.20 0.60 Typ 0.85 0.25 0.175 5.00 3.10 1.20 5.00 4.30 0.70 0.50 0.40 0.50 0.08 Max 0.95 0.30 0.185 5.15 3.20 1.30 5.15 4.40 0.80
Note:
VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no lead. Very thin profile: 0.80 < A < 1.00 mm. Details of terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features.
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L6228Q Figure 30. Package dimensions
Package mechanical data
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Order codes
L6228Q
9
Order codes
Table 9. Ordering information
Order code L6228Q VFQFPN32 5x5x1.0 mm L6228QTR Tape and reel Package Packaging Tube
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Revision history
10
Revision history
Table 10.
Date 14-Jan-2008 10-Jun-2008 28-Jan-2009 31-Aug-2010
Document revision history
Revision 1 2 3 4 First release Updated: Figure 25 on page 24 Added: Note 1 on page 4 Updated value in Table 3: Thermal data on page 4 Updated Table 9 Changes
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L6228Q
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