L6230

L6230 DMOS driver for three-phase brushless DC motor Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Operating supply voltage from 8 to 52 V 2.8 A output peak current (1.4 A RMS) RDS(on) 0.73 Ω typ. value @ TJ = 25 °C Integrated fast free wheeling diodes Operating frequency up to 100 kHz Non dissipative overcurrent detection and protection Cross conduction protection Diagnostic output Uncommitted comparator Thermal shutdown Under voltage lockout VFQFPN32 PowerSO36 Description The L6230 is a DMOS fully integrated threephase motor driver with overcurrent protection, optimized for FOC application thanks to the independent current senses. Realized in BCDmultipower technology, the device combines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip. An uncommitted comparator with open-drain output is available. Available in PowerSO36 and VFQFPN-32 5x5 packages the L6230 features a non dissipative overcurrent protection on the high side power MOSFETs and thermal shutdown. Application ■ ■ ■ BLDC motor driving Sinusoidal / 6-steps driving Field oriented control driving system Table 1. Device summary Order codes L6230PD PowerSO36 L6230PDTR L6230Q VFQFPN32 L6230QTR Tape and reel Tape and reel Tube Package Packaging Tube June 2011 Doc ID 18094 Rev 2 1/24 www.st.com 24 Contents L6230 Contents 1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 4 5 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 5.2 5.3 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 13 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 6.2 6.3 6.4 Field oriented control driving method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Six-step driving method with current control . . . . . . . . . . . . . . . . . . . . . . 16 Six-step driving method with BEMF zero crossing detection . . . . . . . . . . 17 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 Doc ID 18094 Rev 2 L6230 Block diagram 1 Block diagram Figure 1. Block diagram Doc ID 18094 Rev 2 3/24 Electrical data L6230 2 2.1 Table 2. Symbol VS VOD VBOOT VIN, VEN VCP-, VCP+ VSENSE IS(peak) IS Tstg, TOP Electrical data Absolute maximum ratings Absolute maximum ratings Parameter Supply voltage Differential voltage between: VSA, OUT1, OUT2, SENSEA and VSB, OUT3, SENSEB Bootstrap peak voltage Logic inputs voltage range Voltage range at CP- and CP+ pins Voltage range at SENSEx pins Pulsed supply current (for each VS pin) RMS supply current (for each VS pin) Storage and operating temperature range VSA = VSB = VS; TPULSE < 1 ms VSA = VSB = VS Parameter VSA = VSB = VS VSA = VSB = VS = 60 V; VSENSEx = GND VSA = VSB = VS Value 60 60 VS + 10 -0.3 to +7 -0.3 to +7 -1 to +4 3.55 1.4 -40 to 150 Unit V V V V V V A A °C 2.2 Table 3. Symbol VS VOD VCP-, VCP+ VCPCM VSENSE IOUT TJ fsw Recommended operating conditions Recommended operating conditions Parameter Supply voltage Parameter VSA = VSB = VS Min 8 Max 52 52 -0.1 0 pulsed tW < trr DC RMS output current Operating junction temperature Switching frequency -25 -6 -1 5 3 6 1 1.4 +125 100 Unit V V V V V V A °C kHz VSA = VSB = VS; Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, VSENSE1 = VSENSE2 = OUT1B, OUT2B, SENSEB VSENSE3 Voltage range at CP- and CP+ pins Common mode voltage at the comparator inputs Voltage range at pins SENSEx 4/24 Doc ID 18094 Rev 2 L6230 Electrical data 2.3 Thermal data Table 4. Symbol Thermal data Value Parameter PowerSO36 QFN32 42 2 Unit 36 16 63 °C/W °C/W °C/W °C/W Rth(j-amb)1 Maximum thermal resistance junction-ambient (1) Rth(j-amb)1 Maximum thermal resistance junction-ambient Rth(j-amb)2 Maximum thermal resistance junction-ambient (2) (3) Rth(j-amb)3 Maximum thermal resistance junction-ambient (4) 1. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm (with a thickness of 35 µm). 2. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm), 16 via holes and a ground layer. 3. Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board. 4. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC). Doc ID 18094 Rev 2 5/24 Pin connection L6230 3 Pin connection Figure 2. Pin connection PowerSO36 (top view) Figure 3. Pin connection VFQFPN32 (top view) Note: The pins 2 to 8 are connected to die PAD. The die PAD must be connected to GND pin. 6/24 Doc ID 18094 Rev 2 L6230 Pin connection Table 5. Pin VBOOT VCP Pin description Type Function Power supply Bootstrap voltage needed for driving the upper power MOSFETs. Output Charge pump oscillator output. Double function: chip Enable as input and Overcurrent/Over-temperature indication as output. LOW logic level switches OFF all Power MOSFETs, putting the power stages in high impedance status. An internal open drain transistor pulls to GND the pin when an overcurrent on one of the High Side MOSFETs is detected or during Thermal Protection. Logic input half bridge 1. Enable input half bridge 1. Logic input half bridge 2. Enable input half bridge 2. Logic input half bridge 3. Enable input half bridge 3. DIAG-EN Logic output/input IN1 EN1 IN2 EN2 IN3 EN3 CPCP+ CPOUT SENSE3 OUT3 VSB SENSE2 OUT2 SENSE1 OUT1 VSA GND Logic input Logic input Logic input Logic input Logic input Logic input Analog input Inverting input of internal comparator. Analog input Non-Inverting input of internal comparator. Output Open-drain output of internal comparator. Half bridge 3 source pin. This pin must be connected to power ground through a sensing power resistor. Power output Output half bridge 3. Power supply Half bridge 3 power supply voltage. it must be connected to the supply voltage together with pin VSA. Half bridge 2 source pin. This pin must be connected to power ground through a sensing power resistor. Power output Output half bridge 2. Half bridge 1 source pin. This pin must be connected to power ground through a sensing power resistor. Power output Output half bridge 1. Power supply Ground Half bridge 1 and half bridge 2 power supply voltage. It must be connected to the supply voltage together with pin VSB. Ground terminal. Doc ID 18094 Rev 2 7/24 Electrical characteristics L6230 4 Electrical characteristics (VS = 48 V, TA = 25 °C, unless otherwise specified) Table 6. Symbol VSth(ON) VSth(OFF) IS Tj(OFF) Electrical characteristics Parameter Turn-on threshold Turn-off threshold Quiescent supply current Thermal shutdown temperature All bridges OFF; TJ = -25 °C to 125 °C(1) Test condition Min 5.8 5 Typ 6.3 5.5 5 165 Max 6.8 6 10 Unit V V mA °C Output DMOS transistors RDS(on) IDSS High-side / low-side switch ON resistance Leakage current TJ = 25 °C TJ =125 °C (1) 0.73 1.18 0.85 1.35 2 Ω Ω mA mA DIAG-EN = LOW; OUT = VS DIAG-EN = LOW; OUT = GND -0.3 Source drain diodes VSD trr tfr Forward ON voltage Reverse recovery time Forward recovery time ISD = 1.4 A, DIAG-EN = LOW If = 1.4 A 1.15 300 200 1.3 V ns ns Logic inputs (INx, ENx, DIAG-EN) VIL VIH IIL IIH Low level logic input voltage High level logic input voltage Low level logic input current High level logic input current GND logic input voltage 7 V logic input voltage 2 -10 10 0.8 V V µA µA Switching characteristics tD(ON)EN tD(OFF)EN tD(ON)IN tD(OFF)IN tRISE tFALL tDT fCP Enable to output turn-on delay time (2) Enable to output turn-off delay time (2) Other logic inputs to OUT turn-ON delay time ILOAD = 1.4 A, resistive load Other logic inputs to OUT turn-OFF delay time Output rise time (2) Output fall time Dead time Charge pump frequency TJ = -25 °C to 125 °C (1) (2) 500 500 650 800 1000 ns ns µs ns 1.6 800 40 40 0.5 1 0.6 1 250 250 ns ns µs MHz 8/24 Doc ID 18094 Rev 2 L6230 Table 6. Symbol Comparator VOFFSET tprop IBIAS RCPOUT Offset voltage Propagation delay Inputs bias current Open drain ON resistance VCP- = 0.5 V (3) Electrical characteristics Electrical characteristics (continued) Parameter Test condition Min Typ Max Unit -14 500 +14 mV ns 10 40 60 µA Ω Over current detection and protection ISOVER RDIAG tOCD(ON) tOCD(OFF) Supply overcurrent protection threshold TJ = -25 to 125 °C (1) Open drain ON resistance OCD turn-ON delay time (4) 2 2.8 40 200 100 3.55 60 A Ω ns ns IDIAG = 4 mA IDIAG = 4 mA; CDIAG < 100 pF IDIAG = 4 mA; CDIAG < 100 pF OCD turn-OFF delay time (4) 1. Tested at 25 °C in a restricted range and guaranteed by characterization 2. See Figure 4. 3. Measured applying a voltage of 1 V to pin CP+ and a voltage drop from 2 V to 0 V to pin CP-. 4. See Figure 5. Figure 4. Switching characteristic definition DIAG-EN Vth(ON) Vth(OFF) t IOUT 90% 10% D01IN1316 t tFALL tD(OFF)EN tD(ON)EN tRISE Doc ID 18094 Rev 2 9/24 Electrical characteristics Figure 5. Overcurrent detection timing definition L6230 IOUT ISOVER ON BRIDGE OFF VDIAG-EN 90% 10% tOCD(ON) tOCD(OFF) D02IN1387 10/24 Doc ID 18094 Rev 2 L6230 Circuit description 5 5.1 Circuit description Power stages and charge pump The L6230 integrates a three-phase bridge, which consists of 6 power MOSFETs connected as shown on the block diagram (see Figure 1), each power MOS has an RDS(ON) = 0.73 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Cross conduction protection is implemented by using a dead time (tDT = 1 µs typical value) set by internal timing circuit between the turn off and turn on of two power MOSFETs in one leg of a bridge. Pins VSA and VSB must be connected together to the supply voltage (VS). Using N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in Figure 6. The oscillator output (pin VCP) is a square wave at 600 kHz (typically) with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table 7. Table 7. Charge pump external component values Component CBOOT CP D1 D2 Value 220 nF 10 nF 1N4148 1N4148 Figure 6. Charge pump circuit VS D1 D2 CBOOT CP VCP VBOOT VSA VSB Doc ID 18094 Rev 2 11/24 Circuit description L6230 5.2 Logic inputs Pins INx and ENx are TTL/CMOS and microcontroller compatible logic inputs. The internal structure is shown in Figure 7. Typical value for turn-on and turn-off thresholds are respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V. Pin DIAG-EN has identical input structure with the exception that the drain of the Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving this pin. The EN input may be driven in one of two configurations as shown in Figure 8 or Figure 9. If driven by an open drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Figure 8. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Figure 9. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 10 kΩ and 5.6 nF. More information on selecting the values is found in the overcurrent protection section. Figure 7. Logic inputs internal structure 5V ESD PROTECTION D01IN1329 Figure 8. Pin DIAG-EN open collector driving 5V REN OPEN COLLECTOR OUTPUT DIAG-EN 5V CEN ESD PROTECTION D01IN1330 Figure 9. Pin DIAG-EN push-pull driving 5V REN PUSH-PULL OUTPUT DIAG-EN CEN ESD PROTECTION D01IN1331 12/24 Doc ID 18094 Rev 2 L6230 Circuit description 5.3 Non-dissipative overcurrent detection and protection The L6230 integrates an overcurrent detection circuit (OCD) for full protection. This circuit provides output-to-output and output-to-ground short circuit protection as well. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 10 shows a simplified schematic for the overcurrent detection circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on. The pin DIAG-EN can be used to signal the fault condition to a μC and to shut down the three-phase bridge simply by connecting the pin to an external R-C (see REN, CEN). Figure 10. Overcurrent protection simplified schematic OUT1 VSA OUT2 OUT3 VSB HIGH SIDE DMOS I1 POWER SENSE 1 cell TO GATE LOGIC REN CEN RDS(ON) 40Ω TYP. DIAG\EN POWER DMOS n cells HIGH SIDE DMOS I2 POWER DMOS n cells POWER SENSE 1 cell I3 HIGH SIDE DMOS μC or LOGIC POWER DMOS n cells POWER SENSE 1 cell VDD + I1 / n I1+I2 / n I2/ n OCD COMPARATOR INTERNAL OPEN-DRAIN IREF OVER TEMPERATURE I3/ n IREF D02IN1381 Figure 11 shows the overcurrent detection operation. The disable time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 12. The delay time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 13 CEN is also used for providing immunity to pin DIAG\EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable delay time and the REN value should be chosen according to the desired disable time. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs disable time. Doc ID 18094 Rev 2 13/24 Circuit description Figure 11. Overcurrent protection waveforms IOUT ISOVER L6230 DIAG-EN VDD Vth(ON) Vth(OFF) VEN(LOW) ON OCD OFF ON BRIDGE OFF tOCD(ON) tEN(FALL) tD(OFF)EN tOCD(OFF) tEN(RISE) tD(ON)EN D02IN1383 tDELAY tDISABLE Figure 12. tDISABLE versus CEN and REN 3 1 .1 0 R EN = 220 kΩ R EN = 100 kΩ R EN = 47 kΩ R EN = 33 kΩ R EN = 10 kΩ tDISABLE [µs] 100 10 1 1 10 100 C E N [n F ] Figure 13. tDELAY versus CEN 10 tdelay [μs] 1 0.1 1 10 Cen [nF] 100 14/24 Doc ID 18094 Rev 2 L6230 Application information 6 Application information Some typical applications using L6230 are shown in this paragraph. A high quality ceramic capacitor (C2) in the range of 100 nF to 200 nF should be placed between the power pins VSA and VSB and ground near the L6230 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor (CEN) connected from the DIAG-EN input to ground sets the shut down time when an over current is detected (see overcurrent protection). The current sensing inputs (SENSEX) should be connected to the sensing resistors RSENSE with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the dI/dt transients across the resistors. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) (see pin description). It is recommended to keep power ground and signal ground separated on PCB. Table 8. Component values for typical application Component C1 C2 CBOOT CEN CP D1 D2 REN Value 100 µF 100 nF 220 nF 5.6 nF 10 nF 1N4148 1N4148 100 kΩ The examples reported describe some typical application to drive a 3-phase BLDC motor using L6230 device. In the first example is shown a field oriented control (FOC) system, with this method it is possible to provide smooth and precise motor control of BLDC motors. A six-step driving method with current control is reported in the second example, the inputs sequence is generated by external controller and the L6230 comparator is used to obtain the information for the peak current control. Finally, the third example shows how to implement a sensorless motor control system, the information on rotor position is achieved by BEMF zero-crossing detection. 6.1 Field oriented control driving method In this configuration (see Figure 14) three sensing resistors are required, one for each channel. The sensing signals coming from the output power stage are conditioned by external operational amplifiers which provide the proper feedback signals to the AtoD converter and the system controller. According to the feedback signals the six input lines are generated by the controller. Note that some filtering and level shifting RC networks should be added between the sense resistor and the correspondent op-amp input. Doc ID 18094 Rev 2 15/24 Application information The uncommitted internal comparator with open-drain output is available. Figure 14. F.O.C. typical application L6230 6.2 Six-step driving method with current control In this configuration only one sense resistor are needed, the three OUT pins are connected together to RSENSE (see Figure 15). The non-inverting input comparator CP+ monitors the voltage drop across the external sense resistor connected between the source of the three lower power MOS transistors and ground. As the current in the motor increases the voltage across the RSENSE increases proportionally. When the voltage drop across the sense resistor becomes greater than the reference voltage applied at inverting input CP- the comparator open-drain output is switched on pulling down the CPOUT pin. This signal could be managed by controller to generate the proper input sequence for sixstep driving method with current control and select what current decay method to implement. When the sense voltage decrease below the CP- voltage, the open-drain is switched off and the voltage at CPOUT pin start to increase charging the capacitor C3. The reference voltage at pin CP- will be set according to sense resistor value and the desired regulated current (VCP- { RSENSE x ITARGET). A very simple way to obtain variable voltage is to low-pass filter a PWM output of a controller. 16/24 Doc ID 18094 Rev 2 L6230 Figure 15. Six-step with current control typical application Application information 6.3 Six-step driving method with BEMF zero crossing detection The BEMF zero crossing information can be used to evaluate the rotor position; in this way no Hall effect sensors or encoder are needed. In six-step driving mode one of the three phases is left in high impedance state. Comparing the voltage of this phase with the center-tap voltage we can detect the BEMF zero-crossing. In shown example (see Figure 16), the OUT1 phase voltage is monitored by the CP+; the center-tap voltage is obtained as combination of three phase voltages and monitored by the CP- pin. Only when the OUT1 is in high impedance, the CPOUT will perform a commutation each time a BEMF zero crossing is detected. In this configuration one sense resistor is needed, the three OUT pins are connected together to RSENSE. Doc ID 18094 Rev 2 17/24 Application information Figure 16. Six-step with zero crossing detection typical application L6230 6.4 Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. For instance, using a VFQFPN32L 5 x 5 package the typical Rth(JA) is about 42 °C/W when mounted on a double-layer FR4 PCB with a dissipating copper area of 0.5 cm2 on the top side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC). Otherwise, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board with 6cm2 dissipating footprint (copper thickness of 35 µm), the Rth(jA) is about 35°C/W. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15°C/W. 18/24 Doc ID 18094 Rev 2 L6230 Package mechanical data 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 9. VFQFPN 5 x 5 x 1.0, 32 lead, pitch 0.50 Databook (mm) Dim. Min A b b1 D D2 D3 E E2 E3 e L ddd 0.30 0.80 0.18 0.165 4.85 3.00 1.10 4.85 4.20 0.60 Typ 0.85 0.25 0.175 5.00 3.10 1.20 5.00 4.30 0.70 0.50 0.40 0.50 0.08 Max 0.95 0.30 0.185 5.15 3.20 1.30 5.15 4.40 0.80 Note: VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no lead. Very thin profile: 0.80 < A < 1.00 mm. Details of terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features. Doc ID 18094 Rev 2 19/24 Package mechanical data Figure 17. Package dimensions L6230 20/24 Doc ID 18094 Rev 2 L6230 Package mechanical data Table 10. PowerSO36 mechanical data Min. A a1 a2 a3 b c 0 0.22 0.23 15.8 9.4 13.9 0.65 11.05 10.9 11.1 2.9 5.8 2.9 0 15.5 6.2 3.2 0.1 15.9 1.1 0.8 10°(max.) 8 °(max.) 1.1 0.1 Typ. Max. 3.6 0.3 3.3 0.1 0.38 0.32 16 9.8 14.5 D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S Doc ID 18094 Rev 2 21/24 Package mechanical data Figure 18. PowerSO36 mechanical drawings L6230 22/24 Doc ID 18094 Rev 2 L6230 Revision history 8 Revision history Table 11. Date 14-Oct-2010 07-Jun-2011 Document revision history Revision 1 2 First release Updated maturity status from preliminary data to final datasheet. Changes Doc ID 18094 Rev 2 23/24 L6230 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 24/24 Doc ID 18094 Rev 2