L6235Q

L6235Q DMOS driver for 3-phase brushless dc motor Features ■ Operating supply voltage from 8 to 52 V ■ 5.6 A output peak current ■ RDS(on) 0.3 Ω typ. value @ TJ = 25 °C ■ Operating frequency up to 100 kHz ■ Non-dissipative overcurrent protection ■ Diagnostic output ■ Constant tOFF PWM current controller ■ Slow decay synchronous rectification ■ 60° and 120° Hall effect decoding logic ■ Brake function ■ Tacho output for speed loop ■ Cross conduction protection ■ Thermal shutdown ■ Undervoltage lockout ■ Integrated fast freewheeling diodes Figure 1. QFN-48 (7 x 7 mm) Description The L6235Q is a DMOS fully integrated 3-phase motor driver with overcurrent protection. Realized in BCDmultipower technology, the device combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. The device includes all the circuitry needed to drive a 3-phase BLDC motor including: a 3-phase DMOS bridge, a constant OFF time PWM current controller and the decoding logic for single ended Hall sensors that generates the required sequence for the power stage. Available in QFN48 7x7 package, the L6235Q features a nondissipative overcurrent protection on the high-side power MOSFETs and thermal shutdown. Block diagram VBOOT VCP VBOOT VBOOT CHARGE PUMP VSA THERMAL PROTECTION OCD1 DIAG OUT1 10V OCD1 OCD2 OCD OCD OCD3 VBOOT EN BRAKE FWD/REV OCD2 H3 HALL-EFFECT SENSORS DECODING LOGIC H2 GATE LOGIC SENSEA VBOOT H1 RCPULSE OUT2 10V TACHO MONOSTABLE VSB OCD3 OUT3 10V TACHO 10V 5V SENSEB PWM VOLTAGE REGULATOR ONE SHOT MONOSTABLE MASKING TIME + SENSE COMPARATOR - VREF RCOFF AM02555v1 November 2011 Doc ID 018997 Rev 2 1/33 www.st.com 33 Contents L6235Q Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 Tacho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 18 4.8 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Output current capability and IC power dissipation . . . . . . . . . . . . . . 25 7 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/33 Doc ID 018997 Rev 2 L6235Q Electrical data 1 Electrical data 1.1 Absolute maximum ratings Table 1. Symbol VS Parameter Parameter Value Unit Supply voltage VSA = VSB = VS 60 V Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS = 60 V; VSENSEA = VSENSEB = GND 60 V Bootstrap peak voltage VSA = VSB = VS VS + 10 V Input and enable voltage range -0.3 to +7 V Voltage range at pin VREF -0.3 to +7 V VRCOFF Voltage range at pin RCOFF -0.3 to +7 V VSENSE Voltage range at pins SENSEA and SENSEB -1 to +4 V IS(peak) Pulsed supply current (for each VSA and VSB pin) VSA = VSB = VS; tPULSE < 1 ms 7.1 A IS DC supply current (for each VSA and VSB pin) VSA = VSB = VS 2.5 A -40 to 150 °C VOD VBOOT VIN,VEN VREF Tstg, TOP 1.2 Absolute maximum ratings Storage and operating temperature range Recommended operating conditions Table 2. Symbol VS Recommended operating conditions Parameter Parameter Supply voltage VSA = VSB = VS VOD Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS; VSENSEA = VSENSEB VREF Voltage range at pin VREF VSENSE IOUT Min. 8 Max. Unit 52 V 52 V -0.1 5 V Voltage range at pins SENSEA and SENSEB Pulsed tW < trr -6 6 V DC -1 1 V DC output current VSA = VSB = VS; 2.5 A +125 °C 100 kHz Tj Operating junction temperature fsw Switching frequency Doc ID 018997 Rev 2 -25 3/33 Pin connection Pin connection DIAG H1 H3 H2 45 44 43 42 41 OUT2 SENSEA 46 NC SENSEA 47 VCP NC 48 OUT2 RCOFF Pin connection (top view) 40 39 38 37 36 NC 35 VSA 3 34 VSA NC 4 33 NC NC 5 32 NC GND 6 31 GND NC 7 30 NC NC 8 29 NC NC 9 28 NC NC 10 27 VSB NC 11 26 VSB TACHO 12 25 NC 18 19 20 21 22 23 24 OUT3 NC 17 OUT3 16 VBOOT 15 BRAKE 14 EN 13 VREF OUT1 EPAD SENSEB OUT1 2 FWD/REV 1 SENSEB NC NC Figure 2. RCPULSE 2 L6235Q Note: The exposed PAD must be connected to GND pin. Table 3. Pin description AM02556v1 Pin Name Type 43 H1 Sensor input 44 DIAG Open drain output 45, 46 SENSEA Power supply 48 RCOFF RC pin 2, 3 OUT1 Power output 6, 31 GND GND 12 TACHO Open drain output Frequency-to-voltage open drain output. Every pulse from pin H1 is shaped as a fixed and adjustable length pulse. 13 RCPULSE RC pin RC network pin. A parallel RC network connected between this pin and ground sets the duration of the monostable pulse used for the frequency-to-voltage converter. 4/33 Function Single ended Hall effect sensor input 1. Overcurrent detection and thermal protection pin. An internal open drain transistor pulls to GND when an overcurrent on one of the high-side MOSFETs is detected or during thermal protection. Half bridge 1 and half bridge 2 source pin. This pin must be connected together with pin SENSEB to power ground through a sensing power resistor. RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF time. Output 1 Ground terminals. Doc ID 018997 Rev 2 L6235Q Table 3. Pin Pin connection Pin description (continued) Name Type Function Half bridge 3 source pin. This pin must be connected together with pin SENSEA to power ground through a sensing power resistor. At this pin also the inverting input of the sense comparator is connected. 15, 16 SENSEB Power supply 17 FWD/REV Logic input Selects the direction of the rotation. High logic level sets forward operation, whereas low logic level sets reverse operation. If not used, it must be connected to GND or +5 V. 18 EN Logic input Chip enable. Low logic level switches off all power MOSFETs. If not used, it must be connected to +5 V. 19 VREF Logic input Current controller reference voltage. Do not leave this pin open or connect to GND. 20 BRAKE Logic input Brake input pin. Low logic level switches on all high-side power MOSFETs, implementing the brake function. If not used, it must be connected to +5 V. 21 VBOOT 22, 23 OUT3 Power output Output 3. 26, 27 VSB Power supply Half bridge 3 power supply voltage. It must be connected to the supply voltage together with pin VSA. 34, 35 VSA Power supply Half bridge 1 and half bridge 2 power supply voltage. It must be connected to the supply voltage together with pin VSB. 38, 39 OUT2 Power output Output 2. 40 VCP Output 41 H2 Sensor input Single ended Hall effect sensor input 2. 42 H3 Sensor input Single ended Hall effect sensor input 3. Supply voltage Bootstrap voltage needed for driving the upper power MOSFETs. Charge pump oscillator output. Doc ID 018997 Rev 2 5/33 Electrical characteristics 3 L6235Q Electrical characteristics VS = 48 V, TA = 25 °C, unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit VSth(ON) Turn-on threshold 6.6 7 7.4 V VSth(OFF) Turn-off threshold 5.6 6 6.4 V 5 10 mA IS Tj(OFF) All bridges OFF; Tj = -25 °C to 125 °C (1) Quiescent supply current Thermal shutdown temperature 165 °C Output DMOS transistors High-side switch ON resistance RDS(ON) Low-side switch ON resistance IDSS Tj = 25 °C 0.34 0.4 Tj =125 °C (1) 0.53 0.59 Tj = 25 °C 0.28 0.34 Tj =125 °C (1) 0.47 0.53 EN = low; OUT = VS Leakage current EN = low; OUT = GND 2 -0.15 Ω mA mA Source drain diodes VSD Forward ON voltage ISD = 2.5 A, EN = low 1.15 1.3 V trr Reverse recovery time If = 2.5 A 300 ns tfr Forward recovery time 200 ns Logic input (H1, H2, H3, EN, FWD/REV, BRAKE) VIL Low level logic input voltage -0.3 0.8 V VIH High level logic input voltage 2 7 V IIL Low level logic input current GND logic input voltage IIH High level logic input current 7 V logic input voltage -10 µA 1.8 10 µA 2.0 V Vth(ON) Turn-on input threshold Vth(OFF) Turn-off input threshold 0.8 1.3 V Vth(HYS) Input threshold hysteresis 0.25 0.5 V Switching characteristics tD(on)EN Enable to out turn ON delay time (2) ILOAD =2.5 A, resistive load 100 250 400 ns tD(off)EN Enable to out turn OFF delay time (2) ILOAD =2.5 A, resistive load 300 550 800 ns tD(on)IN Other logic inputs to output turn ON delay time ILOAD =2.5 A, resistive load 2 ns tD(off)IN Other logic inputs to out turn OFF delay time ILOAD =2.5 A, resistive load 2 ns 6/33 Doc ID 018997 Rev 2 L6235Q Table 4. Electrical characteristics Electrical characteristics (continued) Symbol Parameter Test condition (2) tRISE Output rise time tFALL Output fall time (2) tDT Dead time protection fCP Charge pump frequency Min. Typ. Max. Unit ILOAD =2.5 A, resistive load 40 250 ns ILOAD =2.5 A, resistive load 40 250 ns 0.5 Tj = -25 °C to 125 °C (7) 1 0.6 µs 1 MHz PWM comparator and monostable IRCOFF Source current at pin RCOFF Voffset Offset voltage on sense comparator VRCOFF = 2.5 V 3.5 VREF = 0.5 V (3) tPROP Turn OFF propagation delay tBLANK Internal blanking time on SENSE comparator tON(MIN) Minimum ON time 5.5 mA ±5 mV 500 ns 1 µs 1.5 tOFF PWM recirculation time IBIAS Input bias current at pins VREFA and VREFB 2 µs ROFF = 20 kΩ; COFF = 1 nF 13 µs ROFF = 100 kΩ; COFF = 1 nF 61 µs 10 µA Tacho monostable IRCPULSE Source current at pin RCPULSE tPULSE Monostable of time RTACHO Open drain ON resistance VRCPULSE = 2.5 V 3.5 5.5 mA RPUL = 20 kΩ; CPUL =1 nF 12 µs RPUL = 100 kΩ; CPUL =1 nF 60 µs 40 60 Ω 5.6 7.1 A 60 Ω Over current detection e protection Isover ROPDR IOH tOCD(ON) tOCD(OFF) Supply overcurrent protection threshold -25 °C t RCRISE – t DT ⎩ t RCRISE = 600 ⋅ C OFF Figure 12 shows the lower limit for the ON time tON for having a good PWM current regulation capacity. It should be mentioned that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues to work but the OFF time tOFF is not more constant. Therefore, a small COFF value gives more flexibility to the applications (allows smaller ON time and, therefore, higher switching frequency), but, the smaller the value for COFF, the more influential the noises on the circuit performance. Figure 11. tOFF vs. COFF and ROFF 4 1 .10 R off = 100kΩ 3 1 .10 R off = 47kΩ toff [μs] R off = 20kΩ 100 10 1 0.1 1 10 100 Coff [nF] Doc ID 018997 Rev 2 13/33 Circuit description L6235Q Figure 12. Area where tON can vary maintaining the PWM regulation ton(min) [μs] 100 10 1.5μs (typ. value) 1 0.1 1 10 Coff [nF] 14/33 Doc ID 018997 Rev 2 100 L6235Q 4.4 Circuit description Slow decay mode Figure 13 shows the operation of the bridge in slow decay mode during the OFF time. At any time only two legs of the 3-phase bridge are active, therefore, only the two active legs of the bridge are shown in the figure and the third leg is off. At the start of the OFF time, the lower power MOSFET is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the dead time the upper power MOSFET is operated in the synchronous rectification mode reducing the impedance of the freewheeling diode and the related conducting losses. When the monostable times out, the upper power MOSFET that was operating the synchronous mode turns off and the lower power MOSFET is turned on again after some delay set by the dead time to prevent cross conduction. Figure 13. Slow decay mode output stage configurations B) 1μs DEAD TIME A) ON TIME D01IN1336 4.5 C) SYNCHRONOUS RECTIFICATION D) 1μs DEAD TIME Decoding logic The decoding logic section is a combinatory logic that provides the appropriate driving of the 3-phase bridge outputs according to the signals coming from the three Hall sensors that detect rotor position in a 3-phase BLDC motor. This novel combinatory logic discriminates between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a universal IC without dedicating pins to select the sensor configuration. There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 14, positions 1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b). Four of them are used in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phasing (3b and 6b). The decoder can drive motors with different sensor configurations simply by following Table 2. For any input configuration (H1, H2 and H3) there is one output configuration (OUT1, OUT2 and OUT3). The output configuration 3a is the same as 3b and analogously output configuration 6a is the same as 6b. The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive the motor with all four conventions by changing the direction set. Doc ID 018997 Rev 2 15/33 Circuit description L6235Q Table 6. 60 and 120 electrical degree decoding logic in forward direction Hall 120° 1 2 3a - 4 5 6a - Hall 60° 1 2 - 3b 4 5 - 6b H1 H H L H L L H L H2 L H H H H L L L H3 L L L H H H H L OUT1 Vs High Z GND GND GND High Z Vs Vs OUT2 High Z Vs Vs Vs High Z GND GND GND OUT3 GND GND High Z High Z Vs Vs High Z High Z Phasing 1->3 2->3 2->1 2->1 3->1 3->2 1->2 1->2 Figure 14. 120° Hall sensor sequence H1 H3 H1 H2 H3 H2 1 =H H1 2 H3 H1 H2 H3 H1 H2 3a 4 H3 H1 H2 5 H3 H2 6a =L Figure 15. 60° Hall sensor sequence H1 H1 H2 H3 4.6 H2 H3 1 =H H1 H2 H3 2 H1 3b H1 H2 H3 4 H1 H2 H3 5 H2 H3 6b =L Tacho The tachometer function consists of a monostable, with constant OFF time (tPULSE), whose input is one Hall effect signal (H1). It allows to develop an easy speed control loop by using an external op amp, as shown in Figure 17. For component values refer to Section 5. The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall effect sensors H1, the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time tPULSE (see Figure 16). The OFF time tPULSE can be set using the external RC network (RPUL, CPUL) connected to the pin RCPULSE. Figure 18 gives the relation between tPULSE and CPUL, RPUL. It is approximately: tPULSE = 0.6 · RPUL · CPUL 16/33 Doc ID 018997 Rev 2 L6235Q Circuit description where CPUL should be chosen in the range 1 nF … 100 nF and RPUL in the range 20 kΩ … 100 kΩ. By connecting the tachometer pin to an external pull-up resistor, the output signal average value VM is proportional to the frequency of the Hall effect signal and, therefore, to the motor speed. This realizes a simple frequency-to-voltage converter. An op amp, configured as an integrator, filters the signal and compares it with a reference voltage VREF, which sets the speed of the motor. t PULSE V M = ------------------ ⋅ V DD T Figure 16. Tacho operation waveforms H1 H2 H3 VTACHO VDD VM t PULSE T Figure 17. Tachometer speed control loop H1 RCPULSE TACHO MONOSTABLE VDD RPUL R3 RDD CPUL TACHO C1 R4 VREF R1 VREF CREF2 R2 Doc ID 018997 Rev 2 CREF1 17/33 Circuit description L6235Q Figure 18. tPULSE vs. CPUL and RPUL 4 1 .10 R PUL = 100kΩ R PUL = 47kΩ 3 1 .10 tpulse [μs] R PUL = 20kΩ 100 10 1 4.7 10 Cpul [nF] 100 Non-dissipative overcurrent detection and protection The L6235Q integrates an overcurrent detection circuit (OCD) for full protection. With this internal overcurrent detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 19 shows a simplified schematic of the overcurrent detection circuit. To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high-side power MOSFET. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold (typically ISOVER = 5.6 A), the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOSFET with a pull-down capability of 4 mA connected to pin DIAG is turned on. Pin DIAG can be used to signal the fault condition to a µC or to shut down the 3-phase bridge simply by connecting it to pin EN and adding an external R-C (see REN, CEN). 18/33 Doc ID 018997 Rev 2 L6235Q Circuit description Figure 19. Overcurrent protection simplified schematic OUT1 VSA I1 μC or LOGIC VDD REN VSB HIGH SIDE DMOS I2 POWER DMOS n cells POWER DMOS n cells I3 POWER SENSE 1 cell POWER DMOS n cells POWER SENSE 1 cell + OCD COMPARATOR EN OUT3 HIGH SIDE DMOS HIGH SIDE DMOS POWER SENSE 1 cell TO GATE LOGIC OUT2 I1 / n I2/ n I1+I2 / n CEN INTERNAL OPEN-DRAIN DIAG RDS(ON) 40Ω TYP. IREF OVER TEMPERATURE I 3/ n IREF AM02563v1 Figure 20 shows the overcurrent detection operation. The disable time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected by both CEN and REN values and its magnitude is reported in Figure 21. The delay time tDELAY before turning off the bridge, when an overcurrent has been detected, depends only on the CEN value. Its magnitude is reported in Figure 22. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable delay time and the REN value should be chosen according to the desired disable time. The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF which allow to obtain 200 µs disable time. Doc ID 018997 Rev 2 19/33 Circuit description L6235Q Figure 20. Overcurrent protection waveforms IOUT ISOVER VEN=VDIAG VDD Vth(ON) Vth(OFF) VEN(LOW) ON OCD OFF ON tDELAY BRIDGE tDISABLE OFF tOCD(ON) tEN(FALL) tOCD(OFF) tEN(RISE) tD(ON)EN tD(OFF)EN AM02564v1 20/33 Doc ID 018997 Rev 2 L6235Q Circuit description Figure 21. tDISABLE vs. CEN and REN (VDD = 5 V) R EN = 220 kΩ 3 1 .1 0 R EN = 100 kΩ R EN = 47 kΩ R EN = 33 kΩ tDISABLE [µs] R EN = 10 kΩ 100 10 1 1 10 100 C E N [n F ] Figure 22. tDELAY vs. CEN (VDD = 5 V) tdelay [μs] 10 1 0.1 1 10 Cen [nF] Doc ID 018997 Rev 2 100 21/33 Circuit description 4.8 L6235Q Thermal protection In addition to the overcurrent detection, the L6235Q integrates a thermal protection to prevent device destruction in case of junction overtemperature. It works sensing the die temperature by means of a sensitive element integrated in the die. The device switches off when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value). 22/33 Doc ID 018997 Rev 2 L6235Q 5 Application information Application information A typical application using L6235Q is shown in Figure 23. Typical component values for the application are shown in Table 7. A high quality ceramic capacitor (C2) in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6235Q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors (CEN) connected from the EN input to ground sets the shutdown time when an overcurrent is detected (see Section 4.7). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistors RSENSE with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level) (see Section 2). It is recommended to keep power ground and signal ground separated on the PCB. Table 7. Component values for typical application Component Value C1 100 uF C2 100 nF C3 220 nF CBOOT 220 nF COFF 1 nF CPUL 10 nF CREF1 33 nF CREF2 100 nF CEN 5.6 nF CP 10 nF D1 1N4148 D2 1N4148 R1 5K6Ω R2 1K8Ω R3 4K7Ω R4 1 MΩ RDD 1 KΩ REN 100 kΩ RP 100 Ω RSENSE 0.3 Ω ROFF 33 kΩ RPUL 47 kΩ RH1, RH2, RH3 10 kΩ Doc ID 018997 Rev 2 23/33 Application information L6235Q Figure 23. Typical application + VS 8-52VDC VSA C1 C2 POWER GROUND - VSB D1 RP CP VCP 34, 35 40 SIGNAL GROUND 44 VBOOT RSENSE THREE-PHASE MOTOR SENSEA SENSEB OUT1 HALL SENSOR +5V RH1 M OUT2 OUT3 H1 RH2 H2 RH3 H3 GND 21 18 2, 3 38, 39 22, 23 + VREF CREF2 R2 C3 DIAG R4 EN REN ENABLE CEN 45, 46 15, 16 R1 VREF CREF1 26, 27 D2 CBOOT 19 17 20 12 FWD/REV BRAKE BRAKE TACHO R3 FWD/REV COFF RDD 43 41 48 RCOFF 42 5V ROFF CPUL 6, 31 RCPULSE 13 RPUL AM02566v1 Note: 24/33 To reduce the IC thermal resistance, therefore improving the dissipation path, the NC pins can be connected to GND. Doc ID 018997 Rev 2 L6235Q 6 Output current capability and IC power dissipation Output current capability and IC power dissipation Figure 24 shows the approximate relation between the output current and the IC power dissipation using PWM current control. For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large the onboard copper dissipating area must be to guarantee a safe operating junction temperature (125 °C maximum). Figure 24. IC power dissipation vs. output power I1 IOUT 10 I2 8 PD [W] 6 IOUT I3 IOUT 4 Test Condition s: Supply Voltage = 24 V 2 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] No PWM fSW = 30 kHz (slow decay) AM02570v1 Doc ID 018997 Rev 2 25/33 Thermal management 7 L6235Q Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Selecting the appropriate package and heatsinking configuration for the application is required to maintain the IC within the allowed operating temperature range for the application. 26/33 Doc ID 018997 Rev 2 L6235Q 8 Electrical characteristics curves Electrical characteristics curves Figure 25. Typical quiescent current vs. supply voltage Figure 26. Typical high-side RDS(on) vs. supply voltage Iq [m A] 5.6 RDS(ON) [Ω] fsw = 1kHz 0.380 Tj = 25°C 0.376 Tj = 85°C 5.4 0.372 Tj = 25°C 0.368 Tj = 125°C 0.364 5.2 0.360 0.356 5.0 0.352 0.348 4.8 0.344 0.340 0.336 4.6 0 10 20 30 V S [V] 40 50 60 0 5 10 15 AM02572v1 Figure 27. Normalized typical quiescent current vs. switching frequency 20 25 VS [V] 30 AM02573v1 Figure 28. Normalized RDS(on) vs. junction temperature (typical value) Iq / (Iq @ 1 kHz) R DS(ON) / (RD S(ON) @ 25 °C ) 1.7 1.8 1.6 1.6 1.5 1.4 1.4 1.3 1.2 1.2 1.1 1.0 1.0 0.8 0.9 0 20 40 60 80 100 0 20 40 60 80 100 120 140 Tj [°C] fSW [kHz] AM02574v1 Doc ID 018997 Rev 2 AM02575v1 27/33 Electrical characteristics curves L6235Q Figure 29. Typical low-side RDS(on) vs. supply Figure 30. Typical drain-source diode forward voltage ON characteristic R DS(ON) [Ω] ISD [A] 0.300 3.0 0.296 2.5 Tj = 25°C Tj = 25°C 0.292 2.0 0.288 1.5 0.284 1.0 0.280 0.5 0.276 0 5 10 15 VS [V] 20 25 30 0.0 700 900 1000 1100 1200 1300 VSD [mV] AM02576v1 28/33 800 Doc ID 018997 Rev 2 AM02577v1 L6235Q 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 8. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data (mm) Dim. Min. Typ. Max. 0.80 0.90 1.00 A1 0.02 0.05 A2 0.65 1.00 A3 0.25 A b 0.18 0.23 0.30 D 6.85 7.00 7.15 D2 4.95 5.10 5.25 E 6.85 7.00 7.15 E2 4.95 5.10 5.25 e 0.45 0.50 0.55 L 0.30 0.40 0.50 ddd 0.08 Doc ID 018997 Rev 2 29/33 Package mechanical data L6235Q Figure 31. VFQFPN48 (7 x 7 x 1.0 mm) package outline 30/33 Doc ID 018997 Rev 2 L6235Q 10 Order codes Order codes Table 9. Ordering information Order codes Package L6235Q Packaging Tray QFN48 7 x 7 x 1.0 mm L6235QTR Tape and reel Doc ID 018997 Rev 2 31/33 Revision history 11 L6235Q Revision history Table 10. 32/33 Document revision history Date Revision Changes 30-Jul-2011 1 First release 28-Nov-2011 2 Document moved from preliminary to final datasheet Doc ID 018997 Rev 2 L6235Q Please Read Carefully: Information in this document is provided solely in connection with ST products. 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